Chopper-Stabilized, Two-Wire Hall-Effect Switches

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1 FETURES N ENEFITS E-Q100 automotive qualified High-speed, 4-phase chopper stabilization Low switchpoint drift throughout temperature range Low sensitivity to thermal and mechanical stresses On-chip protection Supply transient protection Reverse-battery protection On-board voltage regulator 3 to 24 V operation Solid-state reliability Robust EM and ES performance Industry-leading ISO performance through use of proprietary, 40 V clamping structures ontinued on the next page Packages 3-pin SOT23-W 2 mm 3 mm 1 mm (suffix LH) pproximate footprint 3-pin ultramini SIP 1.5 mm 4 mm 3 mm (suffix U) 2-pin ultramini SIP 1.5 mm 4 mm 4 mm (suffix U) ESRIPTION The 1150, 1152, 1153, 1155, comprise a family of two-wire, unipolar, Hall-effect switches, which are factory-trimmed to optimize magnetic switchpoint accuracy. These devices are produced on the llegro advanced imos wafer fabrication process, which implements a patented high-frequency, 4-phase, chopper-stabilization technique. This technique achieves magnetic stability over the full operating temperature range, and eliminates offsets inherent in devices with a single Hall element that are exposed to harsh application environments. The 115x family has a number of automotive applications. These include sensing seat track position, seat belt buckle presence, hood/trunk latching, and shift selector position. Two-wire unipolar switches are particularly advantageous in cost-sensitive applications because they require one less wire for operation versus the more traditional open-collector output switches. dditionally, the system designer inherently gains diagnostics because there is always output current flowing, which should be in either of two narrow ranges. ny current level not within these ranges indicates a fault condition. ll family members are offered in three package styles. The LH is a SOT-23W style, miniature, low profile package for surface-mount applications. The U is a 3-pin, ultra-mini, single inline package (SIP) for through-hole mounting. The U is a 2-pin, ultra-mini, single inline package (SIP) for through-hole mounting. ll three packages are lead (Pb) free, with 100% matte-tin leadframe plating. U package only V+ V 0. 1 µf Regulator To all subcircuits LH & U package only µf ynamic Offset ancellation lock/logic mp Sample and Hold Low-Pass Filter Schmitt Trigger Polarity GN GN U package only Functional lock iagram 1152-S, Rev. 10

2 Features and enefits (continued) Extended Operating mbient temperature range, 40 to 150 U package with integrated 0.1 µf bypass capacitor Selection Guide Part Number Packing Package 1150LLHLX-T 13-in. reel, pieces/reel 3-pin SOT23W surface mount 1150LU-T ulk, 500 pieces/bag 3-pin SIP through hole 1152LLHLX-T 13-in. reel, pieces/reel 3-pin SOT23W surface mount 1152LU-T ulk, 500 pieces/bag 3-pin SIP through hole 1152LUTN-T 13-in. reel, pieces/reel 2-pin SIP through hole 1153LLHLX-T 13-in. reel, pieces/reel 3-pin SOT23W surface mount 1153LU-T ulk, 500 pieces/bag 3-pin SIP through hole 1153LUTN-T 13-in. reel, pieces/reel 2-pin SIP through hole 1155LLHLX-T 13-in. reel, pieces/reel 3-pin SOT23W surface mount 1155LU-T ulk, 500 pieces/bag 3-pin SIP through hole 1155LUTN-T 13-in. reel, pieces/reel 2-pin SIP through hole 1156LLHLX-T 13-in. reel, pieces/reel 3-pin SOT23W surface mount 1156LU-T ulk, 500 pieces/bag 3-pin SIP through hole 1156LUTN-T 13-in. reel, pieces/reel 2-pin SIP through hole 1157LLHLX-T 13-in. reel, pieces/reel 3-pin SOT23W surface mount 1157LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount 1157LU-T ulk, 500 pieces/bag 3-pin SIP through hole 1158LLHLX-T 13-in. reel, pieces/reel 3-pin SOT23W surface mount 1158LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount 1158LU-T ulk, 500 pieces/bag 3-pin SIP through hole Output (I ) in South Polarity Field Supply urrent at I (L) (m) Low 2 to 5 Low 5 to 6.9 High 5 to 6.9 Low 5 to 6.9 High 5 to 6.9 Low High Magnetic Operate Point, OP (G) 50 to to 60 2 to 5 20 to 80 2

3 SPEIFITIONS bsolute Maximum Ratings haracteristic Symbol Notes Rating Unit Forward Supply Voltage V 28 V Reverse Supply Voltage V R 18 V Magnetic Flux ensity Unlimited G Operating mbient Temperature T Range L 40 to 150 º Maximum Junction Temperature T J (max) 165 º Storage Temperature T stg 65 to 170 º Pin-Out iagrams and Terminal List Table 3 N 1 2 LH Package U Package LH and U Terminal List Table Number LH package Name U package Function 1 V V Input power supply 2 N GN LH package: no connection, it is highly recommended that this pin be tied to GN U package: ground terminal 3 GN GN Ground terminal U Terminal List Table Number Name Function 1 V Input power supply 2 GN Ground terminal 1 2 U Package 3

4 ELETRIL HRTERISTIS: valid at T = 40 to 150, T J < T J (max), YP = 0.01 µf, through operating supply voltage range, unless otherwise noted haracteristics Symbol Test onditions Min. Typ. Max. Unit Supply Voltage 1,2 V Operating, T J V I (L) 1150, 1157 > OP m 1158 < RP 1152, 1155 > OP m Supply urrent 1153, 1156 < RP I (H) 1150, 1152, 1155, 1157 < RP 1153, 1156, 1158 > OP m Supply Zener lamp Voltage V Z(sup) I (L) (max) + 3 m, T = V Supply Zener lamp urrent I Z(sup) V Z(sup) = 28 V I (L) (max) + 3 m m Reverse Supply urrent I R V R = 18 V 1.6 m Output Slew Rate 3 di/dt LH and U No bypass capacitor, capacitance of probe S = 20 pf 90 m / µs Integrated bypass capacitor, U 0.22 m / µs capacitance of probe S = 20 pf hopping Frequency f c 700 khz 1150, 1152, > OP + 10 G 1155, 1157 Power-Up Time 4,5 t on 25 µs 1153, 1156, < 1158 RP 10 G Power-Up State 2,4,6,7 POS t on < t on (max), V slew rate > 25 mv / µs I (H) 1 V represents the generated voltage between the V pin and the GN pin. 2 The V slew rate must exceed 600 mv/ms from 0 to 3 V. slower slew rate through this range can affect device performance. 3 Measured without bypass capacitor between V and GN. Use of a bypass capacitor results in slower current change. 4 Power-Up Time is measured without and with bypass capacitor of 0.01 µf. dding a larger bypass capacitor would cause longer Power-Up Time. 5 Guaranteed by characterization and design. 6 Power-Up State as defined is true only with a V slew rate of 25 mv / µs or greater. 7 For t > t on and RP < < OP, Power-Up State is not defined. MGNETI HRTERISTIS 1: Valid at T = 40 to 150, T J < T J (max), unless otherwise noted haracteristics Symbol Min. Typ. Max. Unit 2 Magnetic Operating Point OP 1155, G 1150, 1152, G 1157, G Magnetic Release Point RP 1155, G 1150, 1152, G 1157, G Hysteresis HYS 5 30 G 1 Relative values of use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north magnetic polarity; therefore greater values indicate a stronger south polarity field (or a weaker north polarity field, if present). 2 1 G (gauss) = 0.1 mt (millitesla). 4

5 THERML HRTERISTIS: may require derating at maximum conditions; see application information haracteristic Symbol Test onditions* Value Unit Package LH, on 1-layer P with copper limited to solder pads 228 º/W Package Thermal Resistance R θj Package LH, on 2-layer P with in. 2 of copper area each side 110 º/W Package U, on 1-layer P with copper limited to solder pads 165 º/W Package U, on 1-layer P with copper limited to solder pads 213 º/W *dditional thermal information available on the llegro website LH and Power U erating Power erating urve urve U Power erating urve Maximum llowable V (V) layer P, Package LH (R θj = 110 º/W) 1-layer P, Package U (R θj = 165 º/W) 1-layer P, Package LH (R θj = 228 º/W) V (max) V (min) Temperature (º) Power issipation, P (mw) LH and U Power Power issipation versus mbient Temperature layer P, Package LH (R θj = 110 º/W) 1-layer P, Package U (R θj = 165 º/W) 1-layer P, Package LH (R θj = 228 º/W) Temperature ( ) U Power issipation versus mbient Temperature 5

6 HRTERISTI PERFORMNE 1152/1153/1155/1156 verage Supply urrent (Low) versus Temperature /1153/1155/1156 verage Supply urrent (Low) versus Supply Voltage 7.0 Supply urrent, I (L) (m) V = 24 V Supply urrent, I (L) (m) T = 150 T = 40 T = /1157/1158 verage Supply urrent (Low) versus Temperature /1157/1158 verage Supply urrent (Low) versus Supply Voltage 5.0 Supply Voltage, V (V) Supply urrent, I (L) (m) V = 24 V Supply urrent, I (L) (m) T = 150 T = 25 T = /1152/1153/1155/1156/1157/1158 verage Supply urrent (High) versus Temperature /1152/1153/1155/1156/1157/1158 verage Supply urrent (High) versus Supply Voltage 17 Supply Voltage, V (V) Supply urrent, I (H) (m) V = 24 V Supply urrent, I (H) (m) T = 40 T = 150 T = Supply Voltage, V (V) 6

7 /1152/1153 verage Operate Point versus Temperature 1155/1156 verage Operate Point versus Temperature 60 pplied Flux ensity at Operate Point, OP (G) V = 24 V pplied Flux ensity at Operate Point, OP (G) V = 24 V /1152/1153 verage Release Point versus Temperature /1156 verage Release Point versus Temperature 55 pplied Flux ensity at Release Point, RP (G) V = 24 V pplied Flux ensity at Release Point, RP (G) V = 24 V /1152/1153/1155/1156/1157/1158 verage Switchpoint Hysteresis versus Temperature /1152/1153/1155/1156/1157/ /1156 verage Switchpoint Hysteresis versus Temperature pplied Flux ensity at Switchpoint Hysteresis, HYS (G) V = 24 V pplied Flux ensity at Switchpoint Hysteresis, HYS (G) V = 24 V

8 FUNTIONL ESRIPTION The 1150, 1152, 1155, and 1157 output, I, switches low after the magnetic field at the Hall sensor I exceeds the operate point threshold, OP. When the magnetic field is reduced to below the release point threshold, RP, the device output goes high. This is shown in Figure 1, panel. In the case of the reverse output polarity, as in the 1153, 1156, and 1158, the device output switches high after the magnetic field at the Hall sensor I exceeds the operate point threshold, OP. When the magnetic field is reduced to below the release point threshold, RP, the device output goes low (panel ). The difference between the magnetic operate and release points is called the hysteresis of the device, HYS. This built-in hysteresis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise. I+ I (H) I+ I (H) I Switch to High Switch to Low I Switch to Low Switch to High 0 RP OP + I (L) 0 RP OP + I (L) HYS () Hysteresis curve for 1150, 1152, 1155, and 1157 HYS () Hysteresis curve for 1153, 1156, and 1158 Figure 1: lternative Switching ehaviors vailable in the 115x evice Family. On the horizontal axis, the + direction indicates increasing south polarity magnetic field strength, and the direction indicates decreasing south polarity field strength (including the case of increasing north polarity). 8

9 V+ V R SENSE 115x 0.1 µf YP 0.01 µf V+ 115x V YP GN GN 0.1 µf 0.01 µf EU R SENSE Package U Only Package U Only GN GN Package LH & U Only () Low side sensing () High side sensing Figure 2: Typical pplication ircuits hopper Stabilization Technique When using Hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the Hall element. This voltage is disproportionally small relative to the offset that can be produced at the output of the Hall sensor I. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. hopper stabilization is a unique approach used to minimize Hall offset on the chip. The patented llegro technique, namely ynamic Quadrature Offset ancellation, removes key sources of the output drift induced by thermal and mechanical stresses. This offset reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the magnetic fieldinduced signal in the frequency domain, through modulation. The subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at base band, while the offset becomes a high-frequency signal. The magnetic-sourced signal then can pass through a low-pass filter, while the modulated offset is suppressed. The chopper stabilization technique uses a 350 khz high frequency clock. For demodulation process, a sample and hold technique is used, where the sampling is performed at twice the chopper frequency. This high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. This approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent Hall output voltages and precise recoverability after temperature cycling. This technique is made possible through the use of a imos process, which allows the use of low-offset, low-noise amplifiers in combination with high-density logic integration and sampleand-hold circuits. Regulator lock/logic Hall Element mp Sample and Hold Low-Pass Filter Figure 3: hopper Stabilization ircuit (ynamic Quadrature Offset ancellation) 9

10 Power erating The device must be operated below the maximum junction temperature of the device, T J (max). Under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors affecting operating T J. (Thermal data is also available on the llegro MicroSystems Web site.) The Package Thermal Resistance, R θj, is a figure of merit summarizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. Its primary component is the Effective Thermal onductivity, K, of the printed circuit board, including adjacent devices and traces. Radiation from the die through the device case, R θj, is relatively small component of R θj. mbient air temperature, T, and air motion are significant external factors, damped by overmolding. The effect of varying power levels (Power issipation, P ), can be estimated. The following formulas represent the fundamental relationships used to estimate T J, at P. P = V IN I IN (1) ΔT = P R θj (2) T J = T + ΔT (3) For example, given common conditions such as: T = 25, V = 12 V, I = 4 m, and R θj = 140 /W, then: P = V I = 12 V 4 m = 48 mw ΔT = P R θj = 48 mw 140 /W = 7 T J = T + ΔT = = 32 worst-case estimate, P (max), represents the maximum allowable power level (V (max), I (max)), without exceeding T J (max), at a selected R θj and T. Example: Reliability for V at T = 150, package U, using a low-k P. Observe the worst-case ratings for the device, specifically: R θj = 165 /W, T J (max) = 165, V (max) = 24 V, and I (max) = 17 m. alculate the maximum allowable power level, P (max). First, invert equation 3: ΔT max = T J (max) T = = 15 This provides the allowable increase to T J resulting from internal power dissipation. Then, invert equation 2: P (max) = ΔT max R θj = /W = 91 mw Finally, invert equation 1 with respect to voltage: V (est) = P (max) I (max) = 91 mw 17 m = 5 V The result indicates that, at T, the application and device can dissipate adequate amounts of heat at voltages V (est). ompare V (est) to V (max). If V (est) V (max), then reliable operation between V (est) and V (max) requires enhanced R θj. If V (est) V (max), then operation between V (est) and V (max) is reliable under these conditions. 10

11 PKGE OUTLINE RWINGS For Reference Only Not for Tooling Use (Reference WG-2840) imensions in millimeters NOTTO SLE imensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown ± MIN REF 0.25 S 0.95 randed Face Seating Plane Gauge Plane P Layout Reference View 8X 10 REF 1.00 ±0.13 NNN 0.95 S 0.40 ± Standard randing Reference View N = Last three digits of device part number ctive rea epth, 0.28 mm Reference land pattern layout; all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and P layout tolerances randing scale and appearance at supplier discretion Hall elements, not to scale Figure 4: Package LH, 3-Pin SOT23W 11

12 For Reference Only Not for Tooling Use (Reference WG-9013) imensions in millimeters NOT TO SLE imensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown ±0.05 E E E 2 X 10 randed Face Mold Ejector Pin Indent MX 0.79 REF NOM NNN ± Standard randing Reference View = Supplier emblem N = Last three digits of device part number E ambar removal protrusion (6X) Gate and tie bar burr area ctive rea epth, 0.50 mm REF randing scale and appearance at supplier discretion Hall element, not to scale Figure 5: Package U, 3-Pin SIP 12

13 For Reference Only Not for Tooling Use (Reference WG-9070) imensions in millimeters imensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown X 10 E ± E E Mold Ejector Pin Indent randed Face 0.85 ± NNN YYWW LLLL 4 X 2.50 REF 4 X 0.85 REF 0.25 REF 0.30 REF REF ±0.10 Standard randing Reference View = Supplier emblem N = Last three digits of device part number Y = Last 2 digits of year of manufacture W = Week of manufacture L = Lot number 1.00 ±0.10 ambar removal protrusion (8X) ±0.10 Gate and tie bar burr area 4 X 7.37 REF ctive rea epth, 0.38 mm REF 1.80 ±0.10 E randing scale and appearance at supplier discretion Hall element; not to scale F Thermoplastic Molded Lead ar for alignment during shipment 0.38 REF 4 X 0.85 REF 0.25 REF 0.85 ± F ±0.05 Figure 6: Package U, 2-Pin SIP 13

14 Revision History Revision Revision ate escription of Revision 7 May 22, 2014 dded U Package 8 October 2, 2014 Revised U packge drawing and reformatted document. 9 March 2, 2015 Updated branding info on package drawing 10 September 21, 2015 orrected LH package ctive rea epth value; added E-Q100 qualification under Features and enefits opyright 2015, reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. efore placing an order, the user is cautioned to verify that the information being relied upon is current. llegro s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of llegro s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: 14