Absolute Maximum Ratings Max.

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1 PD 97049B IRF52SPbF IRF52LPbF HEXFET Power MOSFET Advanced Process Technoogy Utra Low OnResistance 50 C Operating Temperature Fast Switching Repetitive Avaanche Aowed up to Tjmax Some Parameters are Different from IRF52S/L PChanne LeadFree G D S V DSS = V R DS(on) = 60mΩ I D = 38A Description Features of this design are a 50 C junction operating temperature, fast switching speed and improved repetitive avaanche rating. These features combine to make this design an extremey efficient and reiabe device for use in a wide variety of other appications. D S D G D 2 Pak IRF52SPbF D S D G TO262 IRF52LPbF G D S Gate Drain Source Absoute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 38 A I T C = C Continuous Drain Current, V 24 I DM Pused Drain Current c 40 P A = 25 C Maximum Power Dissipation 3. W P C = 25 C Maximum Power Dissipation Linear Derating Factor 70.3 W/ C V GS GatetoSource Votage ± 20 V E AS Singe Puse Avaanche Energy d 20 mj I AR Avaanche Current c 23 A E AR Repetitive Avaanche Energy c 7 mj dv/dt Peak Diode Recovery dv/dt e 7.4 V/ns T J Operating Junction and 55 to 50 C Storage Temperature Range T STG 300 (.6mm from case ) Sodering Temperature, for seconds Therma Resistance Parameter Typ. Max. Units R θjc JunctiontoCase 0.75 C/W R θja JunctiontoAmbient (PCB Mount, steady state) g /04/09

2 Eectrica T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units V (BR)DSS DraintoSource Breakdown Votage V ΒV DSS / T J Breakdown Votage Temp. Coefficient 0. V/ C R DS(on) Static DraintoSource OnResistance 60 mω V GS = V, I D = 38A f V GS(th) Gate Threshod Votage V V DS = V GS, I D = 250µA gfs Forward Transconductance 9.5 S V DS = 50V, I D = 23A I DSS DraintoSource Leakage Current 50 µa V DS = V, V GS = 0V 250 V DS = 80V, V GS = 0V, T J = 25 C I GSS GatetoSource Forward Leakage na V GS = 20V GatetoSource Reverse Leakage V GS = 20V Q g Tota Gate Charge nc I D = 23A Q gs GatetoSource Charge V DS = 80V Q gd GatetoDrain ("Mier") Charge 8 20 V GS = V f t d(on) TurnOn Deay Time 4 ns V DD = 50V t r Rise Time 63 I D = 23A t d(off) TurnOff Deay Time 72 R G = 2.4Ω t f Fa Time 55 V GS = V f L D Interna Drain Inductance 4.5 nh Between ead, 6mm (0.25in.) L S Interna Source Inductance 7.5 from package and center of die contact C iss Input Capacitance 2780 pf V GS = 0V C oss Output Capacitance 800 V DS = 25V C rss Reverse Transfer Capacitance 430 SourceDrain Ratings and Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 38 Conditions V GS = 0V, I D = 250µA Reference to 25 C, I D = ma ƒ =.0MHz, See Fig. 5 Conditions MOSFET symbo (Body Diode) A showing the I SM Pused Source Current 40 integra reverse (Body Diode)Ãc pn junction diode. V SD Diode Forward Votage.6 V T J = 25 C, I S = 23A, V GS = 0V f t rr Reverse Recovery Time ns T J = 25 C, I F = 23A, V DD = 25V Q rr Reverse Recovery Charge nc di/dt = A/µs f t on Forward TurnOn Time Intrinsic turnon time is negigibe (turnon is dominated by LSLD) Notes: Repetitive rating; puse width imited by max. junction temperature. ( See fig. ) Starting T J = 25 C, L = 0.46mH R G = 25Ω, I AS = 23A. (See Figure 2) ƒ I SD 23A, di/dt 650A/µs, V DD V (BR)DSS, T J 50 C. Puse width 300µs; duty cyce 2%. When mounted on " square PCB (FR4or G Materia). For recommended footprint and sodering techniques refer to appication note #AN

3 I D, DraintoSource Current (A) R DS(on), DraintoSource On Resistance (Normaized) I D, DraintoSource Current (A) I D, DraintoSource Current (A) VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 4.5V 60µs PULSE WIDTH Tj = 25 C V DS, DraintoSource Votage (V) 60µs PULSE WIDTH Tj = 50 C V DS, DraintoSource Votage (V) Fig. Typica Output Characteristics Fig 2. Typica Output Characteristics T J = 25 C 2.0 I D = 38A V GS = V T J = 50 C V DS = 50V 60µs PULSE WIDTH V GS, GatetoSource Votage (V) T J, Junction Temperature ( C) Fig 3. Typica Transfer Characteristics Fig 4. Normaized OnResistance vs. Temperature 3

4 I SD, Reverse Drain Current (A) I D, DraintoSource Current (A) C, Capacitance(pF) V GS, GatetoSource Votage (V) 00 0 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd I D = 23A V DS = 80V V DS = 50V V DS = 20V C iss 6.0 C oss C rss V DS, DraintoSource Votage (V) Q G, Tota Gate Charge (nc) Fig 5. Typica Capacitance vs. DraintoSource Votage Fig 6. Typica Gate Charge vs. GatetoSource Votage OPERATION IN THIS AREA LIMITED BY R DS (on) T J = 50 C T J = 25 C V GS = 0V V SD, SourcetoDrain Votage (V) Tc = 25 C Tj = 50 C Singe Puse µsec msec msec V DS, DraintoSource Votage (V) Fig 7. Typica SourceDrain Diode Forward Votage Fig 8. Maximum Safe Operating Area 4

5 I D, Drain Current (A) V DS R D T C, Case Temperature ( C) R G V GS V Puse Width µs Duty Factor 0. % D.U.T. Fig a. Switching Time Test Circuit V GS t d(on) t r t d(off) t f % 90% V DS V DD Fig 9. Maximum Drain Current vs. Case Temperature Fig b. Switching Time Waveforms D = R R 2 R 3 R R 2 R 3 τ J τ J τ τ τ 2 τ 3 τ 2 τ 3 Ci= τi/ri Ci= τi/ri τ C τ Ri ( C/W) τι (sec) Therma Response ( Z thjc ) SINGLE PULSE ( THERMAL RESPONSE ) Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc 0.00 E006 E t, Rectanguar Puse Duration (sec) Fig. Maximum Effective Transient Therma Impedance, JunctiontoCase 5

6 E AS, Singe Puse Avaanche Energy (mj) V DS L 500 R G 20V tp D.U.T IAS 0.0Ω DRIVER V DD A I D TOP 8.7A 4A BOTTOM 23A 300 Fig 2a. Uncamped Inductive Test Circuit I AS 5V Starting T J, Junction Temperature ( C) tp Fig 3. Maximum Avaanche Energy vs. Drain Current V (BR)DSS Fig 2b. Uncamped Inductive Waveforms Current Reguator Same Type as D.U.T. V Q G 2V.2µF 50KΩ.3µF Q GS Q GD D.U.T. V DS V G V GS 3mA Charge I G I D Current Samping Resistors Fig 4a. Basic Gate Charge Waveform Fig 4b. Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T* ƒ Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer V GS R G dv/dt controed by R G I SD controed by Duty Factor "D" D.U.T. Device Under Test V DD * Reverse Poarity of D.U.T for PChanne Driver Gate Drive Period P.W. D = P.W. Period [ ] *** V GS =V D.U.T. I SD Waveform Reverse Recovery Current ReAppied Votage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Forward Drop V DD [ ] Rippe 5% I SD [ ] *** V GS = 5.0V for Logic Leve and 3V Drive Devices Fig 5. For PChanne HEXFETS 7

8 D 2 Pak (TO263AB) Package Outine Dimensions are shown in miimeters (inches) D 2 Pak (TO263AB) Part Marking Information 7,6,6$,5)6:,7 /27&2'(,7(5$7,2$/ $66(0%/('2:: 5(&7,),(5,7($66(0%/</,(/ /2*2 $66(0%/< /27&2'( )6 3$5780%(5 '$7(&2'( <($5 :((. /,(/ 25,7(5$7,2$/ 5(&7,),(5 /2*2 $66(0%/< /27&2'( )6 3$5780%(5 '$7(&2'( 3 '(6,*$7(6/($')5(( 352'8&7237,2$/ <($5 :((. $ $66(0%/<6,7(&2'( Note: For the most current drawing pease refer to IR website at 8

9 TO262 Package Outine Dimensions are shown in miimeters (inches) TO262 Part Marking Information (;$03/( 7,6,6$,5// /27&2'( $66(0%/('2::,7($66(0%/</,(&,7(5$7,2$/ 5(&7,),(5 /2*2 $66(0%/< /27&2'( 3$5780%(5 '$7(&2'( <($5 :((. /,(& 25,7(5$7,2$/ 5(&7,),(5 /2*2 $66(0%/< /27&2'( 3$5780%(5 '$7(&2'( 3 '(6,*$7(6/($')5(( 352'8&7237,2$/ <($5 :((. $ $66(0%/<6,7(&2'( Note: For the most current drawing pease refer to IR website at 9

10 D 2 Pak (TO263AB) Tape & Ree Information Dimensions are shown in miimeters (inches) TRR.60 (.063).50 (.059) 4. (.6) 3.90 (.53).60 (.063).50 (.059) (.045) (.035) FEED DIRECTION TRL.85 (.073).65 (.065).60 (.457).40 (.449) 5.42 (.609) 5.22 (.60) (.957) (.94).90 (.429).70 (.42) 6. (.634) 5.90 (.626).75 (.069).25 (.049) 4.72 (.36) 4.52 (.78) FEED DIRECTION 3.50 (.532) 2.80 (.504) (.079) (.94) (4.73) MAX (2.362) MIN. NOTES :. COMFORMS TO EIA CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLANGE OUTER EDGE (.039) (.96) (.97) MAX. 4 Note: For the most current drawing pease refer to IR website at Data and specifications subject to change without notice. This product has been designed and quaified for the Industria market. Quaification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., E Segundo, Caifornia 90245, USA Te: (3) TAC Fax: (3) Visit us at for saes contact information. 08/09

V DSS. 30V Q1 GS = 10V 6.4A Q2 GS = 10V 9.7A

V DSS. 30V Q1 GS = 10V 6.4A Q2 GS = 10V 9.7A PD 9794A IRF7902PbF Appications Dua SO8 MOSFET for POL Converters in Notebook Computers, Servers, Graphics Cards, Game Consoes and SetTop Box V DSS HEXFET Power MOSFET R DS(on) max 30V Q 22.6m:@V GS =