TOP VIEW C DP2 GND C GC2 C DC2 V EE2 V DD V SS V EE1 C DC1 C GC1 GND C DP1

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1 19-413; Rev 0; /0 EVALUATION KIT AVAILABLE General Description The integrated circuits generate high-voltage, high-frequency, unipolar or bipolar pulses from low-voltage logic inputs. These dual pulsers feature independent logic inputs, independent high-voltage pulser outputs with active clamps and independent high-voltage supply inputs. The feature a 9Ω output for the high-voltage outputs, and a 7Ω for the active clamp. The high-voltage outputs are guaranteed to provide 1.3A output current. All devices use three logic inputs per channel to control the positive and negative pulses and active clamp. Also included are two independent enable inputs. Disabling EN ensures the output MOSFETs are not accidentally turned on during fast power-supply ramping. This allows for faster ramp times and smaller delays between pulsing modes. A low-power shutdown mode reduces power consumption to less than 1µA. All digital inputs are CMOS compatible. The MAX4 includes clamp output overvoltage protection, while the MAX411 features both pulser output and clamp output overvoltage protection. The MAX4 does not provide overvoltage protection. See the Ordering Information/Selector Guide. The are available in a 5-pin (7mm x 7mm), TQFN exposed-pad package and are specified over the 0 C to +70 C commercial temperature range. Ultrasound Medical Imaging Cleaning Equipment PART Ordering Information/ Selector Guide PROTECTED OUTPUTS OUTPUT CURRENT (A) PIN- PACKAGE MAX4CTN+ OCP_, OCN_ TQFN-EP** MAX411CTN+ OCP_, OCN_, OP_, ON_ Applications Flaw Detection Piezoelectric Drivers Test Instruments TQFN-EP** MAX4CTN+* None TQFN-EP** Note: All devices are specified over the 0 C to +70 C operating temperature range. +Denotes a lead-free/rohs-compliant package. *Future product contact factory for availability. **EP = Exposed pad. Features ly Integrated, -Voltage, -Frequency Unipolar/Bipolar Pulser 9Ω Output Impedance and 1.3A (min) Output Current 7Ω Active Clamp Pulser and Clamp Overvoltage Protection (MAX4/MAX411) 0 to +0V Unipolar or ±1V Bipolar Outputs Matched Rise/Fall Times and Matched Propagation Delays CMOS-Compatible Logic Inputs 5-Pin, 7mm x 7mm, TQFN Package TOP VIEW C DP V CC C GC C DC V EE V EE1 C DC1 C GC1 V CC1 C DP CGP MAX4 MAX411 MAX4 TQFN 7mm x 7mm Pin Configuration CGP1 VPP VPP1 VPP VPP1 OP OP1 OCP OCP1 *EP = EXPOSED PAD, CONNECT EP TO. Warning: The are designed to operate with high voltages. Exercise caution. + OCN OCN1 ON ON1 VNN VNN1 VNN *EP VNN1 CGN CGN1 CDN CDN1 7 V CC INN 5 INC 4 INP 3 EN A 1 SHDN 0 EN1 19 INP1 1 INC INN1 V CC1 15 Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS (Voltages referenced to.) Logic Supply Voltage V to +V V CC_ Output Driver Positive Supply Voltage V to +15V V EE_ Output Driver Negative Supply Voltage...-15V to +0.3V V PP_ Positive Supply Voltage V to +30V V NN_ Negative Supply Voltage...-30V to +0.3V Voltage...(V PP_ - 50V) to V NN_ V PP1 - V NN1, V PP - V NN Supply Voltage...-0.V to +50V INP_, INN_, INC_, EN_, SHDN Logic Input V to + 0.3V O P_, O CP_, O LN_, O N_...(-0.3V + V NN_ ) to (-0.3V to V PP_ ) C GN_ Voltage...(-0.3V + V NN_ ) to (+15V + V NN_ ) C GP_ Voltage...(+0.3V + V PP_ ) to (-15V + V PP_ ) C GC_ Voltage...-15V to +15V ELECTRICAL CHARACTERISTICS C DC_, C DP_, C DN_ Voltage V to V CC_ Peak Current per Output Channel...3.0A Continuous Power Dissipation (T A = +70 C) (Note 1) 5-Pin TQFN (derate 40mW/ C above +70 C)...300mW Thermal Resistance (Note ) θ JA...5 C/W θ JC...0. C/W Operating Temperature Range...0 C to +70 C Junction Temperature C Storage Temperature Range...-5 C to +150 C Lead Temperature (soldering, s) C Note 1: This specification is based on the thermal characteristic of the package, the maximum junction temperature, and the setup described by JEDEC 51. The maximum power dissipation for the might be limited by the thermal protection included in the device. Note : Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ( = +.7V to +V, V CC_ = +4.75V to +.V, V EE_ = -.V to -4.75V, V NN_ = -00V to 0, V PP_ = 0 to (V NN_ + 00V), the lower of V NN1 or V NN, T A = T J = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5 C.) (Note 3) (See Figures, 9, and.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY (, V CC_, V EE _, V PP_, V NN_ ) Logic Supply Voltage V Positive Drive Supply Voltage V CC_ V Negative Drive Supply Voltage V EE_ V -Side Supply Voltage V PP_ 0 V NN_ + 0 Low-Side Supply Voltage V NN_ V V PP_ - V NN_ Supply Voltage 0 +0 V SUPPLY CURRENT (Single Channel) V INN_ /V INP_ = 0, V SHDN = 0 1 Supply Current I DD VEN_ =, V SHDN =, V INC_ = 0 or, V INN_ = V INP_, f = 5MHz V CC_ Supply Current I CC_ 0 00 V SHDN = 0, CH1 and CH 1 V EN_ =, V SHDN =, CH1 and CH V EN_ =, V SHDN =, V INC_ = 0 or, V INN_ = V INP_, f = 5MHz, V CC_ = 5V, = 3V, only one channel switching V EN_ =, V SHDN =, V INC_ = 0 or, V INN_ = V INP_, f = 5MHz, V CC_ = V, = 3V, only one channel switching 15 3 V µa µa ma

3 ELECTRICAL CHARACTERISTICS (continued) ( = +.7V to +V, V CC_ = +4.75V to +.V, V EE_ = -.V to -4.75V, V NN_ = -00V to 0, V PP_ = 0 to (V NN_ + 00V), the lower of V NN1 or V NN, T A = T J = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5 C.) (Note 3) (See Figures, 9, and.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS V EE_ Supply Current I EE_ V SHDN = 0, CH1 and CH 5 V EN_ =, V SHDN =, CH1 and CH 1 V EN_ =, V SHDN =, V INC_ = 0 or, V INN_ = V INP_, f = 5MHz, V EE_ = -5V, only one channel switching V EN_ =, V SHDN =, V INC_ = 0 or, V INN_ = V INP_, f = 5MHz, V EE_ = -V, only one channel switching V SHDN = 0, CH1 and CH 1 V EN_ =, V SHDN =, CH1 and CH V PP_ Supply Current I PP_ V E N _ = V D D, V SHDN = V D D, V I N C _ = 0 or V D D, V I N N _ = V I NP_, f = 5M H z, V P P _ = + 5V, V N N _ = - 5V, no l oad, onl y one channel sw i tchi ng V EN_ =, V SHDN =, V INC_ = 0 or, V PP_ = +0V, V NN_ = -0V, pulse repetition frequency = khz, f = MHz, 4 periods, no load, only one channel switching V SHDN = 0, CH1 and CH 1 V EN_ =, V SHDN =, CH1 and CH 40 0 V NN_ Supply Current I NN_ V E N _ = V D D, V SHDN = V D D, V I N C _ = 0 or V D D, V I N N _ = V I NP_, f = 5M H z, V N N _ = - 5V, V P P _ = + 5V, no l oad, onl y one channel sw i tchi ng V EN_ =, V SHDN =, V INC_ = 0 or, V PP_ = +0V, V NN_ = -0V, pulse repetition frequency = khz, f = MHz, 4 periods, no load, only one channel switching LOGIC INPUTS (EN_, SHDN, INN_, INP_, INC_) Low-Level Input Voltage V IL 0.5 x -Level Input Voltage V IH 0.75 x Logic-Input Capacitance C IN 5 pf Logic-Input Leakage I IN V IN = 0 or ±1 µa OUTPUT (OUT_) No load at OUT_ V NN_ V PP_ OUT_ Output-Voltage Range V OUT_ Unprotected outputs (see the Ordering Information/Selector Guide), 0mA load Protected outputs (see the Ordering Information/Selector Guide), 0mA load Low-Side Small-Signal Output Impedance V NN_ V NN_ V PP_ V PP_ -.5 I OP _ = - 0m A, V C C _ = + V ± 5%, D C - coup l ed 9 17 R OLS I OP _ = - 0m A, V C C _ = + 5V ± 5%, D C - coup l ed µa µa ma µa ma V V V Ω 3

4 ELECTRICAL CHARACTERISTICS (continued) ( = +.7V to +V, V CC_ = +4.75V to +.V, V EE_ = -.V to -4.75V, V NN_ = -00V to 0, V PP_ = 0 to (V NN_ + 00V), the lower of V NN1 or V NN, T A = T J = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5 C.) (Note 3) (See Figures, 9, and.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS -Side Small-Signal Output Impedance I OP _ = - 0m A, V C C _ = + V ± 5%, D C - coup l ed.5 17 R OHS I OP _ = - 0m A, V C C _ = + 5V ± 5%, D C - coup l ed 1 Low-Side Output Current I OL V CC_ = +V ±5%, V OUT_ - V NN_ = 0V 1.3 A -Side Output Current I OH V CC_ = +V ±5%, V OUT_ - V PP_ = 0V 1.3 A Off-Output Capacitance C O(OFF) connected together, OP_, ON_, OCP_ and OCN_ MAX4 45 V PP_ = +0V, V NN_ = -0V MAX Off-Output Leakage Current I LK V NN_ = -0V, V PP_ = 0V, EN_ = 0, OUT = -0V to +0V Low-Side Signal-Clamp Output Impedance -Side Signal-Clamp Output Impedance Low-Side Gate Short Impedance Ω pf µa I OC N _ = - 0m A, D C - coup l ed, V C C _ = + V ± 5%, V E E _ = - V C C _ 50 R CLS I OCN_ = -0mA, DC-coupled, V CC_ = +5V ±5%, V EE_ = -V CC_ 4 5 I OC P _ = - 0m A, D C - coup l ed, V C C _ = + V ± 5%, V E E _ = - V C C _ 50 R CHS I OCP_ = -0mA, DC-coupled, V CC_ = +5V ±5%, V EE_ = -V CC_ 3 5 R LSH V CC_ = +V ±5%, V EE_ = -V CC_, I CGN = ma, EN_ = 0 Ω Ω 0 Ω V CC_ = +V ±5%, V EE_ = -V CC_, I CGN = ma, EN_ = kω -Side Gate Short Impedance R HSH V CC_ = +V ±5%, V EE_ = -V CC_, I CGN = ma, EN_ = 0 0 Ω V CC_ = +V ±5%, V EE_ = -V CC_, I CGN = ma, EN_ = kω THERMAL SHUTDOWN Thermal Shutdown T SHDN Junction temperature rising 150 C Thermal-Shutdown Hysteresis 0 C DYNAMIC CHARACTERISTICS (R L = 0Ω, C L = 0pF, unless otherwise noted) Logic Input to Output Rise Propagation Delay Logic Input to Output Fall Propagation Delay Logic Input to Output Rise Propagation Delay Logic Input to Output Fall Propagation Delay Logic Input to Output-Rise Propagation Delay Clamp t PLH V CC_ = +V, V PP_ = +5V, V NN_ = -5V, Figure 4 15 ns t PHL V CC_ = +V, V PP_ = +5V, V NN_ = -5V, Figure 4 15 ns t POH V CC_ = +V, V PP_ = +5V, V NN_ = -5V, Figure 4 15 ns t POL V CC_ = +V, V PP_ = +5V, V NN_ = -5V, Figure 4 15 ns t PLO V CC_ = +V, V PP_ = +5V, V NN_ = -5V, Figure 4 15 ns 4

5 ELECTRICAL CHARACTERISTICS (continued) ( = +.7V to +V, V CC_ = +4.75V to +.V, V EE_ = -.V to -4.75V, V NN_ = -00V to 0, V PP_ = 0 to (V NN_ + 00V), the lower of V NN1 or V NN, T A = T J = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5 C.) (Note 3) (See Figures, 9, and.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Logic Input to Output-Fall Propagation Delay Clamp t PHO V CC_ = +V, V PP_ = +5V, V NN_ = -5V, Figure 4 15 ns OUT_ Rise Time ( to V PP_ ) t R0P V P P _ = + 0V, V N N _ = - 0V, V C C _ = + V ± 5%, V E E _ = - V C C _, Fi g ur e 4 OUT_ Rise Time (V NN_ to ) t RN0 V P P _ = + 0V, V N N _ = - 0V, V C C _ = + V ± 5%, V E E _ = - V C C _, Fi g ur e 4 OUT_ Rise Time (V NN_ to V PP_ ) t RNP V P P _ = + 0V, V N N _ = - 0V, V C C _ = + V ± 5%, V E E _ = - V C C _, Fi g ur e 4 OUT_ Fall Time ( to V NN_ ) t F0N V P P _ = + 0V, V N N _ = - 0V, V C C _ = + V ± 5%, V E E _ = - V C C _, Fi g ur e 4 OUT_ Fall Time (V PP_ to ) t FP0 V P P _ = + 0V, V N N _ = - 0V, V C C _ = + V ± 5%, V E E _ = - V C C _, Fi g ur e 4 OUT_ Fall Time (V PP_ to V NN_ ) t FPN V P P _ = + 0V, V N N _ = - 0V, V C C _ = + V ± 5%, V E E _ = - V C C _, Fi g ur e 4 OUT Enable Time from EN (Figure 5) OUT Disable Time from EN (Figure 5) Clamp Enable Time from INC (Figure ) Clamp Disable Time from INC (Figure ) Short Enable Time from EN (Figure 7) Short Disable Time from EN (Figure 7) 9 0 ns ns.5 35 ns 9 0 ns ns.5 35 ns V CC_ = +V ± 5%, V EE_ = -V CC_ 0 t EN V CC_ = +5V ± 5%, V EE_ = -V CC_ 150 V CC_ = +V ± 5%, V EE_ = -V CC_ 0 t DI V CC_ = +5V ± 5%, V EE_ = -V CC_ 150 V CC_ = +V ± 5%, V EE_ = -V CC_ 150 t EN-CL V CC_ = +5V ± 5%, V EE_ = -V CC_ 10 V CC_ = +V ± 5%, V EE_ = -V CC_ 150 t DI-CL V CC_ = +5V ± 5%, V EE_ = -V CC_ 150 V PP_ = V, V NN_ = 0, V CC_ = +V ± 5%, V EE_ = -V CC_ 00 t EN_SH V PP_ = 5V, V NN_ = 0, V CC_ = +5V ± 5%, V EE_ = -V CC_ 00 V PP_ = V, V NN_ = 0, V CC_ = +V ± 5%, V EE_ = -V CC_ 50 t DI_SH V PP_ = 5V, V NN_ = 0, V CC_ = +5V ± 5%, V EE_ = -V CC_ 50 IN P _ to IN N _ Over l ap Tol er ance 3 ns Crosstalk V PP_ = V CC_ = +5V, V NN_ = V EE_ = -5V, f = 5MHz ns ns ns ns ns ns 9 db nd Harmonic Distortion HD V PP_ = V NN_ = 0V, f OUT = 5MHz, V CC_ = V -4 db RMS Output Jitter t J V CC_ = V 9 ps Note 3: Specifications are guaranteed for the stated global conditions, unless otherwise noted and are 0% production tested at T A = +5 C and T A = +70 C. Specifications at T A = 0 C are guaranteed by design. Note 4: 0% production tested at T A = +5 C. Specifications over temperature are guaranteed by design. 5

6 Typical Operating Characteristics ( = +3.3V, V CC _ = +V, V EE _ = -V, = -0V, V PP _ = +0V, V NN _ = -0V, f OUT = 5MHz, T A = +5 C, unless otherwise noted.) ICC (ma) ICC (ma) I CC vs. OUTPUT FREQUENCY 4 PULSES, PRF = khz FREQUENCY (MHz) I CC vs. TEMPERATURE CONTINUOUS SWITCHING, f OUT =.5MHz, V PP_ = V CC_ = +5V, V NN_ = V EE_ = -5V, = +3.3V, NO LOAD TEMPERATURE ( C) MAX4/11/ toc01 MAX4/11/ toc04 IPP (ma) ICC (ma) I CC vs. OUTPUT FREQUENCY CONTINUOUS SWITCHING, V PP_ = V CC_ = +5V, V NN_ = V EE_ = -5V, = +3.3V, NO LOAD FREQUENCY (MHz) I PP vs. OUTPUT FREQUENCY PULSES, PRF = khz FREQUENCY (MHz) MAX4/11/ toc0 MAX4/11/ toc05 ICC (μa) IPP (ma) I CC vs. TEMPERATURE PULSES AT MHz, PRF = khz TEMPERATURE ( C) I PP vs. OUTPUT FREQUENCY CONTINUOUS SWITCHING, V PP_ = V CC_ = +5V, V NN_ = V EE_ = -5V, = +3.3V, NO LOAD FREQUENCY (MHz) MAX4/11/ toc03 MAX4/11/ toc I PP vs. TEMPERATURE 4 PULSES AT MHz, PRF = khz MAX4/11/ toc I PP vs. TEMPERATURE CONTINUOUS SWITCHING, f OUT =.5MHz, V PP_ = V CC_ = +5V, V NN_ = V EE_ = -5V, = +3.3V, NO LOAD MAX4/11/ toc I NN vs. OUTPUT FREQUENCY 4 PULSES, PRF = khz MAX4/11/ toc09 IPP (ma) IPP (ma) 5 4 INN (ma) TEMPERATURE ( C) TEMPERATURE ( C) FREQUENCY (MHz)

7 Typical Operating Characteristics (continued) ( = +3.3V, V CC _ = +V, V EE _ = -V, = -0V, V PP _ = +0V, V NN _ = -0V, f OUT = 5MHz, T A = +5 C, unless otherwise noted.) INN (ma) trop (ns) I NN vs. OUTPUT FREQUENCY CONTINUOUS SWITCHING, V PP_ = V CC_ = +5V, V NN_ = V EE_ = -5V, = +3.3V, NO LOAD FREQUENCY (MHz) OUT RISE TIME ( TO V PP_ ) vs. V CC_ /V EE_ SUPPLY VOLTAGE R L = 0Ω, C L = 0pF / /-7.5 +/- +5/-5 +/- +./-. V CC_ /V EE_ SUPPLY VOLTAGE (V) MAX4/11/ toc MAX4/11/ toc13 INN (ma) tfon (ns) I NN vs. TEMPERATURE PULSES AT MHz, PRF = khz TEMPERATURE ( C) OUT FALL TIME ( TO V NN_ ) vs. V CC_ /V EE_ SUPPLY VOLTAGE R L = 0Ω, C L = 0pF / /-7.5 +/- +5/-5 +/- +./-. V CC_ /V EE_ SUPPLY VOLTAGE (V) MAX4/11/ toc11 MAX4/11/ toc14 INN (ma) tplh (ns) I NN vs. TEMPERATURE CONTINUOUS SWITCHING, f OUT =.5MHz, V PP_ = V CC_ = +5V, V NN_ = V EE_ = -5V, = +3.3V, NO LOAD TEMPERATURE ( C) INP-TO-OUT RISE PROPAGATION DELAY vs. V CC_ /V EE_ SUPPLY VOLTAGE R L = 0Ω, C L = 0pF +4.75/ /-7.5 +/- +5/-5 +/- +./-. V CC_ /V EE_ SUPPLY VOLTAGE (V) MAX4/11/ toc MAX4/11/ toc15 tplh (ns) INP-TO-OUT RISE PROPAGATION DELAY vs. TEMPERATURE R L = 0Ω, C L = 0pF TEMPERATURE ( C) MAX4/11/ toc1 tphl (ns) INP-TO-OUT FALL PROPAGATION DELAY vs. V CC_ /V EE_ SUPPLY VOLTAGE R L = 0Ω, C L = 0pF +4.75/ /-7.5 +/- +5/-5 +/- +./-. V CC_ /V EE_ SUPPLY VOLTAGE (V) MAX4/11/ toc17 tphl (ns) 4 INP-TO-OUT FALL PROPAGATION DELAY vs. TEMPERATURE 0 R L = 0Ω, C L = 0pF TEMPERATURE ( C) MAX4/11/ toc1 7

8 PIN NAME FUNCTION Pin Description Channel 1 -Side Gate Input. Connect a 1nF to nf capacitor between C 1 C DP1 and C GP1 as close as GP1 possible to the device. Channel 1 -Side Positive Supply Voltage Input. Bypass V PP1 to with a 0.1µF as close as, 3 V PP1 possible to the device. See the Power Supplies and Bypassing section. Depending on the output, additional bypassing may be required. 4,, 33, 39 No Connection. Not connected internally. 5 OP1 Channel 1 -Side Drain Output OCP1 Channel 1 -Side Clamp Output 7, 15,, 3, 44, 55 Ground OCN1 Channel 1 Low-Side Clamp Output 9 ON1 Channel 1 Low-Side Drain Output 11, V NN1 possible to the device. See the Power Supplies and Bypassing section. Depending on the output, Channel 1 -Side Negative Supply Voltage Input. Bypass V NN1 to with a 0.1µF as close as additional bypassing may be required. Channel 1 Low-Side Gate Input. Connect a 1nF to nf capacitor between C 13 C DN1 and C GN1 as close as GN1 possible to the device. Channel 1 Low-Side Driver Output. Connect a 1nF to nf capacitor between C 14 C DN1 and C GN1 as close DN1 as possible to the device. 1, 54 V CC1 the device. See the Power Supplies and Bypassing section. Depending on the output, additional Channel 1 Gate-Drive Supply Voltage Input. Bypass V CC1 to with a 0.1µF as close as possible to bypassing may be required. 17 INN1 Channel 1 Low-Side Logic Input (Table 1) 1 INC1 Channel 1 Clamp Logic Input. Clamps OCP1 and OCN1 are turned on when INC1 is high and when INP1 and INN1 are low (see Table 1). 19 INP1 Channel 1 -Side Logic Input (Table 1) 0 EN1 Channel 1 Enable Logic Input. Drive EN1 high to enable OP1 and ON1. Pull EN1 low to turn on the gatesource short circuit (see Table 1). 1 SHDN Shutdown Logic Input (Table 1) A Analog Ground. Must be connected to common. 3 EN Channel Enable Logic Input. Drive EN high to enable OP and ON. Pull EN low to turn on the gatesource short circuit. See Table 1. 4 INP Channel -Side Logic Input (Table 1) 5 INC Channel Clamp Logic Input. Clamps OCP and OCN are turned on when INC is high and when INP and INN are low. See Table 1. INN Channel Low-Side Logic Input (Table 1) 7, 45 V CC the device. See the Power Supplies and Bypassing section. Depending on the output, additional Channel Gate-Drive Supply Voltage Input. Bypass V CC to with a 0.1µF as close as possible to bypassing may be required. Channel Low-Side Driver Output. Connect a 1nF to nf capacitor between C 9 C DN and C GN as close DN as possible to the device. Channel Low-Side Gate Input. Connect a 1nF to nf capacitor between C 30 C DN and C GN as close as GN possible to the device.

9 PIN NAME FUNCTION Pin Description (continued) 31, 3 V NN possible to the device. See the Power Supplies and Bypassing section. Depending on the output, Channel -Side Negative Supply Voltage Input. Bypass V NN to with a 0.1µF as close as additional bypassing may be required. 34 ON Channel Low-Side Drain Output 35 OCN Channel Low-Side Clamp Output 37 OCP Channel -Side Clamp Output 3 OP Channel -Side Drain Output 40, 41 V PP device. See the Power Supplies and Bypassing section. Depending on the output, additional bypassing Channel -Side Supply Voltage Input. Bypass V PP to with a 0.1µF as close as possible to the may be required. Channel -Side Gate Input. Connect a 1nF to nf capacitor between C 4 C DP and C GP as close as GP possible to the device. Channel -Side Driver Output. Connect a 1nF to nf capacitor between C 43 C DP and C GP as close DP as possible to the device. Channel -Side Clamp Gate Input. Connect a 1nF to nf capacitor between C 4 C DC and C GC as GC close as possible to the device. Channel -Side Clamp Driver Output. Connect a 1nF to nf capacitor between C 47 C DC and C GC as DC close as possible to the device. 4 V EE V EE to with a 0.1µF as close as possible to the device. See the Power Supplies and Bypassing Channel Negative Supply Input. V EE V CC. Gate Drive Supply Voltage for the OCP clamp. Bypass section. Depending on the output, additional bypassing may be required. 49 Power Supplies and Bypassing section. Depending on the output, additional bypassing may be Logic Supply Voltage Input. Bypass to with a 0.1µF as close as possible to the device. See the required. 50 Substrate Voltage. Connect to a voltage equal to or more negative than the more negative of V NN1 or V NN. 51 V EE1 V EE1 to with a 0.1µF as close as possible to the device. See the Power Supplies and Bypassing Channel 1 Negative Supply Input. V EE1 V CC1. Gate Drive Supply Voltage for the OCP clamp. Bypass section. Depending on the output, additional bypassing may be required. Channel 1 -Side Clamp Driver Output. Connect a 1nF to nf capacitor between C 5 C DC1 and C GC1 as DC1 close as possible to the device. Channel 1 -Side Clamp Gate Input. Connect a 1nF to nf capacitor between C 53 C DC1 and C GC1 as GC1 close as possible to the device. Channel 1 -Side Driver Output. Connect a 1nF to nf capacitor between C 5 C DP1 and C GP1 as close DP1 as possible to the device. EP Exposed Pad. EP must be connected to. Do not use EP as the only connection for the device. Detailed Description The are dual high-voltage, high-speed pulsers that can be independently configured for either unipolar or bipolar pulse outputs. These devices have independent logic inputs for full pulse control and independent active clamps. The clamp input, INC_, can be set high to activate the clamp automatically when the device is not pulsing to the positive or negative high-voltage supplies. Logic Inputs (INP_, INN_, INC_, EN_, SHDN) The have a total of nine logic input signals. SHDN controls power-up and powerdown of the device. There are two sets of INP_, INN_, INC_, and EN_ signals: one for each channel. INP 9

10 Table 1. Truth Table X = Don t care. 0 = Logic-low. 1 = Logic-high. INPUTS OUTPUTS SDHN EN_ INP_ INN_ INC_ OP_ ON_ 0 X X X 0 0 X X X X X X X X V NN_ X V PP_ OCP_, OCN_ X V PP_ V NN_ STATE Powered down, INP_/INN_ disabled, gate-source short disabled Powered down, INP_/INN_ disabled, gate-source short disabled Powered up, INP_/INN_ disabled, gate-source short enabled Powered up, INP_/INN_ disabled, gate-source short enabled Powered up, all inputs enabled, gate-source short disabled Powered up, all inputs enabled, gate-source short disabled Powered up, all inputs enabled, gate-source short disabled Powered up, all inputs enabled, gate-source short disabled Not allowed (3ns maximum overlap) controls the on and off states of the high side FET, INN_ controls the on and off states of the low side FET, INC_ controls the active clamp and EN_ controls the gate to source short. These signals give complete control of the output stage of each driver (see Table 1 for all logic combinations). The logic inputs are CMOS logic compatible and the logic level are referenced to for maximum flexibility. The low 5pF (typ) input capacitance of the logic inputs reduces loading and increases switching speed. -Voltage Output Protection (MAX411 Only) The high-voltage outputs of the MAX411 feature an integrated overvoltage protection circuit that allows the user to implement multilevel pulsing by connecting the outputs of multiple pulser channels in parallel. Internal diodes in series with the ON_ and OP_ outputs prevent the body diode of the high-side and low-side FETs from switching on when a voltage greater than V NN_ or V PP_ is present on the output. See Figure. Active Clamps The feature an active clamp circuit to improve pulse quality and reduce nd harmonic output. The clamp circuit consists of an N- channel (DC-coupled) and a P-channel (AC and DC delay coupled) high-voltage FETs that are switched on or off by the logic clamp input (INC_). The MAX4/ MAX411 feature protected clamp devices, allowing the clamp circuit to be used in bipolar pulsing circuits (see Figures 1 and ). A diode in series with the OCN_ output prevents the body diode of the low-side FET from turning on when a voltage lower than is present. Another diode in series with the OCP_ output prevents the body diode of the high-side FET from turning on when a voltage higher than ground is present. The MAX4 does not have diode protection on the clamp outputs. Thus, the device is suitable for use in circuits where only unipolar pulsing is required. The user can connect the active clamp input (INC_) to a logic-high voltage and drive only the INP_ and INN_ inputs to minimize the number of signals used to drive the

11 device. In this case, whenever both the INP_ and INN_ inputs are low and the INC_ input is high, the active clamp circuit pulls the output to through the OCP_ and OCN_ outputs (see Table 1 for more information). Power-Supply Ramping and Gate-Source Short Circuit The include a gatesource short circuit that is controlled by the enable input (EN_). When SHDN is high and EN is low, a 0Ω switch shorts together the gate and source of the high-side output FET. At the same time, a similar switch shorts the gate and source of the low-side output FET (Table 1). The gate-source short circuit prevents accidental turnon of the output FETs due to the ramping voltage on V PP_ and V NN_, and allows for faster ramping rates and smaller delay times between pulsing modes. Shutdown Mode SHDN is common to both channel 1 and channel and powers up or down the device. Drive SHDN low to power down all internal circuits (except the clamp circuits). When SHDN is low, the device is in the lowest power state (1µA) and the gate-source short circuit is disabled. The device takes 1µs (typ) to become active when SHDN is disabled. Thermal Protection A thermal shutdown circuit with a typical threshold of +150 C prevents damage due to excessive power dissipation. When the junction temperature exceeds T J = +150 C, all outputs are disabled. Normal operation typically resumes after the IC s junction temperature drops below +130 C. Applications Information AC-Coupling Capacitor Selection The value of all AC-coupling capacitors (between C DP_ and C GP, and between C DN_ and C GN_ ) should be between 1nF to nf. The voltage rating of the capacitor should be at least as high as V PP_. The capacitors should be placed as close as possible to the device. Because INP_ and part of INC_ are AC-coupled to the output devices, they cannot be driven high indefinitely when the device is active. Power Dissipation The power dissipation of the MAX4/MAX411/ MAX4 consists of three major components caused by the current consumption from V CC_,V PP_, and V NN_. The sum of these components (P VCC_, P VPP_ and P VNN_ ) must be kept below the maximum power-dissipation limit. See the Typical Operating Characteristics section for more information on typical supply currents versus switching frequencies. The device consumes most of the supply current from V CC_ supply to charge and discharge internal nodes such as the gate capacitance of the high-side FET (C P ) and the low-side FET (C N ). Neglecting the small quiescent supply current and a small amount of current used to charge and discharge the capacitances at the internal gate clamp FETs, the power consumption can be estimated as follows: ( ) + ( ) P VCC = C V f C V N CC_ IN P CC_ f IN BR F BTD fin = finn + finp ( ) Where f INN and f INP are the switching frequency of the inputs INN, INP respectively, and where BRF is the burst repitition frequency and BTD is the burst time duration. The typical value of the gate capacitances of the power FET are C N = 0.nF, C P = 0.4nF. For an output load that has a resistance of R L and capacitance of C L, the power dissipation can be estimated as follows (assume square wave output and neglect the resistance of the switches): P VPP = ( + ) ( ) C C f V V + V PP _ 1 O L IN PP_ NN_ RL ( ) BRF BTD where C O is the output capacitance of the device. Power Supplies and Bypassing The operate from independent supply voltage sets (only and are common to both channels). The logic input circuit operates from a +.7V to +V single supply ( ). The level-shift driver dual supplies, V CC_ /V EE_ operate from ±4.75V to ±.V. The V PP_ /V NN_ high-side and low-side supplies are driven from a single positive supply up to +0V, from a single negative supply up to -00V, or from ±1V dual supplies. Either V PP_ or V NN_ can be set at 0. Bypass each supply input to ground with a 0.1µF capacitor as close as possible to the device. Depending on the load of the input, additional bypassing may be needed to keep the output of V NN_ and V PP_ stable during output transitions. For example, with 11

12 INP_ INC_ SHDN EN_ V CC_ C DP_ C GP_ SHORT CIRCUIT V CC_ C DP_ V EE_ C DC_ C GC_ V CC_ OCN_ C GP_ MAX4 V PP_ OP OCP_ ON_ V CC_ INN_ C DN_ C GN_ V NN_ V EE_ CDC_ C GC_ C DN_ C GN_ Figure 1. MAX4 Simplified Functional Diagram for One Channel C OUT = 0pF and R OUT = 0Ω load, additional µf (typ) capacitor is recommended. is the substrate voltage and must be connected to a voltage equal to or more negative than the more negative voltage of V NN1 or V NN. Exposed Pad and Layout Concerns The provide an exposed pad (EP) underneath the TQFN package for improved thermal performance. EP is internally connected to. Connect EP to externally and do not run traces under the package to avoid possible short circuits. To aid heat dissipation, connect EP to a similarly sized pad on the component side of the PCB. This pad should be connected through to the solder-side copper by several plated holes to a large heat spreading copper area to conduct heat away from the device. The high-speed pulsers require low-inductance bypass capacitors to their supply inputs. -speed PCB trace design practices are recommended. Pay particular attention to minimize

13 INP_ INC_ SHDN EN_ V CC_ C DP_ C GP_ SHORT CIRCUIT V CC_ C DP_ V EE_ C DC_ C GC_ V CC_ OCN_ C GP_ MAX411 V PP_ OP OCP_ ON_ V CC_ INN_ C DN_ C GN_ V NN_ V EE_ CDC_ C GC_ C DN_ C GN_ Figure. MAX411 Simplified Functional Diagram for One Channel trace lengths and use sufficient trace width to reduce inductance. Use of surface-mount components is recommended. Supply Sequencing must be lower than or equal to the more negative voltage of V NN1 or V NN at all times. No other powersupply sequencing is required for the MAX4/ MAX411/MAX4. Typical Application Circuits Figures, 9, and show typical applications for the. Figure shows the MAX4 used in a bipolar pulsing connection. Figure 9 shows the MAX411 in a five-level pulsing application, and Figure shows the MAX4 used in a unipolar application. 13

14 INP_ INC_ SHDN EN_ V CC_ C DP_ C GP_ SHORT CIRCUIT V CC_ C DP_ V EE_ C DC_ C GC_ V CC_ OCN_ C GP_ MAX4 V PP_ OP OCP_ ON_ V CC_ INN_ C DN_ C GN_ V NN_ V EE_ CDC_ C GC_ C DN_ C GN_ Figure 3. MAX4 Simplified Functional Diagram for One Channel 14

15 OUT_ INP_ INN_ INC_ = HIGH t POH t ROP 50% % 90% % 90% % 50% t PHO t POL 90% % Figure 4. Detailed Timing (R L = 0Ω, C L = 0pF) t FPO t PLH t RNP 50% t FON 50% 50% 50% % 90% % 50% t PHL t FPN 50% t PLO 90% t RNO V PP_ V NN_ OUT_ (INP_ = HIGH) % % OUT_ (INN_ = HIGH) t DI t EN EN 50% 50% INC_ = HIGH Figure 5. Enable Timing (R L = 0Ω, C L = 0pF) 15

16 OUT_ (V PP_ ) OUT_ (V NN_ ) t EN-CL INC_ Figure. Active Clamp Timing % 1kΩ PULLUP RESISTOR TO V PP_ % % 1kΩ PULLDOWN RESISTOR TO V NN_ t DI-CL +V 90% CGN_ % % CGP_ t DI-SH -V % t EN-SH EN 50% 1kΩ PULLUP RESISTOR BETWEEN CGN_ AND +V. 1kΩ PULLDOWN RESISTOR BETWEEN CGP_ AND -V. Figure 7. Short-Circuit Timing 1

17 OUT1 +0V -0V C GP1 V PP1 V PP1 OP1 OCP1 OCN1 MAX4 ON1 V NN1 V NN1 C GN1 C DN1-0V -V +3V -V +V +V CDP1 VCC1 CGC1 CDC1 VEE1 VSS VDD VEE CDC CGC VCC CDP VCC1 INN1 INC1 INP1 EN1 SHDN A EN INP INC INN VCC C GP V PP V PP OP OCP OCN ON V NN V NN C GN C DN V -0V OUT +V +V Figure. MAX4: Dual Bipolar Pulsing, ±0V, 17

18 OUT1 +0V -0V C GP1 V PP1 V PP1 OP1 OCP1 OCN1 MAX411 ON1 V NN1 V NN1 C GN1 C DN1-0V -V +3V -V +V +V CDP1 VCC1 CGC1 CDC1 VEE1 VSS VDD VEE CDC CGC VCC CDP VCC1 INN1 INC1 INP1 EN1 SHDN A EN INP INC INN VCC C GP V PP V PP OP OCP OCN ON V NN V NN C GN C DN V -0V OUT V +V Figure 9. MAX411: Five-Level Pulsing, ±0V, ±50V, 1

19 C AC C AC C GP1 C GP 4 CDP1 +3V +V +V VCC1 CGC1 CDC1 VEE1 VSS V PP1 V PP 41 +0V +0V C 3 V PP1 V PP 40 PP C PP OP1 OP 3 OUT1 OCP1 OCP OUT OCN1 MAX4 OCN 35 9 ON1 ON V NN1 V NN 3 13 V NN1 C GN1 V NN C GN C DN1 C DN 9 VCC1 INN1 INC1 INP1 EN1 SHDN A EN INP INC INN VCC VDD VEE CDC CGC VCC CDP +V +V Figure. MAX4: Dual Unipolar Pulsing, +0V, 19

20 Package Information For the latest package outline information and land patterns, go to PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 5 TQFN T Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 0 Maxim Integrated Products, 0 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.