Error Analysis of a Synchronizer Analysis Algorithm

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1 Error Analysis of a Synchronizer Analysis Algorithm Mark Greenstreet 1 Chen Greif 1 Suwen Yang 2 1 University of British Columbia 2 Oracle Frontiers of Analog Circuits

2 Outline Metastability: synchronizers and other circuits. Analysis: challenges and solutions to simulating saddles.

3 Basins of Attraction Vector flow

4 Basins of Attraction Basins of attraction

5 Basins of Attraction The separator. A set of lower dimension than the full state space. Trajectories that start on the separator stay on it forever. Trajectories that start close to the separator may take a long time to settle in their basin.

6 A Synchronizer d D Q d Data goes high well before the clock edge.

7 A Synchronizer d D Q d Data goes high well after the clock edge.

8 A Synchronizer d D Q d Data goes high close to the clock edge...

9 A Synchronizer d D Q d... or a late transition

10 A Synchronizer d D Q d... or a slow transition

11 A Synchronizer d D Q d... or a glitch

12 A Synchronizer d D Q d... or oscillation, or... There is no perfect synchronizer. The failure probability can be made arbitrarily small if the settling time is long enough.

13 More Metastability Analog-to-digital converters Comparator output not guaranteed to settle in bounded time. Recent design review: high clock rate, successive approximation, ADC designer had neglected metastability. Oscillator start-up An oscillator implements the dynamics of a periodic attractor. Every periodic attractor has an associated euilibrium point. This euilibrium point should be unstable. The best we can hope to verify is that the an oscillator starts from almost all initial conditions. PLL mode change Will the VCO move forward or backward in phase to converge to the reference?

14 Simulating Metastable Behaviors Used To Be Hard Forward simulation numerically unstable due to divergence in a few directions (eigenvectors) near the unstable euilibrium. Backward simulation unstable because the forward version is stable for the other eigenvectors. Example: Using bisection, HSPICE can locate critical timing window for a synchronizer to within a few femtoseconds. That establishes an MTBF of a few milliseconds. DON T USE HSPICE TO VALIDATE YOUR SYNCHRONIZERS!

15 How to Simulate Metastable Behaviors Bisection With Restarts (BWR): t t d The designer chooses initial settle-high and settle-low conditions. The rest is automatic.

16 How to Simulate Metastable Behaviors Bisection With Restarts (BWR): t t d Next, BWR tries the midpoint for t d.

17 How to Simulate Metastable Behaviors Bisection With Restarts (BWR): t t d Further bisection, narrows the time window further.

18 How to Simulate Metastable Behaviors Bisection With Restarts (BWR): V 1,H t t d V 1,L Bisect until the window for t d is very small. Use numerical integration to find new initial conditions. The settle-high and settle-low trajectories are very close to each other. Thus, intermediate trajectories can infered by linear interpolation.

19 How to Simulate Metastable Behaviors Bisection With Restarts (BWR): V 1,H V 2,H t t d V 2,L Subseuent rounds of bisecting voltage-vector intervals allows metastable behavior to be explored as deeply as we want. We ve analysed synchronizers with four or more flip flops, and shown failure probabilities down to less than

20 Can We Rely On BWR? In use at Oracle (né SUN) for four years. Has motivated design changes. Design changes can be very expensive. An unreliable synchronizer would be extremely expensive. Do we believe BWR enough to rely on its results? Validating BWR Compare with HSPICE Compare with small-signal analysis. Test chip? Error analysis of the algorithm

21 Error Analysis Key idea BWR computes a small-signal response matrix. Compute SVD of that matrix, and do standard forward-backward error analysis. But it doesn t uite work that way For the example here, the largest singular value is > Matlab gives a value for the second largest singular value. This is zero to within round-off error! We strongly believe that it is < 1 as reuired. But belief isn t a proof. The main issue is floating nodes.

22 Singular Value Circuit Analysis clk sv(1) = 8.39 sv(2) = 1.02 sv(3) = 0.96 Note: clk is low at this analysis step. All other singular values < 0.2. x More observations: The metastable synchronizer is a time-varying, linear system. When the clock is constant, the sensitivity matrices are very similar to each other. Interval matrix methods may be applicable. We can probably identify floating nodes by their singular vectors and remove them by suitable over-approximations.

23 Summary Metastability is unavoidable in any system with multiple modes. Traditionally associated with synchronizers and arbiters. Metastability can occur in any circuit that must make a hard decision based on a soft input. A lurking issue in small a analog? Numerical methods have a role to play in new circuit analysis techniues: Dynamical systems Linear algebra Error analysis

Computing Synchronizer Failure Probabilities

Submitted to DATE 07. Please do not distribute Computing Synchronizer Failure Probabilities Suwen Yang Mark Greenstreet Department of Computer Science, University of British Columbia Abstract System-on-Chip