AON6266E 60V N-Channel AlphaSGT TM
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1 6V NChannel AlphaSGT TM General Description Trench Power AlphaSGT TM technology Low R DS(ON) Logic Level Gate Drive ESD Protected Excellent Gate Charge x R DS(ON) Product (FOM) RoHS and HalogenFree Compliant Applications High Frequency Switching and Synchronous Rectification Product Summary V DS I D (at V GS =V) R DS(ON) (at V GS =V) R DS(ON) (at V GS =4.V) 6V 4A < 3.mΩ < 7.7mΩ Typical ESD protection HBM Class % UIS Tested % Rg Tested Top View DFNx6 Bottom View Top View D G PIN PIN 4 S Orderable Part Number Package Type Form Minimum Order Quantity DFN x6 Tape & Reel 3 Absolute Maximum Ratings T A = C unless otherwise noted Parameter DrainSource Voltage GateSource Voltage Avalanche energy V DS Spike I T A = C T A =7 C L=.3mH C Symbol Continuous Drain T C = C 4 I D Current G T C = C Pulsed Drain Current C 9 Continuous Drain Current Avalanche Current C Power Dissipation A µs T C = C V DS V GS I DM 4. I DSM. I AS E AS V SPIKE T A = C. P DSM Maximum 6 Power Dissipation B T C = C. T A =7 C 3. Junction and Storage Temperature Range T J, T STG to P D ± Units V V A A A mj V W W C Thermal Characteristics Parameter Symbol Typ Maximum JunctiontoAmbient A t s R θja Maximum JunctiontoAmbient A D SteadyState 4 Maximum JunctiontoCase SteadyState 4. R θjc Max 4.8 Units C/W C/W C/W Rev..: February 7 Page of 6
2 Electrical Characteristics (T J = C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units STATIC PARAMETERS BV DSS DrainSource Breakdown Voltage I D =µa, V GS =V 6 V I DSS Zero Gate Voltage Drain Current V DS =6V, V GS =V T J = C µa I GSS GateBody leakage current V DS =V, V GS =±V ± µa V GS(th) Gate Threshold Voltage V DS =V GS, I D =µa..7. V R DS(ON) V GS =V, I D =A.7 3. mω Static DrainSource OnResistance T J = C V GS =4.V, I D =8A mω g FS Forward Transconductance V DS =V, I D =A 4 S V SD Diode Forward Voltage I S =A, V GS =V.7 V I S Maximum BodyDiode Continuous Current G 4 A DYNAMIC PARAMETERS C iss Input Capacitance 7 pf C oss Output Capacitance V GS =V, V DS =3V, f=mhz pf C rss Reverse Transfer Capacitance pf R g Gate resistance f=mhz.6.3. Ω SWITCHING PARAMETERS Q g (V) Total Gate Charge 3. nc Q g (4.V) Total Gate Charge 6. nc V GS =V, V DS =3V, I D =A Q gs Gate Source Charge. nc Q gd Gate Drain Charge 3. nc Q oss Output Charge V GS =V, V DS =3V nc t D(on) TurnOn DelayTime ns t r TurnOn Rise Time V GS =V, V DS =3V, R L =.Ω, 3 ns t D(off) TurnOff DelayTime R GEN =3Ω 9 ns t f TurnOff Fall Time 3 ns t rr Body Diode Reverse Recovery Time I F =A, di/dt=a/µs 7 ns Q rr Body Diode Reverse Recovery Charge I F =A, di/dt=a/µs 4 nc A. The value of R θja is measured with the device mounted on in FR4 board with oz. Copper, in a still air environment with T A = C. The Power dissipation P DSM is based on R θja t s and the maximum allowed junction temperature of C. The value in any given application depends on the user's specific board design. B. The power dissipation P D is based on T J(MAX) = C, using junctiontocase thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. C. Single pulse width limited by junction temperature T J(MAX) = C. D. The R θja is the sum of the thermal impedance from junction to case R θjc and case to ambient. E. The static characteristics in Figures to 6 are obtained using <3µs pulses, duty cycle.% max. F. These curves are based on the junctiontocase thermal impedance which is measured with the device mounted to a large heatsink, assuming a maximum junction temperature of T J(MAX) = C. The SOA curve provides a single pulse rating. G. The maximum current rating is package limited. H. These tests are performed with the device mounted on in FR4 board with oz. Copper, in a still air environment with T A = C. I. The spike duty cycle % max, limited by junction temperature T J(MAX) = C. APPLICATIONS OR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,FUNCTIONS AND RELIABILITY WITHOUT NOTICE. Rev..: February 7 Page of 6
3 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 8 6 V 6V V 4.V 4V 8 6 V DS =V I D (A) 4 3.V I D (A) 4 3V C C 3 4 V GS =.V Figure : OnRegion Characteristics (Note E) V GS (Volts) Figure : Transfer Characteristics (Note E) R DS(ON) (mω) V GS =4.V V GS =V Normalized OnResistance V GS =V I D =A V GS =4.V I D =8A 4 3 I D (A) Figure 3: OnResistance vs. Drain Current and Gate Voltage (Note E) Temperature ( C) Figure 4: OnResistance vs. Junction Temperature (Note E) 4 I D =A.E R DS(ON) (mω) 3 C C V GS (Volts) Figure : OnResistance vs. GateSource Voltage (Note E) I S (A).E.E.E.E3.E4 C C.E V SD (Volts) Figure 6: BodyDiode Characteristics (Note E) Rev..: February 7 Page 3 of 6
4 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 8 V DS =3V I D =A 8 C iss V GS (Volts) 6 4 Capacitance (pf) 6 4 C oss C rss Q g (nc) Figure 7: GateCharge Characteristics Figure 8: Capacitance Characteristics I D (Amps)..... R DS(ON) limited T J(Max) = C T C = C µs DC µs µs ms ms Power (W) 4 3 T J(Max) = C T C = C... V GS > or equal to 4.V Figure 9: Maximum Forward Biased Safe Operating Area (Note F).... Figure : Single Pulse Power Rating Junctionto Case (Note F) Z θjc Normalized Transient Thermal Resistance. D=T on /T T J,PK =T C P DM.Z θjc.r θjc R θjc =4.8 C/W Single Pulse In descending order D=.,.3,.,.,.,., single pulse P DM T on T. E.... Figure : Normalized Maximum Transient Thermal Impedance (Note F) Rev..: February 7 Page 4 of 6
5 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 3 3 Power Dissipation (W) Current rating I D (A) 7 T CASE ( C) Figure : Power Derating (Note F) 7 T CASE ( C) Figure 3: Current Derating (Note F).8.6 T A = C Eoss(uJ).4. Power (W) E.. Figure 4: Coss stored Energy Figure : Single Pulse Power Rating JunctiontoAmbient (Note H) Z θja Normalized Transient Thermal Resistance.. D=T on /T T J,PK =T A P DM.Z θja.r θja R θja = C/W Single Pulse In descending order D=.,.3,.,.,.,., single pulse P DM T on T..... Figure 6: Normalized Maximum Transient Thermal Impedance (Note H) Rev..: February 7 Page of 6
6 Figure Gate A: Charge Gate Charge Test Circuit Test Circuit & Waveform & Waveforms Qg V Qgs Qgd Ig Figure B: Resistive Resistive Switching Switching Test Test Circuit Circuit & Waveforms Waveforms RL Charge Rg 9% % td(on) t r t d(off) t f t on t off Figure C: Unclamped Inductive Switching (UIS) Test Circuit & Waveforms L E = / LI AR AR BV DSS Rg Id Id I AR Figure Diode D: Recovery Diode Recovery Test Circuit Test Circuit & Waveforms & Waveforms Q = Idt rr Ig Isd L Isd I F di/dt I RM t rr Rev..: February 7 Page 6 of 6
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OptiMOS Small-Signal-Transistor Features N-channel Enhancement mode Logic level (4.5V rated) Avalanche rated Product Summary V DS 3 V R DS(on),max V GS =1 V 16 mω V GS =4.5 V 8 I D 1.4 A Qualified according
More informationMaximum Ratings, at T j = 25 C, unless otherwise specified Parameter Symbol Value Unit Continuous drain current. I D puls E AS. dv/dt 6 kv/µs.
IPD6N3LZ OptiMOS PowerTransistor Feature Ideal for highfrequency dc/dc converters nchannel Logic Level Excellent Gate Charge x R DS(on) product (FOM) Low OnResistance R DS(on) Superior thermal resistance
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l Advanced Process Technology l Ultra Low OnResistance l Dual N and P Channel Mosfet l Surface Mount l Available in Tape & Reel l Dynamic dv/dt Rating l Fast Switching Description Fifth Generation HEXFETs
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OptiMOS P Small-Signal-Transistor Features P-channel Enhancement mode Super Logic Level (.5V rated) Avalanche rated Qualified according to AEC Q % lead-free; RoHS compliant Product Summary V DS - V R DS(on),max
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Silicon Carbide Power MOSFET N-CHANNEL ENHANCEMENT MODE TO-247-3L Inner Circuit Product Summary V DS I D(@25 C) R DS(on) 1200V 20A 120mΩ Features u Low On-Resistance u Low Capacitance u Avalanche Ruggedness
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PHDE GENERAL DESCRIPTION QUICK REFERENCE DATA Nchannel enhancement mode SYMBOL PARAMETER MAX. UNIT fieldeffect power transistor in a plastic envelope suitable for surface V DS Drainsource voltage 6 V mounting
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OptiMOS 3 Power-Transistor Features N-channel, normal level Excellent gate charge x R DS(on) product (FOM) Product Summary V DS 1 V R DS(on),max 7.2 mω I D 8 A Very low on-resistance R DS(on) 175 C operating
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IPB12CN1N G OptiMOS 2 Power-Transistor Features N-channel, normal level Excellent gate charge x R DS(on) product (FOM) Very low on-resistance R DS(on) Product Summary V DS 1 V R DS(on),max (TO252) 12.4
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SIPMOS SmallSignalTransistor Features PChannel Enhancement mode valanche rated Logic Level dv/dt rated Product Summary Drain source voltage V DS 6 V Drainsource onstate resistance R DS(on) 8 W Continuous
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SIPMOS SmallSignalTransistor Feature NChannel Enhancement mode Logic Level dv/dt rated Pbfree lead plating; RoHS compliant Qualified according to EC Q Product Summary V DS V R DS(on) 6 Ω I D.37 PGSOT3
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IPB2N25N3 G OptiMOS TM 3 Power-Transistor Features N-channel, normal level Excellent gate charge x R DS(on) product (FOM) Very low on-resistance R DS(on) Product Summary V DS 25 V R DS(on),max 2 mw I D
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OptiMOS Small-Signal-Transistor Features Dual N-channel Enhancement mode Ultra Logic level (1.8V rated) Avalanche rated Qualified according to AEC Q11 1% lead-free; RoHS compliant Product Summary V DS
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SPP18P6P G SIPMOS Power-Transistor Features P-Channel Enhancement mode Avalanche rated dv /dt rated 175 C operating temperature Product Summary V DS -6 V R DS(on),max.13 Ω I D -18.6 A PG-TO22-3 Type Package
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IPI3N3LA, IPP3N3LA OptiMOS 2 Power-Transistor Features Ideal for high-frequency dc/dc converters Qualified according to JEDEC ) for target applications N-channel - Logic level Product Summary V DS 25 V
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SUM5N3-3LC N-Channel 3-V (D-S) MOSFET With Sense Terminal PRODUCT SUMMARY V (BR)DSS (V) r DS(on) ( ) (A).3 @ V S = V 5 a 3.7 @ V S =.5 V a FEATURES TrenchFET Power MOSFET Plus Current Sensing Diode New
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BSC32N3S G OptiMOS 2 Power-Transistor Features Fast switching MOSFET for SMPS Optimized technology for notebook DC/DC converters Qualified according to JEDEC 1 for target applications Product Summary V
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OptiMOS 2 Power-Transistor Features Ideal for high-frequency dc/dc converters Qualified according to JEDEC 1) for target application N-channel, logic level Product Summary V DS 25 V R DS(on),max (SMD version)
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