Bipolar Transistors. Bipolar Transistors Application Note. Description

Transcription

1 Bipolar Transistors Description This document describes the electrical characteristics o bipolar transistors

2 Table o Contents Description... Table o Contents.... Transistor characteristics Device parameters Circuit parameters Low-requency, low-noise ampliiers Switching characteristics... 5 RESTRICTIONS ON PRODUCT USE... 8 / 8

3 List o Figures Bipolar Transistors Figure. Early's T-type equivalent circuit... 5 Figure. Frequency locus o α... 8 Figure.3 π-type equivalent circuit... 9 Figure.4 Circuit network using the h matrix... Figure.5 Circuit network using the y matrix... Figure.6 Circuit network using the S matrix... Figure.7 Frequency locus o h parameters... 7 Figure.8 Frequency locus o y parameters... 7 Figure.9 Relationship between NF and requency... 9 Figure.0 Noise source o transistor... 0 Figure. Total noise voltage Signal source resistance... 0 Figure. NF R g, I C ()... Figure.3 NF R g, I C ()... Figure.4 Noise igure o a multi-stage ampliier... Figure.5 Equivalent noise resistance o a multi-stage ampliier... 3 Figure.6 Switching time test circuit... 5 Figure.7 Switching waveorms and the deinitions o switching times... 5 Figure.8 I C vs. h FE... 5 List o Tables Table. List o transistoquivalent circuits... 4 Table. Relationships between the parameters o the T-type and the π-type equivalent circuits... 0 Table.3 Interrelation o parameters... 3 Table.4 Conversion ormulas or h parameters... 4 Table.5 Conversion ormulas or y parameters... 5 Table.6 h parameters converted using T-type equivalent circuit... 6 Table.7 y parameters converted using T-type equivalent circuit... 6 Table.8 Types o noise / 8

4 . Transistor characteristics Equivalent parameters o a transistor include the device parameters closely related to its internal operation and the circuit parameters that are represented as a matrix by treating the transistor as a our-terminal network. Equivalent circuits are also divided into small-signal and large-signal equivalent circuits, depending on the amplitude o signals to be handled. Since there are numerous equivalent circuits, circuit designers should careully consider the scopes and limitations o their applications. Table. categorizes equivalent circuits. Chapter ocuses on commonly used small-signal equivalent circuits. Table. List o transistoquivalent circuits Transistor equivalent circuits Small-signal equivalent circuits (General linear circuits such as ampliiers, oscillators, modulators, and demodulators) Device parameters Circuit parameters Early's T-type equivalent circuit (Common-base circuit) Giacoletto s π-type equivalent circuit (Common-collector and common-emitter circuits) Matrices showing the relationship between the input and output by voltage and current a-b matrixes g-h matrices (low requency) y-z matrices (high requency) Matrices showing the relationship between the input and output by power s matrices (ultra-high requency) (transmittance coeicient and relection coeicient indications) Large-signal equivalent circuits - device parameters (Nonlinear circuits such as pulse, digital, and switching circuits) Ebers-Moll current control model Beauoy-Sparkes charge control model Linvil density control model Other nonlinear models 4 / 8

5 .. Device parameters Bipolar Transistors () Early's T-type equivalent circuit Figure. shows Early s T-type equivalent circuit. e + - b - α i e + c μ V cb r c C e r bb C c b Figure. Early's T-type equivalent circuit (a) : Emitter resistance is the orward-bias resistance across the base-emitter junction, which is calculated as: = k T q I E ( Ω ) ( ) k : Boltzmann constant ( J/K) T : Absolute temperature (K) q : Elementary charge ( C) I E : Emitter current (A) At room temperature (300 K), Equation - is restated as ollows when the emitter current is given in ma: 6 I E ( ma ) ( Ω ) (3 ) 5 / 8

6 (b) C e : Emitter capacitance (C Te +C De ) The emitter capacitance is the sum o the depletion capacitance C Te and the diusion capacitance C De in the base-emitter junction. The depletion layer capacitance in the baseemitter junction can be ignored since it is ar smaller than the diusion capacitance. The depletion layer capacitance C Te and the diusion capacitance C De can be calculated using Equation -3 and Equation -4 respectively: 3 C Te = A e ε q n N ϕ 0 - V b'e ( F ) ( 3) A e : Emitter junction area (m ) ε : Dielectric constant n N : Majority carrier density (m -3 ) on the side with higher speciic resistance (NPN in this case) Φ 0 : Contact potential dierence (potential barrier in thermodynamic equilibrium) (V) V b'e : Voltage applied across the base-emitter junction (V) C De = q I E W k T D ( F ) ( 4) W : Base width (m) D : Diusion coeicient o minority carriers in the base layer (m / s) (c) µ : Voltage eedback ratio (Early constant) This constant due to the Early eect is a base-width modulation parameter. μ = k T d C 3 q W ( ϕ 0 - V b'e ) ( F ) ( 5) d C : Width o the collector depletion layer (m) (d) r c : Collector resistance This is a base-width modulation parameter, which is represented as: r C = α I E ( ) V b'c ( Ω ) ( 6) r c is typically to MΩ. 6 / 8

7 (e) Cc : Collector capacitance As is the case with the emitter capacitance, the collector capacitance is the sum o the depletion layer capacitance C TC and the diusion capacitance C DC in the collector-base junction. The diusion capacitance in the collector-base junction can be ignored since it is ar smaller than the depletion layer capacitance. The depletion layer capacitance can be calculated as: 3 C TC = A C ε q a ϕ 0 - V b'c ( F ) ( 7) A C : Collector junction area (m 3 ) a : Dopant concentration gradient (m -4 ) V b c : Voltage applied across the base-collector junction (V) C TC is typically to 0 pf. () α : DC current gain This is the only parameter o Early's T-type equivalent circuit that exhibits requency dependence and can be calculated as: α = α 0 + j ω C e r c = π C e Hence: α = α 0 + j ( 8) α 0 : Value o α at low requency : α cut-o requency (requency at which α drops by 3 db) 7 / 8

8 Figure. shows the requency locus o α. The measurement o α reveals that the dierence between theoretical and measured values increases as the requency approaches. This is because Early's T-type equivalent circuit is based on primary approximation o physical phenomena. T o correct this error, Thomas-Moll included the excess phase parameter m in the equation: α = α 0 + j e - j m ( 9) This equation matches well with measured values at requencies lower than. R e α.0 π 4 α= α0 m + j - j0.5 I m α α = α 0 + j e - j m Figure. Frequency locus o α (g) r bb : Base spreading resistance This is the resistance rom the center o the base layer to the external base terminal that contributes to the operation o a transistor and is determined by the shape and dimensions o the transistor and the speciic resistance o the base layer. The comb-shaped base spreading resistance can be calculated as ollows. Z n p + n + Base Emitter W L r bb' ρ B W L Z (Ω) ( 0) ρ B Speciic resistance o the base layer (Ω m) 8 / 8

9 In a common-emitter coniguration, the DC current gain (β) o a transistor is represented as ollows using π-type equivalent circuit: β = α 0 - α 0 ( + j ω C b'e r b'e ) = β 0 + j ω C b'e r b'e As is the case with α, let s deine the β cut-o requency β as the requency at which the absolute value o β equals β 0 /. Then, β is calculated as: β = π C b'e r b'e β = + j β ( ) () π-type equivalent circuit Figure.3 shows the π-type equivalent circuit, which is essentially the same as the T- type equivalent circuit described above. The π-type equivalent circuit diers rom the T- type equivalent circuit only in that, in principle, the parameters o the ormer have no requency response. Since the physical meaning o each parameter is easy to understand, the π-type equivalent circuit is widely used. To use it or circuit calculation, it is convenient to simpliy the basic coniguration shown in Figure.3, considering the requency range. Table. shows the relationships o the parameters o the T-type and the π-type equivalent circuits. r b c b r bb b c C b c - r b e C b e r ce gmv b e + e e Figure.3 π-type equivalent circuit 9 / 8

10 Table. Relationships between the parameters o the T-type and the π-type equivalent circuits Bipolar Transistors T-type equivalent circuit π-type equivalent circuit C e C b e - α 0 r b e C c C b c - μ ( - α 0 ) r b'c μ α 0 r ce g m r bb r bb 0 / 8

11 .. Circuit parameters Bipolar Transistors () Matrices showing the relationships between the input and the output by voltage and current This method regards a transistor as a our-terminal circuit network to describe it only with the electrical characteristics o its terminals irrespective o the physical characteristics o the transistor. There are six types o matrices (a, b, g, h, y and z) that represent the relationships among the input and output voltages and currents. O the six types, the h and y matrices are used relatively requently. Figure.4 and Figure.5 show the deinitions o the h and y matrices. The suixes e and b ollowing the letters i, r,, and o distinguish between the common-emitter and commonbase conigurations. i i i i h h - h h V V V h i V h h V h + [ V ] = [ h h ] [ i ] = [ h i ] [ i ] i h h V h h o V h r Figure.4 Circuit network using the h matrix i i i i y y V V y y - V y y V y V y V [ i ] = [ y y i y y ] [ V ] = [ y i V y y ] [ V ] o V y r Figure.5 Circuit network using the y matrix The parameters in the matrices have the ollowing meanings: h i : Input impedance y i : Input admittance h r : Reverse voltage eedback ratio y r : Reverse transer admittance h : Forward current gain y : Forward transer admittance h o : Output admittance y o : Output admittance The h matrices are oten used or low-requency regions whereas the y matrices are commonly used or high-requency regions. / 8

12 () Matrix showing the relationships between the input and the output by power Bipolar Transistors The S matrices (scattering matrices) are commonly used to represent the phenomena in microwave circuits such as the relection and transmission o waves. As the requency limits o semiconductor devices increase, the S matrices are sometimes used to describe their circuit parameters. Figure.6 shows the deinitions o the S matrix. a S S a b S S b [ b ] = [ S S ] [ a b S S a ] = [ S i ] [ a S S o a ] S r Figure.6 Circuit network using the S matrix Each parameter has the ollowing meaning: S : Input relection coeicient S : Reverse transmission coeicient S : Forward transmission coeicient S : Output relection coeicient As is the case with the h and y matrices, the suixes e and b denote the common-emitter and common-base conigurations respectively. / 8

13 Table.3 Interrelation o parameters [h] [y] [s] h i h r y i - y r y i ( + s i ) ( + s o ) - s r s ( - s i ) ( + s o ) + s r s s r [h] ( - s i ) ( + s o ) + s r s -s h h o y y i y i y o - y r y y i ( - s i ) ( + s o ) + s r s ( - s i ) ( - s o ) - s r s ( - s i ) ( + s o ) + s r s ( - s i ) ( + s o ) + s r s h i - h r h i y i y r ( + s i ) ( + s o ) - s r s -s r [y] ( + s i ) ( + s o ) - s r s -s h h i h i h o - h r h h i y y o ( + s i ) ( + s o ) - s r s ( + s i ) ( - s o ) + s r s ( + s i ) ( + s o ) - s r s ( h i - ) ( h o + ) - h r h ( - y i ) ( + y o ) + y r y ( h i + ) ( h o + ) - h r h h r ( + y i ) ( + y o ) - y r y -y r s i s r [s] ( h i + ) ( h o + ) - h r h -h ( + y i ) ( + y o ) - y r y -y ( h i + ) ( h o + ) - h r h ( + y i ) ( + y o ) - y r y ( + h i ) ( - h o ) + h r h ( + y i ) ( - y o ) + y r y s s o ( h i + ) ( h o + ) - h r h ( + y i ) ( + y o ) - y r y 3 / 8

14 Table.4 Conversion ormulas or h parameters Converted h parameters Common-base Common-emitter Common-collector Common-base h ib + h b -h b + h b Δh b - h rb + h b h ib + h b h ob + h b - + h b h ob + h b Known h parameters Common-emitter h ie + h e Δh e - h re + h e h ie - h re -h e + h e h oe + h e - ( + h e ) h oe Common-collector -h ic h c -( + h c ) h c -Δh rc h c - h ic - h rc - h oc h c -( + h c ) h oc Δh e = h ie h oe h re h e Δh b = h ib h ob h rb h b Δh c = h ic h oc h rc h c 4 / 8

15 Table.5 Conversion ormulas or y parameters Converted y parameters Common-base Common-emitter Common-collector Known y parameters Common-emit Common-base ter Common-colle ctor y b -( y rb + y ob ) y b -( y ib + y b ) -( y b + y ob ) y ob -( y ib + y rb ) y ib y e -( y re + y oe ) y ie -( y ie + y re ) -( y e + y oe ) y oe -( y ie + y e ) y e y oc -( y c + y oc ) y ic -( y ic + y rc ) -( y rc + y oc ) y c -( y ic + y c ) y c y e = y ie + y re + y e + y oe y b = y ib + y rb + y b + y ob y c = y ic + y rc + y c + y oc 5 / 8

16 Table.6 h parameters converted using T-type equivalent circuit Common-base Common-emitter h ib + r bb' [ ( - α 0 ) + j + j ] h ie r bb' + ( - α 0 ) + j h rb j π C c r bb' h re π α C c j ( - α 0 ) + j h b - α 0 + j h e α 0 ( - α 0 ) + j h ob j π C c h oe π C c j ( + j ) ( - α 0 ) + j Table.7 y parameters converted using T-type equivalent circuit Common-base Common-emitter y ib + j + j r bb' y ie ( - α 0 ) + j + j r bb' y rb - π C c j ( + j ) r + j bb' y re - π C c r bb' j r bb' + j y b - α 0 + j r bb' y e α 0 + j r bb' y ob π C c j ( + r bb' + j r bb' + j α ) y oe Same as or y ob 6 / 8

17 () Common-base () Common-base (a) (b) (a) (b) Im (hib) large 0 R e (h ib ) r bb Im (hrb) large 0 R e (h rb ) Im (y ib) r R e (y ib ) bb' large - π R e (y rb ) large 0 Im (yrb) (c) (d) (c) (d) large - α 0 R e (h b ) 0 Im (hb) Im (hob) large 0 R e (h ob ) large -α 0 R e (y b ) 0 Im (y b) Im (yob) 0 large - π C c ( + R e (y ob ) r bb' ) () Common-emitter () Common-emitter (a) (b) (a) (b) Im (hie) R e (h ie ) r bb r bb ' + β large Im (h re) large β 0 π R e (h re ) Im (y ie) large β 0 -α 0 r R e (y ie ) bb' - π C c r R e (y re ) β large 0 Im (yre) (c) (d) (c) Im (h e) R e (h e ) 0 β β α 0 - α 0 large Im (h oe) 0 β large π R e (h oe ) Im (y e) R e (y e ) β α 0 large Solid line : Theoretical curves Dashed line : Measured curves Figure.7 Frequency locus o h parameters Figure.8 Frequency locus o y parameters 7 / 8

18 See Table.3 to Table.5 or the relationships among the circuit parameters and the conversion between the common-base and common-emitter parameters. Figure.7 and Figure.8 show the requency loci o the h and y parameters obtained rom Table.6 and Table.7 respectively. The parameters described above vary with the operating point and temperature. Circuit designers should understand theiects on the parameters..3. Low-requency, low-noise ampliiers () Designing low-noise ampliiers It is necessary to select and use transistors careully when designing low-noise ampliiers. Voltage, current, and signal source impedance should be considered to ensure that the transistors are used within the ranges that exhibit the best perormance o the transistors. To help circuit designers obtain the best perormance rom low-noise transistors, this section describes the concept o noise characteristics, the optimal conditions o transistors, and the relationships between the noise igures o transistors and the S/N ratios o ampliiers. () Noise characteristics o transistors The noise igure (NF) o a transistor is given by: NF = 0 log ( E si E ni E so ) E no = 0 log ( E si 4 k T R g B E so E no ) ( ) E si E ni : Input signal voltage : Input noise voltage E so : Output signal voltage Eno : Output noise voltage k : Boltzmann constant ( J/ K) T : Absolute temperature (K) R g B : Signal source resistance : Noise bandwidth (Hz) or E ni = 4 k T R g B 8 / 8

19 Figure.9 shows the NF-vs-requency curve, which is divided into three regions: ) / region, ) white noise region, and 3) noise region. - 3 db / oct 6 db / oct Noise igure, NF (db) / noise region White noise region noise region 00 to khz Frequency, (Hz) c βc Figure.9 Relationship between NF and requency Table.8 Types o noise Type Item Description Cause / noise region White noise region noise region Noise decreases at Noise increases at 6 db/oct Noise remains constant -3 db/oct in proportion in proportion to requency over a range o requency. to requency.. Thermal noise caused by Fluctuation caused by Surace luctuation the base spreading current separation resistance r bb Audio applications Noise generated Noise generated Not noise generated 9 / 8

20 A transistor can be modeled with a voltage noise source (e N ) and a current noise source (i N ) as shown below. e N = 4 k T R N B e R R g e i R L i N = q I b B R N : Equivalent noise resistance (Ω) q : Elementary charge (C) Figure.0 Noise source o transistor Considering the ideal transistor without any noise source, the noise igure (NF) is given by: NF = 0 log ( 4 k T R g + e N + i N + Rg + γ en i N 4 k T R g ) ( 3) B γ : Hz : Correlation unction o e N and i N Equation -3 shows that NF is a unction o e N and i N. It is evident rom Equation -3 that the noise igure NF is dependent on the collector current I C and the signal source impedance R g. Let the total noise voltage be e NT. Then, e NT = 4 k T R g + e N + i N Rg + γ en i N ( 4) Figure. shows the relationship between the total noise voltage and the signal source impedance R g. e NT - R g Total noise voltage, ent (nv/hz) Equivalent input noise voltage V CE = 6 V I C = ma = khz B Device C α β Thermal noise voltage o R g = 4kTR g k 0k 00k M Signal source resistance, R g (Ω) Figure. Total noise voltage Signal source resistance 0 / 8

21 Reerring to the curve o Device C in Figure., the noise igure can be seen as a dierence (B) between its noise voltage and the thermal noise at R g = 00 Ω. NF = 0 ( log β - log α ) B in Figure. As can be seen rom Equation -4, voltage noise is more dominant in the small R g region. However, current noise is dominant in the region where Rg increases. R g, e NT, and noise igure can be shown by plotting contours o the constant noise igure as shown in Figure. and Figure.3. Signal source resistance Rg ( ) 00 k 0 k k NF = db NF R g, I C NF = db Common-emitter V CE = 6 V = 0 Hz Signal source resistance Rg ( ) NF R g, I C 00 k Common-emitter V CE = 6 V NF = db = khz 0 k k NF = db Collector current I C ( A) Collector current I C ( A) Figure. NF R g, I C () Figure.3 NF R g, I C () These noise igure contours can be used to determine the optimal usage condition o an ampliier. Use the signal source impedance o the ampliier to obtain the collector current I C at which the noise igure is minimum rom the noise igure contours at = khz and = 0 Hz. When designing a low-noise ampliier, it is necessary to consider the conditions o the circuits preceding and ollowing the ampliier. The next subsection describes an ampliier s noise, considering the oregoing. / 8

22 (3) Ampliier noise The signal-to-noise (S/N) ratio is an important actor in designing an ampliier. S / N = 0 log Rate output Output noise voltage (db) ( 5) From Equation -, Equation -5 can be restated as ollows to include NF. S / N = 0 log E so E no = 0 log E so E no = 0 log ( E si E no NF 0 0 ) = 0 log E si 4 k T R g B - NF ( db ) (-6) Ampliier s S/N ratio (db) = Input S/N ratio (db) - Ampliier s NF (db) Noise igure o multi-stage ampliiers The noise igure o a multi-stage ampliier like the one shown in Figure.4 can be calculated as ollows: NF T = NF + NF - G + NF 3 - G G ( 7) NF T : Total noise igure G G G 3 NF NF NF 3 NF T NF : Noise igure o the irst ampliier NF : Noise igure o the second ampliier NF 3 : Noise igure o the third ampliier G : Power gain o the irst ampliier G : Power gain o the second ampliier G3 : Power gain o the third ampliier Figure.4 Noise igure o a multi-stage ampliier / 8

23 The equivalent noise resistance (R N ) o this ampliier is: R N = R N + R N A + R N3 ( A A ) ( 8) R NT : Total equivalent input noise resistance A A A 3 R N R N R N3 R NT R N : Equivalent noise resistance o the irst ampliier R N : Equivalent noise resistance o the second ampliier R N3 : Equivalent noise resistance o the third ampliier A : Power gain o the irst ampliier A : Power gain o the second ampliier Figure.5 Equivalent noise resistance o a multi-stage ampliier Equation -7 and Equation -8 indicate that, i the power gain o the irst ampliier (A ) is suiciently large, the total noise igure NF T is: NF T NF ( 9) The total noise igure o the multi-stage ampliier is close to that o the irst ampliier. Calculating the total noise igure NF T o a multi-stage ampliier rom the nominal NF parameters o transistors The NF values in the transistor datasheets are the measurements taken at spot requencies (such as khz, 00 Hz, and 0 Hz). These values cannot be used without adjustment to design a wide-bandwidth ampliier with low-requency boost. Since the noise region lies in the high-requency region, only the / and white noise regions are related to low-requency ampliication. Assuming: e g e w e - / : Mean square voltage o the thermal noise generated by signal source resistance R g : Mean square voltage o white noise : Mean square voltage o / noise ( 0) the ollowing equation is derived rom the deinition o the noise igure: NF (white noise region) = e g + ew = NF (khz) e g ( ) NF(kHz) : NF at the -khz spot requency 3 / 8

24 e w is calculated as ollows rom Equation -: e w = ( NF( khz ) - ) e g (-) Let the noise igure at 0 Hz be NF (0Hz). Then, NF ( 0Hz ) = e g + e w + e / ( 0 Hz ) e g ( 3) From Equation (-), e / ( 0 Hz ) = ( NF ( 0 Hz ) - NF ( khz ) ) e g ( 4) Since the / noise decreases at -3 db/oct in proportion to requency, e requency can be calculated as ollows: at a normal e / = ( NF ( 0 Hz ) - NF ( khz ) ) e g 0 ( 5) Reerences ) WILLIAM A.RHEINFELDER : DESIGN OF LOW NOISE TRANSISTOR INPUT CIRCUITS, LONDON ILIFFE BOOKS LTD. (964 ) ) J.WATSON : SEMICONDUCTOR CIRCUIT DESIGN, ADAM HILGE LTD. (970) 4 / 8

25 .4. Switching characteristics When a pulse current is applied to the input terminal IN o the circuit shown in Figure.6, the current waveorms o the base and collector become as shown in Figure.7. The switching times o the transistor are deined as the delay times td, tr, tstg, and t o the output waveorm relative to the input waveorm. V CC I B R LOUT I B Base current A V IN IN I C I B hfe B 90% 0% OUT I C t d t r t stg t Figure.6 Switching time test circuit Figure.7 Switching waveorms and the deinitions o switching times Figure.8 I C vs. h FE t d is a delay time, t r is a rise time, t stg is a storage time, and t is a all time. These expressions are obtained as ollows: t r = τ R h FE ln ( h FE I B h FE I B I C ) ( 5) t stg = τ S ln [ h FE ( I B - I B ) I C - h FE I B ] ( 6) t = τ F h FE ln [ I C - h FE I B 0. I C - h FE I B ] ( 7) where, τ R τ F π T +.7 R L C TC ( 8) τ S = 0.6 π b + τ nc ( 9) 5 / 8

26 C TC h FE T b τ nc : Base-collector capacitance measured at V CC : DC current gain at the end o the saturation region : Transition requency : Base cut-o requency : Lietime o minority carriers in the collector layer Equation -5 shows that t r can be reduced by raising h FE to increase the drive capability o the base drive circuit and by increasing T. Equation -7 denotes that t increases when h FE is increased and decreases when the switching current ratio (I C /I B ) is reduced. Equation -6 indicates that the lietimes o minority carriers in the base and collector layer in relation to the minority carrier recombination process are important actors o t stg. h FE and t stg are in proportion to each other. Thereore, advanced technology is required to reduce all o t r, t, and t stg. Equation -5 to Equation -7 are unctions o h FE. Although it is desirable to reduce h FE in order to reduce the switching times, h FE should be high enough to reduce the base drive power. Figure.8 shows the dependency o h FE on the collector current. h FE has a peak as shown by curve A. The peak o the h FE curve is oten located on the low-current side relative to the operating point shown by the dashed line, with h FE at the operating point being lower than the peak h FE value. Regarding the measurement o the switching times at the operating point, the switching times (particularly t stg ) depend on the peak h FE more strongly than on the h FE at the operating point. The peak h FE value can be reduced by making the h FE curve shallower and moving its peak toward the large-current side as shown by curve B. By doing this, the trade-o between the h FE and switching times, which was a problem in the above case, is ameliorated. A multi-emitter structure increases the eective area o the emitter and thereore helps latten the h FE curve. Equations -8 and -9, which are outer logarithmic terms o Equations -5 to -7, include T and b, i.e., parameters that represent requency responses o a transistor. To increase the breakdown voltage and the sae operating area, it is unavoidable to increase the width and depth o the base at the expense o requency responses. Since the transition requency T ( T < b ) is a ew megahertz, the irst term o Equations - 8 and -9 is considered to be 0 6 to 0 7 seconds. The multi-emitter power transistor improves a requency response an order o magnitude lower than this. The second term o Equation -8, a time constant determined by the collector capacitance and the load resistance, is normally as small as 0 7 to 0 8 seconds. The second term o Equation -9 is o the order o 0-6 seconds. The irst and second terms 6 / 8

27 were almost equal in conventional transistors. However, the switching characteristics o a transistor can be improved by improving the multi-emitter structure because this helps make the irst term negligibly small compared with the second term. In addition, τ nc in the second term can be controlled by diusing heavy metals called lietime killers into the collector layer. The lietime can be made more controllable by making the irst term negligible. As described above, the switching times o a transistor can be reduced by improving the large-current characteristics o h FE (i.e., the h FE linearity) and the high-requency response. 7 / 8

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No responsibility is assumed by TOSHIBA or any inringement o patents or any other intellectual property rights o third parties that may result rom the use o Product. No license to any intellectual property right is granted by this document, whethexpress or implied, by estoppel or otherwise. ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA () ASSUMES NO LIABILITY WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND () DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT. Do not use or otherwise make available Product or related sotware or technology or any military purposes, including without limitation, or the design, development, use, stockpiling or manuacturing o nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). Product and related sotware and technology may be controlled under the applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export o Product or related sotware or technology are strictly prohibited except in compliance with all applicable export laws and regulations. Please contact your TOSHIBA sales representative or details as to environmental matters such as the RoHS compatibility o Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use o controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS. 8 / 8