74VHCT540AFT,74VHCT541AFT

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1 CMOS Digital Integrated Circuits Silicon Monolithic 1. Functional Description Octal Bus Buffer : INERTED, 3-STATE OUTPUTS : NON-INERTED, 3-STATE OUTPUTS 2. General The and are advanced high speed CMOS OCTA BUS BUFFERs fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent Bipolar Schottky TT while maintaining the CMOS low power dissipation. The is an inverting type and, the is a non-inverting type. When either G1 or G2 are high, the terminal outputs are in the high-impedance state. The input voltage are compatible with TT output voltage. These devices may be used as a level converter for interfacing 3.3 to 5 system. Input protection and output circuit eure that can be applied to the input and output () pi without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and input/output voltages such as battery back up, hot board iertion, etc. : Output in off-state 3. Features (1) AEC-Q100 (Rev. ) ( 1) (2) Wide operating temperature range: T opr = -40 to 125 (3) igh speed: Propagation delay time = 5.4 (typ.) at CC = (4) Quiescent supply current: I CC = 4.0 (max) at T a = 25 (5) Compatible with TT input: I = 0.8 (max) I = 2.0 (min) (6) Power down protection is provided on all inputs and outputs. (7) Balanced propagation delays: t P t P (8) ow noise: OP = 1.5 (max) (9) Pin and function compatible with the 74 series (ACT/CT/ACT etc.) 540/541 type. 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales representative. 1 Start of commercial production

2 4. Packaging TSSOP20B 5. Pin Assignment 6. Marking 2

IN OUT I IK I OK I OUT I CC P D T stg (1) (2) (3) (4) -0.5 to 7.0-0.5 to 7.0-0.5 to 7.0-0.5 to CC + 0.

3 7. IEC ogic 8. Truth Table Input G1 Input G2 Input An Output Yn Output Yn X X X X X: Don't care Z: igh impedance Yn: Yn: 9. Absolute imum Ratings () Z Z Z Z Rating Supply voltage Input voltage Output voltage Input diode current Output diode current Output current CC /ground current Power dissipation Storage temperature CC IN OUT I IK I OK I OUT I CC P D T stg (1) (2) (3) (4) -0.5 to to to to CC ±20 ±25 ± to 0 : Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditio (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability andbook ( andling Precautio / Derating Concept and Methods ) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). 1: Output in OFF state. 2: igh () or ow () state. I OUT absolute maximum rating must be observed. 3: OUT < GND, OUT > CC 4: 180 mw in the range of T a = -40 to 85. From T a = 85 to 125 a derating factor of mw/ shall be applied until mw. ma mw 3

4 10. Operating Ranges () Rating Supply voltage Input voltage Output voltage Operating temperature Input rise and fall times CC IN OUT T opr dt/dv (1) (2) 0 to CC -40 to to 20 : The operating ranges must be maintained to eure the normal operation of the device. Unused inputs must be tied to either CC or GND. 1: Output in OFF state. 2: igh () or ow () state. 11. Electrical DC (Unless otherwise specified, T a = 25 ) / Test Condition CC () Typ. igh-level input voltage I 2.0 ow-level input voltage I 0.8 igh-level output voltage O IN = I or I I O = I O = -8 ma 3.94 ow-level output voltage O IN = I or I I O = I O = 8 ma state output OFF-state leakage current I OZ IN = I or I OUT = CC or GND ±0.25 Input leakage current I IN IN = or GND ±0.1 Quiescent supply current I CC I CCT IN = CC or GND Per input: IN = 3.4 Other input: CC or GND ma Output leakage current (Power-OFF) I OPD OUT = DC (Unless otherwise specified, T a = -40 to 85 ) Test Condition CC () igh-level input voltage I 2.0 ow-level input voltage I 0.8 igh-level output voltage O IN = I or I I O = I O = -8 ma 3.80 ow-level output voltage O IN = I or I I O = 0.1 I O = 8 ma state output OFF-state leakage current I OZ IN = I or I OUT = CC or GND ±2. Input leakage current I IN IN = or GND ± Quiescent supply current I CC IN = CC or GND 40.0 Quiescent supply current I CCT Per input: IN = 3.4 Other input: CC or GND 1. ma Output leakage current (Power-OFF) I OPD OUT = 0 4

5 11.3. DC (Unless otherwise specified, T a = -40 to 125 ) Test Condition CC () igh-level input voltage I 2.0 ow-level input voltage I 0.8 igh-level output voltage O IN = I or I I O = I O = -8 ma 3.70 ow-level output voltage O IN = I or I I O = 0.1 I O = 8 ma state output OFF-state leakage current I OZ IN = I or I OUT = CC or GND ±10.0 Input leakage current I IN IN = or GND ±2.0 Quiescent supply current I CC IN = CC or GND 80.0 I CCT Per input: IN = 3.4 Other input: CC or GND 1. ma Output leakage current (Power-OFF) I OPD OUT = AC (Unless otherwise specified, T a = 25,, Input: t r = t f = 3 ) Propagation delay time 3-state output enable time 3-state output disable time Output skew Input capacitance Output capacitance Power dissipation capacitance Part Number t P,t P t P,t P t PZ,t PZ t PZ,t PZ t os,t os C IN C OUT C PD ( 1) ( 2) Test Condition R = 1 kω R = 1 kω CC () ± 0.5 ± 0.5 ± 0.5 ± 0.5 ± 0.5 C () 1: Parameter guaranteed by design. (t os = t P m-t P n, t os = t P m-t P n ) 2: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation. I CC(opr) = C PD CC f IN + I CC /8 (per bit) AC (Unless otherwise specified, T a = -40 to 85,, Input: t r = t f = 3 ) Typ Part Number Test Condition CC () C () Propagation delay time t P,t P ± t P,t P ± state output enable time t PZ,t PZ R = 1 kω ± state output disable time t PZ,t PZ R = 1 kω ± Output skew t os,t os ( 1) ± 0.5 Input capacitance C IN 10 1: Parameter guaranteed by design. (t os = t P m-t P n, t os = t P m-t P n ) 5

6 11.6. AC (Unless otherwise specified, T a = -40 to 125,, Input: t r = t f = 3 ) Propagation delay time 3-state output enable time 3-state output disable time Output skew Input capacitance Part Number t P,t P t P,t P t PZ,t PZ t PZ,t PZ t os,t os C IN ( 1) Test Condition R = 1 kω R = 1 kω CC () ± 0.5 ± 0.5 ± 0.5 ± 0.5 ± 0.5 1: Parameter guaranteed by design. (t os = t P m-t P n, t os = t P m-t P n ) C () Noise (Unless otherwise specified, T a = 25,, Input: t r = t f = 3 ) Test Condition CC () Typ. imit Quiet output maximum dynamic O OP C = Quiet output minimum dynamic O O C = imum high-level dynamic input voltage ID C = 2.0 imum low-level dynamic input voltage ID C = 0.8 6

7 Package Dimeio : mm Weight: g (typ.) Package Name(s) Nickname: TSSOP20B 7

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Before customers use the Product, create desig including the Product, or incorporate the Product into their own applicatio, customers must also refer to and comply with (a) the latest versio of all relevant TOSIBA information, including without limitation, this document, the specificatio, the data sheets and application notes for Product and the precautio and conditio set forth in the "TOSIBA Semiconductor Reliability andbook" and (b) the itructio for the application with which the Product will be used with or for. Customers are solely respoible for all aspects of their own product design or applicatio, including but not limited to (a) determining the appropriateness of the use of this Product in such design or applicatio; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such desig and applicatio. TOSIBA ASSUMES NO IABIITY FOR CUSTOMERS' PRODUCT DESIGN OR APPICATIONS. PRODUCT IS NEITER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS TAT REQUIRE EXTRAORDINARIY IG EES OF QUAITY AND/OR REIABIITY, AND/OR A MAFUNCTION OR FAIURE OF WIC MAY CAUSE OSS OF UMAN IFE, BODIY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBIC IMPACT ("UNINTENDED USE"). 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TC7SZ08FU TC7SZ08FU. 1. Functional Description. 2. Features. 3. Packaging Rev Toshiba Corporation

TC7SZ08FU TC7SZ08FU. 1. Functional Description. 2. Features. 3. Packaging Rev Toshiba Corporation CMOS Digital Integrated Circuits TC7SZ08FU Silicon Monolithic TC7SZ08FU 1. Functional Description 2-Input AND Gate 2. Features (1) AEC-Q100 (Rev. ) (Note 1) (2) Wide operating temperature range: T opr