Increasing Voltage Gain by New Structure of Inductive Switching DC-DC Converter

Transcription

1 AUT Jural f Electrical Egeerg AUT J. Elec. Eg., 49(( DO: 0.060/eej creag Vltage Ga by New Structure f ductie Switchg D-D erter S. Nabati, A. Siadata *, S. B. Mzafari Departmet f Electrical Eg., Sciece ad Reearch Brach, lamic Azad Uierity, Tehra, ra Dept. f Electrical Eg., Faculty f Techical & Egeerg, Wet Tehra Brach, lamic Azad Uierity, Tehra, ra ABSTRAT: a phtltaic ytem, u light eergy i certed t electricity. The geerated electricity ha a lw D ltage. rder t creae ltage geerated by phtltaic cell (PV, a additie D-D certer i required t raie the lw ltage t a gd leel which pride the cditi fr cecti t D-D certer. w wate, lw ct, ad high efficiecy are me ther pecificati f uch certer. Thi paper preet a ew tructure fr a additie D-D certer with ductie ad capacitr witchg fr creag high ltage ga t be ued PV ytem. t i baed the ductie ad -ulated witchg which creae ltage a duty cycle up t 0 time f put ltage. additi, ug a witch, lw elemet, ad al lw ltage tre the witch i the adatage f thi ew etup. The eay creag f leel t reach the higher ltage i ather beefit f thi tructure. The paper ctue with the aalyi f circuit fucti ad PWM (Pule Width Mdulati adjutmet. PSAD/EMTD ftware i ued fr cfirmg the autheticity f the perfrmace f the uggeted mdel. The reult are preeted. Reiew Hitry: Receied: 7 April 06 Accepted: 3 May 07 Aailable Ole: 5 July 07 Keywrd: PV D-D erter High Vltage Ga PWM PSAD Sftware - trducti The ue f equipmet with lw ct ad high efficiecy ha alway bee cidered the dutry. Therefre, there are much mre demad fr creag the ltage ga f D-DA certer. Sme imprtat applicati f uch certer are PV ytem ad ballat lamp with a high charge [, ]. Scietifically, additie certer ca gly preet ay ltage ga the utput becaue it ltage ga relati i where d i the duty cycle. A d creae, the d ga creae. Hweer, the dide wate ad al ltage tre the witch creae practice which fally lead t a reducti f the ga. Therefre, may effrt hae bee made ad differet methd hae bee preeted er the tw recet decade t creae ltage ga ad the retur f uch certer [3]. Thee methd are diided t tw grup. Oe methd make ue f the baic tructure f additial certer which capacitr are the termediate f urce ad charge [4-6], ad a the umber f capacitr creae, the umber f utput ltage clae creae. apacitr witchg were ued me article. They are called -ulated certer [7,8]. the paper [9], mre capacitr ad dide hae bee ued t hae a higher ga but ltage tre the witch creaed, ad the certer retur reduced. Ather methd i t ue ductr ad trafrmer certer which are called ilated certer, ad their mechaim i t trafer eergy baed the magetic ccept. Article [0] preet a additie certer baed ductr which the ductr leakage creae a rie. Sme paper hae uggeted a cmbati f tw methd which hae achieed much ucce [0]; Hweer, the The crrepdg authr; iadata@wtiau.ac.ir prducti ct i high. Thi paper preet a ew tructure f additie D-D certer, with ductie ad capacitr witchg fr the phtltaic ytem (PV, which ca pride ay ltage requeted the utput by creag ad reducg the clae additi t high ga ltage ad lw prducti ct. The ma adatage f thi tructure i t ue a witch ad fewer elemet tha ther tructure, like the tructure prped the paper []. The exitece f erial ductr with capacitr ad dide will limit the curret ad aid impact curret pag thrugh the circuit. The paper i rgaized a it fllw. Secti expla the certer tructure. Secti 3decribe the certer fucti differet mde, ad Secti 4 preet the reult f the imulati with PSAD ftware. - Structure f the uggeted certer Baic erter: Figure hw the baic tructure f the prped certer. Three dide ad tw ductr are ued thi tructure. Dide D ad D are tured ad dide D i tured ff time teral T ; therefre, ductr ad are placed parallel t each ther ad charged by a ltage urce, ad =. Dide D ad D are tured ff ad dide D i tured time teral T ff. The created path put the ductr ad erie with the uer, ad the eergy aed ductr i dicharged the utput lad i =i. Prped Structure The uggeted tructure i dicated Figure 3. The certer cit f + ductr, 3 capacitr, ad 3- dide, where. The methd ued fr creag the clae by creag a defite umber f dide ad ductr ductr blck i hw. apacitr will caue the crrect fucti f turg ad ff the dide D ad D. thi 73

2 S. Nabati et al., AUT J. Elec. Eg., 49(( , DO: 0.060/eej tructure, the fucti f the certer witchg time teral T ad T ff i the creag f utput ltage by witch S. capacitr ad ductr pride ductie ad capacitr witchg. preiu cycle ad it ltage i le tha. Therefre, dide D i direct bia ad i. Dide D i reere bia with a ltage equal t ad i ff. ider that capacitr i charged frm the preiu tep ad keep it charge. apacitr i charged fr thrugh the path made by the dide. Fig.. ductr Blck Fig. 4. ircuit Time teral T (a (b Fig.. Equialet ircuit ductr Blck Time teral T,T ff Fig. 5. ircuit Time teral T ff Fig. 3. Structure f Suggeted erter Fr aimple aalyi, the fllwg hypthee are cidered:. pwer upply ltage i flat withut ripple;. all elemet are deemed ideal; 3. all ductr hae the ame.amut 3- The fucti f uggeted certer: Fucti f tuu ducti Mde(M ircuit aalyi thi mde a time teral T after the traiet tate i a fllw: time teral 0 t DT : accrdg t Figure 4, witch S i cected thi time teral ad dide D,D 3,D 4,...,D ad D,D 3,D 4,...,D are parallel with ltage urce direct bia. Dide D 3,D 33,D 43,...,D 3 are adere bia ad ff. The ltage f their bth ide i equal t. Thu, ductr,, 3,..., are placed charge path ad erie t a ltage urce. The ltage f their bth ide i, ad al their curret reache i max. The fucti f capacitr ad with dide D ad D i aalyzed a way that capacitr i dicharged frm the Fig. 6. Frm f Wae f ircuit Elemet Mde M 74

3 S. Nabati et al., AUT J. Elec. Eg., 49(( , DO: 0.060/eej Accrdg t the gie explaati, the fllwg relati are btaed fr the time teral T : The ltage f ductr are btaed a fllw: apacitr i fully charged: The fllwg relati i btaed by KV the utput circuit lp: The ltage f ff-dide cluded adere bia i a fllw: The ductr curret i btaed by ductr ad tegrati relati: time teral DT t T : witch S i ff. Figure 5 dicate the tructure thi time teral. mmediately after dicectg ductr witch, egatie plarity i elected rder t aid the curret dicecti frm the preiu tep; thu, all dide D,D 3,D 4,...,D ad D,D 3,D 4,...,D are ff. t caue dide D 3,D 33,D 43,...,D 3 t becme tured ad dide D tur becaue a ltage equal t (+ ha bee made it ade. Mreer, reere bia dide D with a ltage equal t the ltage f capacitr tur ff. Therefre, the path f the urce f ltage, ductr, ad the capacitr, t make erie with utput lad i prided t preet the maximum ltage the utput. Figure 6 dicate the wae f me circuit elemet mde M. The fllwg relati are btaed fr the certer fucti the ecd time teral. The ductr ltage i btaed frm KV by Sce the utput ltage i ctat, the curret f utput capacitr i zer; thu, ly fixed curret pae thrugh R ductr which make it ltage zer. thi cae, there are the fllwg cditi: Ad the fllwg relati i btaed frm relati (8: A bia ltage f ff dide i the ecd time teral a = =... = = ( = =... = = ( = = + = =... = = D D D D = di = dt i = t + i m = = = ( (3 (4 (5 (6 (7 (8 (9 (0 D D D 3 = =... = = D D D D 3 = fllw where the ltage f ductr are deemed the ame ( dt T 0 (4 0 dt + dt = T dt equal t V : Vlt-ecd balace rule fr the ductr i a fllw: M M d( + = = d Ug the metied relati, a ideal ga ltage fr the D d( + = = d uggeted certer uder M will be a it fllw: The relati (3 i meaured by relati (9 ad (5: d( + = [ ( + ] ( d ( (3 (5 (6 (7 The ltage tre witch S i btaed frm the fllwg relati: = ( i t + i max (8 The curret ize f ductr thi time teral i attaed frm the fllwg relati: Nw, we ca meaure the aerage utput curret. Suppe that the capacity f the utput capacitr i high uch that fixed ltage bth ide are btaed. Therefre, the aerage (9 = i d0 i D0 curret f the utput capacitr i zer becaue the ltage i ctuu, i.e. where i the aerage curret f dide D. t pae the i d (0 curret ly the ecd time teral, ad ha a curret equal t the ductr curret, i.e. T = ( ( t + i ( d T max T = i = ( d ( imax + im ( After tegratg the whle time teral, the aerage utput curret i btaed: Fucti f Suggeted erter uder DM (Dictuu ducti Mde: thi mde, the ductr curret de t reach the maximum 75

4 S. Nabati et al., AUT J. Elec. Eg., 49(( , DO: 0.060/eej mde M the cpe f ize d f ductr curret, ad the eergy aed the ductr i zer befre the ed f the Fig. 7. urret i Mde DM. ecd time teral. thi mde, i m =0. Figure 7 dicate the frm f wae i thi mde ad ther mde t M. Accrdg t Figure 7, the ltage gaed thi mde i btaed M DM d + d = = d (3 ug the relati f the ductr ltage the firt ad ecd time teral ad aerage frmula hw equati 3. The aerage curret f the utput capacitr i zer; c dt i = T T max 0 (4 hece, the figure 8 ha bee reulted frm the fllwg equati: d T = (5 c 0 ( M DM The fllwg relati hld after the replacemet f relati (3 ad (7: M DM d = = + + t (6 Gie (5 t ad that the ga ltage i equal t zer thi = f R mde, thi i btaed: where. Fucti f Suggeted erter uder BM (Budary ducti Mde = ( d ( imax thi mde, the ductr curret reache zer; i.e. i m =0. i max = V ( dt The relati ( i implified a fllw: i max i btaed frm the relati (7 a: d = ( dv f (7 (8 (9 i btaed accrdg t d by ertg the relati (8 relati (7: d ( d = V f d ( + (30 The equati (5 i reied a fllw accrdg t utput ltage: d ( d t d( + d ( d f ( d = d( + (3 (3 The relati (3 i btaed becaue the mde M i larger tha budary mde: Figure 9 hw f(d accrdg t (=. f t i larger tha f(d, the certer fucti i placed the mde M a per d but it i impible practice becaue ducti r frequecy hall be large thi cae. See Figure 9. The charge le cre t tw pt ad etablihe three ze. The Fig. 8. Wae f DM Mde Fig. 9. Diagram f(d with repect t d middle ze f the certer fucti i uder mde DM ad the ther tw ze M. 4- Simulati reult mde ccm: T tudy the accuracy f the certer fucti, a circuit with pecificati metied Table ha bee imulated with the help f PSAD/EMTD. Gie =3, the ductr blck clude three ductr ad ix dide a utput ltage creae t 500V by regardg d=50% (Figure 0. Figure hw curret ripple ic which i ery lw. The ductr placed the ductr blck hae the ame charge ad dicharge curret ad frm f wae i. Figure dicate 76

5 S. Nabati et al., AUT J. Elec. Eg., 49(( , DO: 0.060/eej Table. ircuit parameter fr imulati V 00V P.5KW 400mH f 0KH 3 400mH d 50% R 00W 3 400mH 00mF 00mF 400mH 3 00mF 0 00mF, ad the way f turg ad ff D i preeted Figure 3. Al, Figure 4 dicate the ripple f ltage. 5- mpari f uggeted certer with certer [3] ad []: Table preet a cmpari f certer aalyzed [3] ad [] with the uggeted certer. Fr example, perfrmace Table. mpari f uggeted certer with certer [3] ad [] ltage duty cycle d=7.7% Vltage Ga V V tre witch Switch umber [] V [3] V Suggeted erter: = V Fig.. The Vut ad V (Time Hrizetal e [] t 0.04 Prped certer erter[3] erter[] Fig.. Vltage Wae V (Time Hriztal e [] d Fig. 5. Diagram t Accrdg t d id0[a] Fig. 3. urret Wae i DO (Time Hriztal e [] Vc[k] Fig. 4. Vltage Wae c(time Hriztal e [] perid d=7.7%, the ltage ga f uggeted certer wa 0, ad the ltage tre witch wa reduced. Figure 5 hw diagram t with repect t the d. A hw, the uggeted certer ha prper perfrmace M mde. 6- ONUSON The imple tructure f the uggeted certer i able t creae the ltage by the ductie witchg blck ad the cmbati f capacitr ad dide. Al, a higher ltage wuld be achieed by addg dide ductie leel. Thi certer ha fewer elemet tha the certer []. Mreer, a high ltage ga will be btaed by placg a urce t the circuit tw tate f witchg. Becaue f the capacitr, erie with the witch, ltage tre the witch decreae ad the exitece f erial ductr with utput capacitr will reduce the utput ltage ripple. ducti mde i a bit greater M. The utput ltage may creae by 0V (d=7.7%, =3 fr a PV ytem with utput electricity V by tallg thi certer. Fally, thi paper aalyzed the certer fucti ctuu, dictuu, ad budary mde. The ltage ad curret f me 77

6 S. Nabati et al., AUT J. Elec. Eg., 49(( , DO: 0.060/eej Referece [] W.-Y. hi, J.-S. Y, J.-Y. hi, High efficiecy dcdc certer with high tep-up ga fr lw PV ltage urce, : Pwer Electric ad EE Aia (PE & EE, 0 EEE 8th teratial ferece, EEE, 0, pp [] Q. Zha, F.. ee, High-efficiecy, high tep-up D-D certer, EEE Traacti Pwer Electric, 8( ( [3] B. Wu, S. i, S. Keyue, A ew hybrid btg certer, : Eergy eri gre ad Expiti (EE, 04 EEE, EEE, 04, pp [4] M. Prudete,.. Pfitcher, G. Emmederfer, E.F. Rmaeli, R. Gule, Vltage multiplier cell applied t -ilated D D certer, EEE Traacti Pwer Electric, 3( ( [5] S. ee, P. Kim, S. hi, High tep-up ft-witched certer ug ltage multiplier cell, EEE Traacti Pwer Electric, 8(7 ( [6] J.. Ra-ar, J.M. Ramirez, F.Z. Peg, A. Valderraba, A D D multileel bt certer, ET Pwer Electric, 3( ( [7] F.. u, H. Ye, Pitie utput multiple-lift puh-pull witched-capacitr u-certer, EEE traacti dutrial electric, 5(3 ( [8] J.A. Starzyk, Y.-W. Ja, F. Qiu, A D-D charge pump deig baed ltage dubler, EEE Traacti ircuit ad Sytem : Fudametal Thery ad Applicati, 48(3 ( [9] F.. u, H. Ye, Pitie utput uper-lift certer, EEE Traacti Pwer Electric, 8( ( [0] N. Vazquez,. Etrada,. Heradez, E. Rdriguez, The tapped-ductr bt certer, : dutrial Electric, 007. SE 007. EEE teratial Sympium, EEE, 007, pp [] T.-F. Wu, Y.-S. ai, J.-. Hug, Y.-M. he, Bt certer with cupled ductr ad buck bt type f actie clamp, EEE Traacti dutrial Electric, 55( ( [].-S. Yag, T.-J. iag, J.-F. he, Trafrmerle D D certer with high tep-up ltage ga, EEE Traacti dutrial Electric, 56(8 ( Pleae cite thi article ug: S. Nabati, A. Siadata, S. B. Mzafari, creag Vltage Ga by New Structure f ductie Switchg D-D erter, AUT J. Elec. Eg., 49(( DO: 0.060/eej