Theoretical Stability Analysis of Isolated Bidirectional Dual Full Bridge DC-DC Converter

Transcription

1 Aia Pwer Electric Jural, l. 7, N., Sep 03 heretical Stability Aalyi f Ilated Bidirectial Dual Full Bridge DC-DC Cverter K. Wu C. W. de Silva W. G. Dufrd Abtract hi per preet a ew methd fr theretical tability aalyi f a bidirectial dual full bridge DC-DC cverter with triple phae-hift ctrl. he develped prach i aalytically ud ad geerally plicable whe cmpared with the exitig prache, which are by ad large baed cmputer imulati. he peratig prce f a bidirectial cverter i multi-tage ad liear, which i explaied by givig ciderati t the ctrl methd that i ued. Baed it wrkig thery, the cverter i eparated it everal tage. Equivalet circuit ad tate equati are built fr each tage t determie the tability i each tage. he, abrupt tate chage ad the repe t ifiite ie are aalyzed fr tage traiti. Next, the tability f the bidirectial cverter i determied uig the eigevalue methd. he aalytical reult are validated thrugh cmputer imulati. Secti I. I Secti, the tability f the bidirectial cverter i determied with the develped methd, whe the iput vltage chage arbitrarily. he reult btaied frm the aalyi are validated uig imulati ad dicued i Secti I. he mai ctributi f the per are ummarized i Secti II. Keywrd Bidirectial ilated DC-DC cverter, tability aalyi, triple phae-hift ctrl, equivalet circuit, tate equati, eigevalue methd. I. INRODUCION I recet year, the develpmet f high pwer ad large pwer rage ilated bidirectial dc-dc cverter ha becme a imprtat tpic becaue f the requiremet f electric autmbile, uiterruptible pwer upply ad aviati pwer ytem [], [], [4], [9]. A idetical dual active full bridge cverter with zer vltage witchig (ZS) ca be ued bth ide f the ilati trafrmer a hw i Fig. [3, 5,4]. Stability i a imprtat requiremet i ay practical egieerig ytem [-8]. Sme parameter f a bidirectial cverter may chage arbitrarily, ad it i imprtat that cverter perate prperly uder thee cditi. hi per preet a effective prach, uig the eigevalue methd, t determie the tability f a liear bidirectial DC-DC cverter whe the parameter chage arbitrarily. he vel prach f triple phae-hift ctrl i ued i thi per a it ca imprve ytem efficiecy ad adtability t parameter chage. hi methd develped i thi per may be ued t tudy tability f ther imilar liear time-varyig circuitry a well. he rgaizati f the ret f the per i a fllw. he prblem addreed i the per i decribed i detail i Secti II. he tability aalyi methd ued i the per i decribed i Secti III. he perati f the bidirectial dual full bridge cverter with the vel triple phae-hift ctrl i aalyzed ad the equivalet circuit are derived i he per firt received 30 Nv 00 ad i revied frm Apr 03. Digital Ref: APEJ Departmet f Electrical ad Cmputer Egieerig, he Uiverity f Britih Clumbia, acuver, BC, Z4, Caada Departmet f Mechaical Egieerig, he Uiverity f Britih Clumbia, acuver, BC, Z4, Caada wukuiyua00@htmail.cm Fig. : he pwer circuit f the bidirectial cverter. II. PROBLEM DESCRIPION. Statemet f the Prblem I pwer electric, tability f a pwer cverter i uually determied thrugh imulati becaue it i liear ytem whe tability aalyi i quite difficult. hi i epecially true fr high pwer zer vltage witchig (ZS) cverter [0], []. Hwever, the methd f imulati i t alway prpriate becaue imulati reult ly prvide ifrmati uder pecific wrkig cditi. Whe iput vltage chage fr me rea, the cverter will wrk i a differet tate. It i impible t imulate the ifiite umber f uch wrkig cditi that are pible. Aalytical determiati f tability aalyi i mre geeral, ad i deired i thi backdrp [7]. hi per preet a effective methd t determie the tability f a bidirectial DC-DC cverter with triple phae-hift ctrl uder pible iput vltage chage. Fr thi purpe, firt a mathematical mdel ha t be develped fr the bidirectial cverter with dual phaehift ctrl, which i a liear ytem. Beide thi, the iput vltage chage mut be take it accut whe determie it tability. he prblem i exacerbated by the fact that the iput vltage ca chage, ad thi chage i ukw i geeral. Althugh the prblem f tability aalyi ca be difficult ad cmplex, the peridic perati f a bidirectial cverter ca be aalytically repreeted. he bidirectial cverter i eparated it everal tage i e perid, guided by reult frm cmputer imulati

2 uder rmal cditi. A equivalet circuit i develped fr every tage f perati by prximatig the liear pwer witche ad dide with liear e; fr example, replacig the pwer MOSFE with a reitace whe it cduct ad replacig the dide with vltage urce f their cducti vltage value. I thi maer, a prximately liear time-varyig equivalet circuit mdel i etablihed fr each tage r ub-tage. Accrdig t the equivalet circuit, the prximately tate equati ca be built fr each tage r ub-tage. hi facilitate the tability aalyi f the bidirectial cverter i every tage ad withi the etire perid f perati.. Cmpet i Pwer Circuit he cmpet i the pwer circuit f the cverter are idetified belw. L0, L w erie iductr C=C=C3=C4=C5=C=C7=C8 --- Eight ubber cacitr C, C ---w large filter cacitr R --- Frward lad reitr he parameter f the mai trafrmer are a fllw: Lp ---Primary leakage iductace L --- Secdary leakage iductace Rp --- Primary widig reitace R--- Secdary widig reitace ur rati: : he parameter f the eight pwer MOSFE are a fllw: R, R, R3, R4, R5, R, R7, R O-reitace D, D, D3, D4, D5, D, D7, D8 --- Ati-parallel dide with pwer MOSFE. 3. ariable Ued i the Per i, ia ---Pwer circuit primary curret ad ecdary curret f the trafrmer c, c, c3,, c5, c, c7, c8 ---ltage acr the crrepdig parallel cacitr. ---Iput vltage ---Output vltage D, D, D3, D4, D5, D, D7, D8 ----Frward cducti vltage f ati-parallel dide. K. Wu et. al: heretical Stability Aalyi f Ilated Baed thi idea, the frward bidirectial dual full bridge cverter i eparated it eight mai tage fr the purpe f theretical aalyi f it tability. here are abrupt tate chage durig the traiti betwee tw tage becaue the tw tage are cected with each ther by the cacitr vltage ad iductr curret. It i well kw they cat chage abruptly. herefre, the frward bidirectial dual full bridge cverter with triple phae-hift ctrl will be table if it i table i each tage. Oly the frward repe i cidered i the preet aalyi. he tability f the backward bidirectial dual full bridge cverter with triple phae-hift ctrl ca be aalyzed imilarly.. Cmpet Parameter i Pwer Circuit L0=7.3μH; C=C=C3=C4=C5=C=C7=C8=F; L0=.9μH; C=C=500μF; R=40Ω; Lp=0.μH; L=μH; Rp=7mΩ; R=0mΩ; =7/ he parameter f the 8 pwer witche are a fllw: r~r4: O reitace: 5mΩ; Dide ltage drp: r5~r8: O reitace: 3mΩ; Dide ltage drp: 0. I. EQUIALEN CIRCUIS he frward imulati wave-frm f the bidirectial cverter with rmal teady tate perati are hw i Fig.. A hw, the triple phae-hift ctrl methd iclude three phae-hift. he firt i the phae-hift betwee the primary ctrl igal ad the crrepdig ecdary ctrl igal, fr example, betwee g ad g5; the ecd i the phae-hift betwee the diagal ctrl igal i the primary pwer circuit, fr example, betwee g ad g4; ad the third i the phae-hift betwee the diagal ctrl igal i the ecdary pwer circuit, fr example, betwee g5 ad g8. III. SABILIY ANALYSIS OF DUAL FULL BRIDGE CONERER. he Methd he bidirectial DC-DC cverter ha may liear cmpet, ad i eetially a liear ytem durig it etire perid f perati. Hwever, it ca be eparated it everal liear tage accrdig t the imulati wave-frm uder rmal wrkig cditi. he equivalet circuit ad the crrepdig tate equati ca be etablihed fr each tage. Uig thee tate equati, tability ca be aalyzed fr every tage. If the cverter i table i every tage ad there i abrupt tate chage at the iterface f tw tage, thi cverter will be table durig the etire wrkig perid. I thi ctext, fr aalytical purpe, abrupt tate chage mea a itataeu chage i the tate variable at the iterface f differet tage.

3 Aia Pwer Electric Jural, l. 7, N., Sep 03 Fig. : Simulati wave frm f the frward bidirectial cverter with triple phae-hift ctrl. he frward bidirectial dual full bridge cverter i eparated it eight tage i e perid. It perati ad the equivalet circuit fr every tage are decribed belw. A. Stage (t0~t) Pwer witche r ad r4 will tur at t=t0. Becaue the primary curret i till egative durig thi perid, the primary curret will flw thrugh r4/r ad the iductr eergy flw back t the pwer urce. he the curret flw thrugh r/d8. he eergy i tred i the ecdary iductr L0 ad the leakage iductr becaue thi i a freewheelig perid with pwer trafer t the lad, i thery. Output cacitr prvide eergy t the lad ad the utput vltage ctiue t reduce i thi perid. he equivalet circuit i thi tage i give i Fig. 5. Becaue g5/g8/g7 are equal t zer, r5/r8/r7 are all i the Off tate; g=, r i O. Ia<0 ad ecdary curret flw thrugh r/d7. he iductr L0 ad utput cacitr prvide eergy t the lad. he utput vltage reduce durig thi perid. he equivalet circuit i thi tage i give i Fig. 3. Fig. 5: Free-wheelig equivalet circuit i tage. r tur ff jut befre t. he ecdary curret will charge the ubber cacitr C ad dicharge the ubber cacitr C5. Durig thi very hrt perid f traitial time, the ecdary curret flw thrugh D8 t charge ad dicharge the ubber cacitr. Whe C5 i ttally dicharged (d5=0), the ecdary curret will flw thrugh D5/D8 ad the eergy will be traferred t the lad. he crrepdig equivalet circuit are hw i Fig. ad Fig. 7. Fig. 3: Equivalet circuit i tage. B. Stage (t~t) Becaue g/ g4 =, pwer witche r ad r4 are i O tate i thi perid. Becaue the primary curret i pitive durig thi perid, the primary curret will flw thrugh r/r4, iductr L0 ad the trafrmer leakage iductace. he eergy will trafer frm the primary ide t the ecdary ide. Becaue g5/g8/g7 are equal t zer, r5/r8/r7 all are i the Off tate; g=, r i O. Ia>0 ad ecdary curret will charge cacitr C7 ad dicharge cacitr C8 util it vltage reduce t the frward cducti vltage f dide D8. he crrepdig equivalet circuit i give i Fig. 4. Fig. : Charge-dicharge equivalet circuit i tage. Fig. 7: Dide cduct equivalet circuit i tage. Fig. 4: C8 dichargig equivalet circuit i tage. C. Stage 3 (t~t3) he ctrl igal g5/g8=. he pwer witche r5/r8 will tur at t. Becaue Ia>0 durig thi tage, the ecdary ide curret will flw thrugh r5/r8 ad trafer eergy t the lad. he utput vltage will 3

4 icreae. he equivalet circuit i thi tage ca be btaied a befre, ad i hw i Fig. 8. D. Stage 4 (t3~t4) Here g4/g8=0;, r4/r8 will tur ff at t 3. Fr the primary ide, r4 tur ff at t 3. he primary curret will charge the ubber cacitr C4 ad dicharge the ubber cacitr C3. Whe C3 i cmpletely dicharged (d3=0), the primary curret will flw thrugh r/d3 ad frm a free-wheelig ub-tage. N pwer i traferred t the ecdary ide, i thery. Fr the ecdary ide, the curret ia>0. hi idicate that r5/d8 will ctiue t cduct i thi perid f time. he additial iductr L0 ad the ecdary leakage iductace will prvide eergy trafer t the lad. he utput vltage will ctiue t icreae i thi tage. he crrepdig equivalet circuit are hw i Fig. 9 ad Fig. 0. K. Wu et. al: heretical Stability Aalyi f Ilated C i cmpletely dicharged (d=0), D will cduct ad frm a eergy feedback t the pwer urce. herefre, r/r3 will tur at t4 uder ZS. Becaue the primary curret I>0, the eergy will feedback t the primary urce i thi tage. Fig. 0: Free-wheelig equivalet circuit i tage 4. r tur ff jut befre t 4. he primary curret will dicharge the ubber cacitr C ad charge the ubber cacitr C. Durig thi very hrt traitial time, the curret will flw thrugh D3 t charge ad dicharge the cacitr. Whe C i cmpletely dicharged (d=0), D will cduct ad frm a eergy feedback t the pwer urce. hi will make it feaible fr r/r3 t tur uder ZS. he crrepdig equivalet circuit are hw i Fig. ad Fig.. Fig. : C dicharge equivalet circuit i tage 4. Fig. 8: Eergy trafer equivalet circuit i tage 3. Fig. : Eergy feedback equivalet circuit i tage 4. Fr the ecdary ide, g5=;, r5 i O i thi tage. g/g7/g8=0;, r/r7/r8 all will be i the ff tate durig thi perid f time. Becaue the ecdary ide curret Ia>0, r5/d8 will cduct i thi perid f time. he iductr L0, the ecdary leakage iductr ad the utput cacitr tgether will prvide eergy t the lad i thi tage. he utput vltage begi t reduce i thi tage. Accrdig t thi aalyi, the equivalet circuit fr thi tage may be btaied a befre. Fig. 9: C3 dicharge equivalet circuit i tage 4 E. Stage 5 ( t4~t5) Becaue g/g3=, r/r3 will tur at t4. r tur ff jut befre t4. he primary curret will dicharge the ubber cacitr C ad charge the ubber cacitr C. Durig thi hrt traitial perid, the curret will flw thrugh D3 t charge ad dicharge the cacitr. Whe F. Stage (t5~t) Becaue g/g3=, r/r3 will be i thi tage. Becaue the primary curret I<0, the eergy will trafer t the ecdary ide agai. Fr the ecdary ide, g5=;, r5 i tate i thi tage. g/g7/g8=0;, r/r7/r8 all will be i the ff tate durig thi perid f time. Becaue the ecdary ide curret Ia<0, the ecdary curret will charge the cacitr C8 ad dicharge the cacitr C7 util it 4

5 Aia Pwer Electric Jural, l. 7, N., Sep 03 vltage reduce t the frward cducti vltage f dide D7. he the curret will flw thrugh r5/d7 i thi perid f time ad frm a freewheelig perid with eergy trafer t the lad, i thery, i thi tage. he eergy frm the primary urce i tred i L0 ad the leakage iductr. he utput cacitr prvide eergy t the lad ad the utput vltage will ctiue t reduce i thi tage. he equivalet circuit ca be btaied a bre, fr thi tage. G. Stage 7 (t~t7) Becaue g/g7=, r/r7 will tur at t. g5=0;, r5 tur ff jut befre t. he ecdary curret will charge C5 ad dicharge C. Durig thi very hrt f traitial time, the ecdary curret will flw thrugh D7 t charge ad dicharge the ubber cacitr. Whe C i cmpletely dicharged (d=0), D will tur ad D/D7 will cduct t frm ZS ad trafer eergy t the lad. Becaue the ecdary ide curret Ia<0, r/r7 will cduct i thi perid f time ad trafer eergy t the lad, ad the utput vltage will icreae i thi tage. he equivalet circuit i thi tage ca be btaied a befre. H. Stage 8 (t7~t8) Becaue g3/g7=0 at t7, r3/r7 will tur ff at t7. O the primary ide, r3 will tur ff; ad the primary curret will charge C3 ad dicharge C4. Durig thi very hrt f traitial time, the primary curret will flw thrugh r t charge ad dicharge the ubber cacitr C3 ad C4. Whe C4 i cmpletely dicharged (d4=0), D4 will tur. r/d4 will cduct. hi will frm a freewheelig tage with eergy trafer t the ecdary ide theretically. r tur ff jut befre t8. he eergy tred i the additial iductr L0 ad the trafrmer leakage iductace will charge the ubber cacitr C ad dicharge the ubber cacitr C. Durig thi very hrt perid f traitial time, the primary curret will flw thrugh D4 t charge ad dicharge the ubber cacitr. Whe C i cmpletely dicharged (d=0), the the primary curret will flw thrugh D4/D ad the iductr eergy will flw back t the pwer urce. O the ecdary ide, r/d7 will ctiue t cduct durig thi perid f time ad trafer eergy t the lad. hi i becaue the ecdary ide curret Ia<0. he eergy maily cme frm the tred eergy f additial iductr L0 ad the leakage iductace. Output vltage will ctiue t icreae i thi tage. he crrepdig equivalet circuit ca be btaied a befre, baed the aalyi fr thi tage.. SABILIY ANALYSIS WIH EIGENALUE MEHOD Baed the equivalet circuit i each tage, the crrepdig tate equati ca be built fr thi bidirectial DC-DC cverter i each tage. he equivalet circuit are gt by the aalyi f the cmbiati act f the iput igal, utput igal ad ctrl igal f thi cled-lp cverter. Accrdig t mdel idetificati [3], [], the equivalet circuit i each tage are cled-lp mdel fr thi liear DC- DC cverter. he crrepdig tate equati will be a cled-lp tate pace mdel f thi bidirectial cverter i each liear tage. It ca be ued t determie the tability f thi bidirectial cverter i every liear tage directly. A. Stability Aalyi i Stage t 0 ~t Frm the equivalet circuit f the cverter, a hw i Fig.3, the tate equati f the cverter ca be geerated fr thi tage. Fr cveiece, let: L eq eq L0 L p L0 L di R eq R R i p eq c D7 d C c i R R c d C4 i R4 dc c C i R C d i R Subtitute the crrepdig value it thee tate equati. he cmplete tat equati are btaied, a give belw. di 95.i 709 c c d c d d D c () c 9 0 i 0 c () 9 i 0 0 c.8 0 i d i 50 herefre, the cled-lp tate pace mdel f thi cverter durig thi tage may be expreed a: x Ax Bu y Cx c (3) 5

6 Where [ i c c ], u [ D7 x ], y he eigevalue f the ytem matrix A fr the preet cverter i thi tage are give belw: i i herefre, the cverter i tate aympttically table i thi tage. It tability i irrelevat t the iput igal S ad the frward dide vltage D7 becaue they ly ifluece the iput ditributi matrix ad d t ifluece the ytem matrix. B. Stability Aalyi i Stage t ~t Frm the previu aalyi f the wrkig prce f the cverter, it i ee that there are three ub-tage ad crrepdig three equivalet circuit i thi tage. he tability f the cverter ca be aalyzed i thee three ub-tage with their equivalet circuit, e by e. () Sub-tage f Charge-dicharge f C7 ad C8 Accrdig t the equivalet circuit f the cverter hw i Fig.4, the crrepdig tate equati are give belw: di Leq Reqi c c dc c C i R d C4 i R4 dc c C i R d ( C8 C) i c7 ( C7 C8 CC8 CC7) C8( c7 c8 ) R( C7 C8 CC8 CC7) d Ci c8 C7C8 CC8 CC7 C7 c7 c8 R C7C8 CC8 CC7 c7 c8 c7 Subtitute the crrepdig cmpet value it thee tate equati, the fial tate equati fr the cverter i thi ub-tage ca be btaied, a give belw: (4) (5) K. Wu et. al: heretical Stability Aalyi f Ilated d d d c c7 c8 d c d i 9 i 0 0 c i c i 5 c 7 5 c i 5 c 7 5 c 8 c7 c8 herefre, the cled-lp tate pace mdel f thi cverter durig thi tage ca be expreed a: where x Ax Bu y Cx x i, u, y c c c7 c8 D7 5 0 he eigevalue f the ytem matrix i thi ub-tage are: i i All eigevalue have egative real part. Hece, the cverter i thi ub-tage i tate aympttically table. here i abrupt chage i tate frm tage t tage. he cverter de t receive ifiite ie. () Sub-tage f Free Wheelig i Stage Accrdig t the equivalet circuit f the cverter i the freewheelig tage, a hw i Fig.5, the crrepdig tate equati fr the cverter durig the preet ub-tage ca be btaied a fllw: di L R i d C i eq eq c c D8 S d C4 C c R C4 R4 d C i R d C C c i R () (7) (8) (9) d i 95.i c7 c Subtitute the crrepdig cmpet value it thee tate equati. he, the cmplete tate equati fr the preet cverter i thi ub-tage ca be gtte a fllw:

7 Aia Pwer Electric Jural, l. 7, N., Sep 03 di 95.i c c D8 S dc 9 0 i 0 c dc i 0 c 4 dc.80 i dc 50 0 c (0) herefre, the cled-lp tate pace mdel f the preet cverter durig the cidered ub-tage may be expreed a: Fig.3 i gt by imulatig the bidirectial cverter with triple phae-hift ctrl whe the iput vltage chage frm 48 t 55. here are tage i e perid at preet. By cmparig Fig.3 with Fig., it i ee that tw tage dipear ad the time durati f the ther tage becme differet whe the iput vltage chage. But the utput vltage will remai very cle t 00 with a mall errr, by adjutig the feedback reitace value t 00kΩ/.8kΩ, ad the bidirectial cverter i BIBO table. hi reult validate the eigevalue methd a prped i thi per, fr etablihig the tability f a bidirectial cverter with triple phae-hift ctrl whe ly the iput vltage chage. If the cverter i utable, hwever, a differet tplgy huld be cidered [], [5], [8]. Fig. ad Fig.3 are btaied thrugh imulati with PSIM. x Ax Bu y Cx () where x i, u, y c c D8 S 0 he eigevalue f the ytem matrix i thi ub-tage are give by: () All eigevalue have egative real part. Hece, the cverter i thi ub-tage i tate aympttically table. here i abrupt chage i the tate variable betwee thee tw ub-tage. Al, there i ifiite ie t the cverter. he tability f the cverter i the ther tage ca be aalyzed imilarly. It ca be etablihed that the bidirectial cverter i aympttically table i every tage. here are tate abrupt chage betwee tage r ub-tage. hi mea there i ifiite ie it the cverter. herefre, thi cverter i table durig the etire wrkig perid. I. SIMULAION SUDIES AND DISCUSSION Secti preeted a effective methd t etablih the tability f a bidirectial cverter uder triple phaehift ctrl, whe the iput vltage chage. he chage f the three phae hift due t a chage i the iput vltage will ly chage the time durati f me wrkig tage. Hece, the geeral equivalet circuit ad the tate equati i every tage will remai the ame. If the cverter i table i thee tage, it will remai table whe the time durati f the tage chage. hi ca be validated by cmputer imulati. Fig. 3: Simulati reult f frward bidirectial cverter with triple phae-hift ctrl whe iput vltage chage. here i a limit t the plicati f the preet methd f tability aalyi. If the ytem parameter chage, the preet methd i t valid. he, the cverter i prximately liear ad time variat i every tage, ad the matrix A i a fucti f time. he eigevalue methd cat be plied. II. CONCLUSION hi per preeted a ew methd t theretically aalyze the tability f a liear bidirectial dual full bridge DC-DC cverter with triple phae-hift ctrl. Firt, the liear cverter wa eparated it everal liear tage i e perid, ad equivalet circuit ad the crrepdig tate equati were determied fr each tage. It wa prved that the cverter wa table i every tage ad there were abrupt chage f tate betwee tw eighbrig tage r ub-tage. hi etablihed that the cverter wuld remai table durig the traiti frm e tage t the ext. he, it wa hw that that the cverter wuld be table i the etire perid. he 7

8 reult were validated thrugh cmputer imulati. REFERENCES [] A. Xu ad S. Xie, A Multipule-Structure-Baed Bidirectial PWM Cverter fr High-Pwer Applicati, IEEE ra. Pwer Electr., vl.4,.5, pp. 33-4, May 009. [] H.J. Chiu ad L.W. Li, A bidirectial DC-DC cverter fr fuel cell electric vehicle drivig ytem, IEEE ra. Pwer Electr., vl.,. 4, pp , July 00. [3] S. Iue ad H. Akagi, A Bidirectial DC-DC Cverter fr a Eergy Strage Sytem with Galvaic Ilati, IEEE ra. Pwer Electr., vl.,., Nvember 007. [4] H. Bai ad C. Mi, Elimiate Reactive Pwer ad Icreae Sytem Efficiecy f Ilated Bidirectial Dual Active Bridge DC-DC Cverter Uig Nvel Dual Phae Shift Ctrl, IEEE ra. Pwer Electr., vl.3,., Nvember 008. [5] G.G. Oggier, G.O. Garcia ad A.R. Oliva, Switchig Ctrl Strategy t Miimize Dual Active Bridge Cverter Le, IEEE ra. Pwer Electr., vl.4,.7, pp , July 009. [] G. C. Gdwi, S. F. Graebe, ad M. E. Salgad, Ctrl Sytem Deig, Pretice Hall f Idia, 00. [7] P. J. Atakli ad A. N. Michel, A Liear Sytem Primer, Birkhäuer, Bt, MA, 007. [8] C.W. de Silva, Mdelig ad Ctrl f Egieerig Sytem, Bca Rat, FL: CRC Pre/aylr & Fraci, 009. [9] D.H. Xu, C.H. Zha ad H. F. Fa, A PWM plu phaehift ctrl bidirectial DC-DC cverter, IEEE ra. Pwer Electr., vl. 9,. 3, pp. -75, May 004. [0] L. Zhu, A vel ft-cmmutatig ilated bt full bridge ZS-PWM dc-dc cverter fr bidirectial high pwer plicati, IEEE ra. Pwer Electr., vl.,., pp. 4-49, March, 00. [] Y.. Hte, D.R. Chudhury, ad J.R.P. Gupta, Rbut Stability Aalyi f the PWM Puh-Pull DC-DC Cverter, IEEE ra. Pwer Electr., vl.4,.0, pp , Oct [] K. Wu ad W. G. Dufrd, A Uuual Full Bridge Cverter t Realize ZS i Large Lad Scpe, Aia Pwer Electric Jural, vl.,., pp. -7, Apr [3]. aldivia, A. Barrad, A. Laazar, P. Zumel, C. Raga ad C. Feradez, Simple Mdelig ad Idetificati Prcedure fr Black-Bx Behaviral Mdelig f Pwer Cverter Baed raiet Repe Aalyi, IEEE ra. Pwer Electr., vl.4,., pp , Dec [4] F. Krimer ad J.W. Klar, Accurate Small-Sigal Mdel fr the Digital Ctrl f a Autmtive Bidirectial Dual Active Bridge, IEEE ra. Pwer Electr., vl.4,., pp , Dec [5] L. Huber, B.. Irvig ad M.M. Jvaic, Review ad Stability Aalyi f PLL-Baed Iterleavig Ctrl f DCM/CCM Budary Bt PFC Cverter, IEEE ra. Pwer Electr., vl.4,.8, pp , Aug [] S. Karagl ad M. Bikdah, Geerati f Equivalet- Circuit Mdel Frm Simulati Data f a hermal Sytem, IEEE ra. Pwer Electr., vl.5,.4, pp , April 00. [7] W. Che, X. Rua, H. Ya, ad C.K. e, DC/DC Cveri Sytem Citig f Multiple Cverter Mdule: Stability, Ctrl, ad Experimetal erificati, IEEE ra. Pwer Electr., vl.4,., pp , Jue 009. [8] J. Mrri, R. Zae, ad D. Makimvic, A Olie Stability Margi Mitr fr Digitally Ctrlled Switched- K. Wu et. al: heretical Stability Aalyi f Ilated Mde Pwer Supplie, IEEE raacti Pwer Electric, vl.4,., pp , Nv BIOGRAPHIES Kuiyua Wu received the B.S. degree frm Suthwet Jia g Uiverity, Chia (990); M.S. degree frm Chiee Academy f Sciece, Beijig, Chia (997); ad Uiverity f Britih Clumbia, Caada (008); ad PhD degree frm Uiverity f Britih Clumbia, acuver, Caada (0), all i electrical egieerig. Frm 009 t 00, he wa with Alpha echlgie Ltd. Hi curret reearch iteret iclude the cmbiati f pwer electric with advaced ctrl thery, vel ctrl methd ad vel pwer cverter develpmet, epecially ilated bidirectial DC-DC cverter, active pwer factr crrectr, high pwer ZS pwer upplie ad high frequecy iverter type reitace weldig machie. Clarece W. de Silva i a Fellw f: ASME, IEEE, Caadia Academy f Egieerig, ad Ryal Sciety f Caada, ad a ditiguihed iitig Fellw f the Ryal Academy f Egieerig. He received Ph.D. degree frm Maachuett Ititute f echlgy (978); ad Uiverity f Cambridge, U.K. (998); ad hrary D.Eg. degree frm Uiverity f Waterl, Caada (008). A Prfer f Mechaical Egieerig ad NSERC-BC Packer Chair hlder i Idutrial Autmati, at the Uiverity f Britih Clumbia, acuver, Caada ice 988, he curretly ccupie the ier Caada Reearch Chair i Mechatric & Idutrial Autmati. He ha authred 0 bk ad ver 400 per, prximately half f which are i jural. Hi recet bk publihed by aylr & Fraci/CRC are: Mechatric A Fudati Cure (00); Mdelig ad Ctrl f Egieerig Sytem (009); Ser ad Actuatr Ctrl Sytem Itrumetati (007); IBRAION Fudametal ad Practice, d Ed. (007); Mechatric A Itegrated Apprach (005); ad by Addi Weley: Sft Cmputig ad Itelliget Sytem Deig hery, l, ad Applicati (with F. Karray, 004). William G. Dufrd received the B.S. ad M.S. degree frm Imperial Cllege, Ld, U.K. ad the Ph.D. degree frm the Uiverity f rt, rt, ON, Caada, all i electrical egieerig. He ha al bee a faculty member f bth itituti ad i curretly a faculty ad Seate member f the Uiverity f Britih Clumbia, acuver, BC, Caada. Hi idutrial experiece iclude piti at the Ryal Aircraft Etablihmet (w Qietiq), Schlumberger ad Alcatel. He ha had a lg term iteret i phtvltaic pwered ytem ad i al ivlved i prject i the autmtive ad ditributed ytem area. Dr. Dufrd ha erved i variu piti the Adviry Cmmittee f the IEEE Pwer Electric Sciety ad chaired PESC i 98 ad 00. 8