An Industrial Perspective on Challenges in Nanoelectronics

Transcription

1 An Industrial Perspective on Challenges in Nanoelectronics Ralph K. Cavin, III Semiconductor Research Corporation November 19, 2002 U. CAL - Santa Barbara 1

2 Outline Technology Roadmap on Semiconductors Fundamentals of information processing, Fundamental limits to scaling Message: We suggest that the benefits from nanoelectronics research may, in the -- Short term lie more with the invention of new structures, materials and processes that extend the CMOS technology platform Long term enable invention of entirely new information processing technologies 2

3 A Bit about SRC Formed in 1982 by the SIA Conducts university research on behalf of its members Over 3000 graduates since inception currently support ~ 800 graduate students Many impressive contributions to the industry technology base across a wide spectrum of areas. Significant emphasis on technology/knowledge transfer Web site emphasizes content and is quite deep Very competitive research selection process ~ 10% of offerings are funded Over 200 industry technical advisors participate in the planning selection and evaluation of research 3

4 More about the SRC SRC products are research results, graduates, university infrastructure, and industry networking SRC revenues are tied to the market performance of members A highly qualified and experienced technical management team, about half of whom are on assignment from member companies Members have royalty-free internal use of IP resulting from SRC research Licenses are negotiated as needed for background IP required to practice foreground 4

5 International Technology Roadmap on Semiconductors A very detailed industrial perspective on the future requirements for micro/nano electronic technologies Goal is to continue exponential gains in performance/price for the next fifteen years Built on worldwide consensus of leading industrial, government, and academic technologists Provides guidance for the semiconductor industry and for academic research worldwide Content: critical requirements and judgment of status Projects that by 2016, half-pitch spacing of metal lines will be 22 nanometers and device gate lengths will be 9 nanometers 5

6 Carver Mead s revelation (1968) Gordon Moore (then at Fairchild) asked me how small we could make transistors in an integrated circuit In 1968, I was invited to give a talk at a workshop on semiconductor devices I had been thinking about Gordon Moore s question, and decided to make it the subject of my talk. As I prepared for this event, I began to have serious doubts about my sanity. My calculations were telling me that, contrary to all the current lore in the field, we could scale down the technology such that everything got better: The circuits got more complex, they ran faster, and they took less power WOW! That s a violation of Murphy s law that won t quit! But the more I looked at the problem, the more I was convinced that the result was correct, so I went ahead and gave the talk, to hell with the Murphy! That talk provoked considerable debate, and at the time most people didn t believe the results. 6

7 Chapters of ITRS ORTC Glossary 12 ITWGs : Design to Modeling & Simulation -Scope - Difficult Challenges - Technology Requirement - Potential Solutions System Drivers Difficult Challenges Grand Challenges Introduction 7

8 Interconnect Design Factory Integration ESH Yield Enhancement Metrology Modeling Lithography PIDS FEP Isolation Channel Source / Drain - Extension Wells Starting Material Contacts Assembly Test QFP BGA PGA Printed Wiring Board 8

9 MOS Transistor Scaling (1974 to present) S=0.7 [0.5x per 2 nodes] Pitch Gate 9

10 2002 ITRS Update=2001 ITRS Technology Node - DRAM Half-Pitch (nm) year Node Cycle 3-year Node Cycle Year of Production 2002 DRAM ½ Pitch 2002 MPU/ASIC ½ Pitch 1999 ITRS DRAM Half-Pitch Welcome to the age of Nanotechnology Source: 2002 ITRS - Exec. Summary, ORTC 10

11 2002 ITRS Update=2001 ITRS Technology Node - DRAM Half-Pitch (nm) MPU Printed Gate Length 2002 MPU Physical Gate Length Year of Production 1999 ITRS MPU Gate-Length 2-year Cycle 3-year Cycle Source: 2002 ITRS - Exec. Summary, ORTC 11

12 Tables Color Scheme Solutions Exist White Solutions Being Pursued Yellow No Known Solutions Red A new category has been introduced starting with 2002ITRS Update 12

13 ITRS Technology Requirements Table Legend Manufacturable Solutions Exist, and Are Being Optimized Manufacturable Solutions are Known Manufacturable Solutions are NOT Known Interim Solutions are Known 13

14 CMOS Scaling Challenges Table 2a High Performance Logic Technology Requirements 2001 ITRS CALENDAR YEAR TECHNOLOGY NODE (NM MPU GATE LENGTH Gate Dielectric Equivalent Oxide Thickness (EOT) (nm) [1] Electrical Thickness Adjustment Factor (Gate Depletion and Quantum Effects) (nm) [2] Tox Electrical Equivalent (nm) [3] Vdd (V) [4]

15 Moore s Law I: Transistors per chip Motivation: density speed functionality 15

16 Moore s Law: Minimum Feature Size Minimum Feature Size (nm)

17 Devices will soon be on the molecular or atomistic scale Atoms per Bit 1.00E E E E E E E E E E Years from 2000 IC and Bio-based device IC density and bio-based converge device densities converge Molecular Molecular Devices devices

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19 Evolution of Electronics Controllable resistor Switch Analog: TV, radio, communications... Digital: Computation DIGITAL INFORMATION PROCESSING General Purpose Computer (GPC) accepts arbitrary types of data and sets of instructions to perform arbitrary tasks of transmission, processing, and storing the information Parameters of GPC: Number of components (integration density/functional complexity) Speed Energy consumption 19

20 What is Information? Information is Measure of distinguishability A function of an apriori probability of a given state or outcome among the universe of possible states Constituents of the Information Theory Sender and recipient Symbols (microstates) as elementary units of information Information carriers Information is physical! 20

21 The Abacus, an ancient digital calculating device Information is represented in digital form Each column denotes a decimal digit Binary representation: two possible positions for each bead A bead in the abacus is a memory device, not a logic gate 21

22 Source: IBM

23 Particle Location is an Indicator of State

24 Two-well bit a E b E b a w w 24

25 Example: Field Effect Transistor Long Channel Short Channel 25

26 A physical system as a computing medium We need to create a bit first. Information processing always requires physical carrier, which are material particles. First requirement to physical realization of a bit implies creating distinguishable states within a system of such material particles. The second requirement is conditional change of state. The properties of distinguishability and conditional change of state are two fundamental properties of a material subsystem to represent information. These properties can be obtained by creating energy barriers in a material system. 26

27 Ideal von Neumann s Computer Designers and Users want: Highest possible integration density (n) To keep chips size small and increase yields To increase functionality Highest possible speed (f=1/t) Speed sells! Lowest possible power consumption (P) Decrease demands for energy The generation of too much heat means costly cooling systems 27

28 Power density will increase Power Density (W/cm2) Rocket Nozzle Nuclear Reactor Hot Plate P6 Pentium proc Year Power density too high to keep junctions at low temp 14 28

29 Energetics of Computation P = E t bit sw n Requirements to an ideal computer: (integration density) n=max (switching time) (power) t sw =min P=min 29

30 Lowest Barrier: Distinguishability Barrier Distinguishability D implies low probability Π of spontaneous transitions between two wells (error probability) D=max, Π=0 D=0, Π=0.5 (50%) E b a a E b Classic distinguishability: Π classic Minimum distinguishable barrier: П= = exp( Eb k T B ) = exp( k E B E b =ktln2 b T Shannon - von Neumann - Landauer limit ) 30

31 Smallest Size: The Heisenberg Barrier h x p h a crit = 2mE b E t h h t min = E b 31

32 Classic and Quantum Π=0.5 Π classic = exp( Eb k T B ) a E b E min b = k B T ln 2 E b a WKB: (Tunneling) Π E quantum min b = = exp( 2 h ln 8ma m h a E b ) E b a a E b 32

33 Total Π=0.5 Π error = Π classic + Π quantum Π classic Π quantum = = exp( Eb kt ) + exp( 2 2m h a E b ) exp( he b + 2akT hkt 2mE b ) Generalized expression for the minimum energy barrier to create a bit E min b kt ln 2 + h 2 (ln 2) 8ma 2 2 E b /kt a, nm ktln2 33

34 Least Energy Computer 1) Minimum distance between two distinguishable states (Heisenberg) h x min = a = = 1.5nm(300K) 2mkT ln 2 2) Minimum state switching time (Heisenberg) t st = h 2kT ln 2 = s(300k) 3) Maximum gate density 1 n = = x 2 min 13 gate 2 cm 34

35 Total Power Consumption at Minimal Energy per bit P E kt ln 2 2 P = np b 2 bit = = = ( kt ln 2) chip bit tsc tsc h P chip 6 W = T=300 K cm 2 The circuit would vaporize when it is turned on! 35

36 How much heat a solid system can tolerate? ITRS 2001 projects 93 W/cm 2 for MPU in 2016 We believe that several hundred W/cm 2 is close to physical limits of heat removal from a 2-dimensional solid material structure with T max =125 C 36

37 Inflexion of ITRS vectors? Heisenberg barrier 1.00E K Memory l t, s 1.00E E E E E P=100 W/cm 2 3 Logic l is the cell size : I=n -1/2 l min =a 2 Heisenberg barrier l, nm l MPU =(11-15)a 37

38 Ultimate and Optimum parameters Switch size Switching time Integration density Frequency 1.5 nm 1 ns 5x10 13 cm -2 1 GHz 54 nm 1 ps 3.4x10 10 cm -2 1 THz Optimum parameters: ITRS vector for logic intercepting the energy barrier 35 nm 2 ps 8x10 10 cm GHz Optimum parameters: ITRS vector for memory intercepting the energy barrier 6 nm 0.1 ns 2.7x10 12 cm GHz 38

39 Implications for Nanoelectronics Scaling to molecular dimensions may not yield performance increases We will be forced to trade-off between speed and density Optimal dimensions (depending on speed/density tradeoffs) for electronic switches should range between 5 and 50 nm, and this may be achievable with silicon technology Within the scope of ITRS projections 39

40 Fundamentals of Heat Removal A quote from anonymous scientists working at the frontiers of nanoelectronics: Heat removal is not an issue. Simply, engineers must invent better technologies for heat removal and cooling. Three fundamentals of heat removal: 1)The Newton's Law of Cooling: q=h(t h -T a ) (h-heat transfer coefficient) 2) The Ambient: T a =300 K!!! 3) The Carnot s theorem: W Work to be done cool Ta Tc = Q T c Heat to be removed 40

41 Carnot s Refrigerator and Cryogenic Computation W cool T T = a c Q T Min. total power needed to run a 100 W chip: at 77 K W at 4.2 K - 7 kw c 41

42 Energetics of Computation II % 20% 40% 60% 80% 100% 0% 20% 40% 60% 80% 100% Servers In 1999, computers and the Internet consumed approximately 8% of the world s electric power. Current forecasts suggest that these sectors will consume up to 50% of the world s electric power by (May be overstated but a concern none-the-less!) PCs Routers Others (H. Sasaki, Chairman of the Board, NEC Corp.), Future Platform for Mobile Communication, ISQED March 27, 2001 ) 42

43 A question What to do? Gate Source Drain Substrate Silicon MOSFET? Bell Labs Molecular FET IBM CNTFET 43

44 Emerging Research Devices Evaluation Criteria Performance - will the technology extend the performance of microelectronics by 100X beyond the 32 nm node? Scalability how many generations will a chosen technology survive? Universality - does a chosen technology have the potential to build a new platform? Manufacturability - will the technology sustain the cost per function curve reducing the cost/function per year? Impact on Infrastructure - will a chosen technology require drastic changes in existing infrastructure? Compatibility with CMOS (design & manufacturing) 44

45 What to do? (Cont d)? Bell Labs Molecular FET Quantum Computer IBM CNFET Conventional von Neumann Architecture Cellular Non Linear Network New Information Processing Architectures 45

46 Neuromorphic Computing Implies computational schemes and systems resembling operation of human brains. The potential capabilities of neuromorphic computers could be close to those of the brain, thus enabling e.g. artificial intelligence Properties of brain: Mass 1.5 kg Volume 1.5 l Energy consumption ~10 W Information stored 1e14 bits 1e13 bits/s 46

47 A Question: What to do? What is the best direction to pursue for alternate information processing technologies (e.g., carbon nanotubes, molecular electronics, etc.)? Replicate CMOS technology with new switches, gates, etc., directly one for one sustaining the von Neumann architecture? Or Eventually invent and develop a completely new information processing technology and systems architecture? We think that a two-faceted approach makes sense Develop new nano-engineered materials and processes for the CMOS technology platform to push CMOS scaling as far as possible Begin explorations for new device paradigms based on principles other than particle position/transfer 47

48 Thesis Basic Research in Solid State Materials in the 1930 s and 1940 s created the foundation for the Electronic Century We have successfully utilized this research investment to create much of modern information technology We need to replenish the knowledge base because the end of evolution in solid state electronics is foreseeable We are significantly under-investing in the physical sciences that support the semiconductor industry 48

49 Government funded research in solid state physics in 1930 s and 40 s laid the foundation Central Breakthroughs: Band structure concept Minute amounts of impurities control properties Advances in purification and high quality crystal growth of Si and Ge Beginning about 1946, we began to utilize this knowledge base Most basic semiconductor devices were demonstrated within 12 years Bipolar transistor 1948 Field effect transistor 1953 LED 1955 Tunnel diode 1957 IC 1959 Laser

50 For about four decades now we have exploited (mined) our investment in materials and we have continuously evolved the devices based on this understanding 50

51 To get from today to the end of CMOS, we must overcome many problems in science where new understanding is needed Semiconductor industry is pumping down last resources Possible to discover new well? We need to be about the process of creating a new science basis for the devices beyond evolution 51

52 Old and New resources: What are the parallels in basic physical concepts needed? 1952 Achievements Bulk band structure of solids 2002 Needs geometry dependent energetic structure of nanostructures Doping precise location of atoms Crystal growth self organization of matter in complex structures 52

53 What should our research address? Examples s r R Spin Measurements, e.g. quantum Hall effect Geometry related quantum effects, e.g. quantum wedge Source Drain Si P + P + Precise location of atoms B - 53

54 Example Research Questions for Functional Materials Intelligent machines, e.g. molecular networks Complex nanostructures: Synthesis and properties, e.g. quantum wedge, spin devices Quantum mechanics and Quantum electrostatics, e.g. Quantum Entanglement Correlated tunnel transitions Mechanical properties of materials at nanoscale Neuromorphic Information Processing Quantum Information Technologies NEMS 54

55 Conclusions The first impacts from nano-engineered materials are likely to be in the area of improving the performance of CMOS devices and interconnects Fundamental considerations suggest that the potential benefits from replacing CMOS devices with new types of electron transport devices may be limited The exploration of alternative approaches to von Neumann type computing, such as brain or Reversible/Quantum Computation, is becoming a strategic imperative. We need a concerted effort in this area because of the long lead times for the introduction of radically new technologies 55

56 Back-Up Slides 56

57 NanoFloating gate memory SiO 2 Gate memory node Before filling n + n + Si After filling 57

58 Si nanocrystals memory Formation of Si nanocrystals in SiO 2 through spontaneous decomposition during CVD deposition of SiO 2 Size of Si nanocrystals ~5 nm 58

59 Nanocrystals Memory Low write voltage Field enhancement at nanodots Improved endurance Write current density is uniformly distributed along the nanodots Write current per nanodot is self-limited by Coulomb blockade 59

60 Nanocrystals Memory Read time: <80 ns Write time: 100 ns Retention: >1 week Erase/Write cycles: