Understand Video Games; Understand Everything
|
|
|
- Charles Alexander
- 5 years ago
- Views:
Transcription
1 Understand Video Games; Understand Everything Stephen A. Edwards Columbia University
2 The Subject of this Lecture 0
3 The Subjects of this Lecture 0 1
4 But let your communication be, Yea, yea; Nay, nay: for whatsoever is more than these cometh of evil. Matthew 5:37
5 Engineering Works Because of Abstraction Application Software Operating Systems Architecture Micro-Architecture Logic Digital Circuits COMS 3157, 4156, et al. COMS W4118 COMS W3827 COMS W3827 COMS W3827 COMS W3827 Analog Circuits ELEN 3331 Devices ELEN 3106 Physics ELEN 3106 et al.
6 thinkgeek.com
7 Boolean Logic George Boole
8 Boole s Intuition Behind Boolean Logic Variables X, Y,... represent classes of things No imprecision: A thing either is or is not in a class If X is sheep and Y is white things, XY are all white sheep, and XY = YX XX = X. If X is men and Y is women, X + Y is both men and women, and X + Y = Y + X X + X = X. If X is men, Y is women, and Z is European, Z(X + Y) is European men and women and Z(X+Y) = ZX+ZY.
9 Simplifying a Boolean Expression You are a New Yorker if you were born in New York or were not born in New York and lived here ten years. Axioms X = born in New York Y = lived here ten years X + (X Y) X + Y = Y + X X Y = Y X X + (Y + Z) = (X + Y) + Z X (Y Z) = (X Y) Z X + (X Y) = X X (X + Y) = X X (Y + Z) = (X Y) + (X Z) X + (Y Z) = (X + Y) (X + Z) X + X = 1 X X = 0 Lemma: X 1 = X (X + X) = X (X + Y) if Y = X = X
10 Simplifying a Boolean Expression You are a New Yorker if you were born in New York or were not born in New York and lived here ten years. Axioms X = born in New York Y = lived here ten years X + (X Y) = (X + X) (X + Y) X + Y = Y + X X Y = Y X X + (Y + Z) = (X + Y) + Z X (Y Z) = (X Y) Z X + (X Y) = X X (X + Y) = X X (Y + Z) = (X Y) + (X Z) X + (Y Z) = (X + Y) (X + Z) X + X = 1 X X = 0 Lemma: X 1 = X (X + X) = X (X + Y) if Y = X = X
11 Simplifying a Boolean Expression You are a New Yorker if you were born in New York or were not born in New York and lived here ten years. Axioms X = born in New York Y = lived here ten years X + (X Y) = (X + X) (X + Y) = 1 (X + Y) Lemma: X + Y = Y + X X Y = Y X X + (Y + Z) = (X + Y) + Z X (Y Z) = (X Y) Z X + (X Y) = X X (X + Y) = X X (Y + Z) = (X Y) + (X Z) X + (Y Z) = (X + Y) (X + Z) X + X = 1 X X = 0 X 1 = X (X + X) = X (X + Y) if Y = X = X
12 Simplifying a Boolean Expression You are a New Yorker if you were born in New York or were not born in New York and lived here ten years. Axioms X = born in New York Y = lived here ten years X + (X Y) = (X + X) (X + Y) = 1 (X + Y) = X + Y Lemma: X + Y = Y + X X Y = Y X X + (Y + Z) = (X + Y) + Z X (Y Z) = (X Y) Z X + (X Y) = X X (X + Y) = X X (Y + Z) = (X Y) + (X Z) X + (Y Z) = (X + Y) (X + Z) X + X = 1 X X = 0 X 1 = X (X + X) = X (X + Y) if Y = X = X
13 Alternate Notations for Boolean Logic Operator Math Engineer Schematic Copy x X X or X X Complement x X X X AND x y XY or X Y X Y XY OR x y X + Y X Y X + Y
14 Expressions to Schematics F = X Y + X Y X Y
15 Expressions to Schematics F = X Y + X Y X X Y Y
16 Expressions to Schematics F = X Y + X Y X X X Y Y Y
17 Expressions to Schematics F = X Y + X Y X X X Y Y Y X Y
18 Expressions to Schematics F = X Y + X Y X X X Y X Y + X Y = F Y Y X Y
19 Expressions to Schematics F = X Y + X Y = (X + Y)(X + Y) X X X Y X Y + X Y = F Y Y X Y (X + Y)(X + Y) = F
20 The Decimal Positional Numbering System Ten figures: = = Why base ten?
21 Binary DEC PDP-8/I, c Dec Bin PC = =
22 Binary Addition Algorithm =
23 Binary Addition Algorithm = =
24 Binary Addition Algorithm = = =
25 Binary Addition Algorithm = = = =
26 Binary Addition Algorithm = = = = =
27 Binary Addition Algorithm = = = = =
28 Arithmetic Circuits
29 Arithmetic: Addition Adding two one-bit numbers: A and B Produces a two-bit result: C S (carry and sum) A B Half Adder C S A B C S
30 Full Adder In general, you need to add three bits: C o = = = = = = 10 C i A B C o S C i A B C i A B C o S S
31 A Four-Bit Ripple-Carry Adder A B A 3 B 3 A 2 B 2 A 1 B 1 A 0 B 0 C o FA C i FA FA FA FA 0 S S 4 S 3 S 2 S 1 S 0
32 PONG PONG, Atari 1973 Built from TTL logic gates; no computer, no software Launched the video arcade game revolution
33 Horizontal Ball Control in PONG M L R A B X X X X X X X X The ball moves either left or right. Part of the control circuit has three inputs: M ( move ), L ( left ), and R ( right ). It produces two outputs A and B. Here, X means I don t care what the output is; I never expect this input combination to occur.
34 Horizontal Ball Control in PONG M L R A B Assume all the X s are 0 s: A = MLR + MLR B = M LR + M LR + MLR 3 inv + 4 AND3 + 1 OR2 + 1 OR3
35 Horizontal Ball Control in PONG M L R A B Choosing better values for the X s: A = ML + MR B = MR 3 NAND2
36 Horizontal Ball Control in PONG M L R A B Being even more clever: A = M B = MR 1 NAND2
37 The Actual Pong Circuit Pong, Atari, 1972 Winner, Midway, 1973
38 Karnaugh Maps Basic trick: put similar variable values near each other so simple functions are obvious M L R A B X X X X X X X X The M s are already arranged nicely
39 Karnaugh Maps Basic trick: put similar variable values near each other so simple functions are obvious M L R A B X X Let s rearrange the L s by permuting two pairs of rows X X X X X X
40 Karnaugh Maps Basic trick: put similar variable values near each other so simple functions are obvious M L R A B X X X X X X Let s rearrange the L s by permuting two pairs of rows X X
41 Karnaugh Maps Basic trick: put similar variable values near each other so simple functions are obvious M L R A B X X X X Let s rearrange the L s by permuting two pairs of rows X X X X
42 Karnaugh Maps Basic trick: put similar variable values near each other so simple functions are obvious M L R A B X X X X Let s rearrange the L s by permuting two pairs of rows X X X X
43 Karnaugh Maps Basic trick: put similar variable values near each other so simple functions are obvious M L R A B X X X X X X Let s rearrange the L s by permuting two pairs of rows X X
44 Karnaugh Maps Basic trick: put similar variable values near each other so simple functions are obvious M L R A B X X X X X X X X Let s rearrange the L s by permuting two pairs of rows
45 Karnaugh Maps Basic trick: put similar variable values near each other so simple functions are obvious M L R A B X X X X X X X X Let s rearrange the L s by permuting two pairs of rows
46 Karnaugh Maps Basic trick: put similar variable values near each other so simple functions are obvious M L R A B X X X X X X X X Let s rearrange the L s by permuting two pairs of rows
47 Karnaugh Maps Basic trick: put similar variable values near each other so simple functions are obvious M L R A B X X X X X X X X The R s are really crazy; let s use the second dimension
48 Karnaugh Maps Basic trick: put similar variable values near each other so simple functions are obvious M L R A B X X X X X X X X The R s are really crazy; let s use the second dimension
49 Karnaugh Maps Basic trick: put similar variable values near each other so simple functions are obvious M L R A B X0 X X 1 X The R s are really crazy; let s use the second dimension X 1 X X1 X0
50 Karnaugh Maps Basic trick: put similar variable values near each other so simple functions are obvious M L R A B X0 X X 1 X MR X 1 X X1 X0 M
51 Maurice Karnaugh s Maps Transactions of the AIEE, 1953
52 The Seven-Segment Decoder Example a W X Y Z a b c d e f g X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X e f d g c b
53 Karnaugh Map for Seg. a W X Y Z a X X X X X X Z X X 0 X 1 1 X X Y W The Karnaugh Map Sum-of-Products Challenge Cover all the 1 s and none of the 0 s using as few literals (gate inputs) as possible. Few, large rectangles are good. Covering X s is optional.
54 Karnaugh Map for Seg. a W X Y Z a X X X X X X Z X X 0 X 1 1 X X Y W The minterm solution: cover each 1 with a single implicant. a = W X Y Z + W X Y Z + W X Y Z + W X Y Z + W X Y Z + W X Y Z + W X Y Z + W X Y Z 8 4 = 32 literals 4 inv + 8 AND4 + 1 OR8
55 Karnaugh Map for Seg. a W X Y Z a X X X X X X Z X X 0 X 1 1 X X Merging implicants helps Y W Recall the distributive law: AB + AC = A(B + C) a = W X Y Z + W Y + W X Z + W X Y = 12 literals 4 inv + 1 AND4 + 2 AND3 + 1 AND2 + 1 OR4
56 Karnaugh Map for Seg. a W X Y Z a X X X X X X Z X X 0 X 1 1 X X Y W Missed one: Remember this is actually a torus. a = X Y Z + W Y + W X Z + W X Y = 11 literals 4 inv + 3 AND3 + 1 AND2 + 1 OR4
57 Karnaugh Map for Seg. a W X Y Z a X X X X X X Z X X 0 X 1 1 X X Y W Taking don t-cares into account, we can enlarge two implicants: a = X Z + W Y + W X Z + W X = 9 literals 3 inv + 1 AND3 + 3 AND2 + 1 OR4
58 Karnaugh Map for Seg. a W X Y Z a X X X X X X Z X X 0 X 1 1 X X Y W Can also compute the complement of the function and invert the result. Covering the 0 s instead of the 1 s: a = W X Y Z + X Y Z + W Y = 9 literals 5 inv + 1 AND4 + 1 AND3 + 1 AND2 + 1 OR3
59 Karnaugh Map for Seg. a W X Y Z a X X X X X X Z X X 0 X 1 1 X X Y W To display the score, PONG used a chip with this: (13) (12) OUTPUT a OUTPUT b
60 Decoders
61 Decoders Input: n-bit binary number Output: 1-of-2 n one-hot code 2-to-4 in out to-8 decoder in out in 4-to-16 decoder out
62 The to-8 Decoder 15 Y0 A 1 14 Y1 Select Inputs B 2 13 Y2 C Y3 Y4 Data Outputs 10 Y5 G1 6 9 Y6 Enable Inputs G2A 4 7 Y7 G2B 5
63 A 138 Spotted in the Wild Pac-Man (Midway, 1980)
64 Multiplexers
65 The Two-Input Multiplexer B A 1 0 S Y S B A Y B A S S A B Y S B A Y 0 X X X X 1 S Y 0 A 1 B
66 Two-input Muxes in the Wild Quad 2-to-1 mux 3B selects color from a sprite or the background Pac-Man (Midway, 1980)
67 State-Holding Elements
68 Bistable Elements Q Q Q Q Equivalent circuits; right is more traditional. Two stable states:
69 A Bistable in the Wild This debounces the coin switch. Breakout, Atari 1976.
70 SR Latches in the Wild Generates horizontal and vertical synchronization waveforms from counter bits. Stunt Cycle, Atari 1976.
71 Atari Space Race, 1973
72 Atari Space Race PCB Front Back (mirrored)
73 Implementing ROMs 0 Wordline 0 Add. Data 1 Wordline A 1 A 0 2-to-4 Decoder 2 Wordline 2 3 Wordline 3 D 2 D 1 D 0
74 Implementing ROMs 1 0 Wordline 0 Add. Data A 1 0 A to-4 Decoder Wordline 1 Wordline 2 Wordline D 2 D 1 D 0
75 Atari Space Race Schematic
76 The 1971 DEC M792-YB Bootstrap Diode Matrix 32-word, 16-bit (64-byte) ROM diode matrix
77 Color PROM in Pac-Man EF F8 06 EA 07 6F F 0A 00 0B C9 0C 38 0D AA 0E AF 0F F F 00
78
79
80
81
82
83 TMS9918 Video Display Processor
84 TMS9918 Video Display Processor
85 Nintendo NES/Famicom
86 TMS9918 Pattern Generation
87 TMS9918 Sprite Generation
88 TMS9918 Sprite Attribute Table Entry
Fundamentals of Computer Systems
Fundamentals of Computer Systems Boolean Logic Stephen A. Edwards Columbia University Fall 2011 Boolean Logic George Boole 1815 1864 Boole s Intuition Behind Boolean Logic Variables x, y,... represent
Fundamentals of Computer Systems
Fundamentals of Computer Systems Boolean Logic Stephen A. Edwards Columbia University Summer 2015 Boolean Logic George Boole 1815 1864 Boole s Intuition Behind Boolean Logic Variables X,,... represent
Fundamentals of Computer Systems
Fundamentals of Computer Systems Boolean Logic Stephen A. Edwards Columbia University Summer 2017 Boolean Logic George Boole 1815 1864 Boole s Intuition Behind Boolean Logic Variables,,... represent classes
Fundamentals of Computer Systems
Fundamentals of Computer Systems Review for the Final Stephen A. Edwards Columbia University Summer 25 The Final 2 hours 8 problems Closed book Simple calculators are OK, but unnecessary One double-sided
Fundamentals of Computer Systems
Fundamentals of Computer Systems Review for the Midterm Stephen A. Edwards Columbia University Spring 22 The Midterm 75 minutes 4 5 problems Closed book Simple calculators are OK, but unnecessary One double-sided
211: Computer Architecture Summer 2016
211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Review: cache hit rate - Project3 - Digital Logic: - truth table => SOP - simplification: Boolean
We are here. Assembly Language. Processors Arithmetic Logic Units. Finite State Machines. Circuits Gates. Transistors
CSC258 Week 3 1 Logistics If you cannot login to MarkUs, email me your UTORID and name. Check lab marks on MarkUs, if it s recorded wrong, contact Larry within a week after the lab. Quiz 1 average: 86%
CHAPTER1: Digital Logic Circuits Combination Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits Combination Circuits 1 PRIMITIVE LOGIC GATES Each of our basic operations can be implemented in hardware using a primitive logic gate.
Fundamentals of Computer Systems
Fundamentals of omputer Systems ombinational Logic Stephen. Edwards olumbia University Fall 2012 Encoders and Decoders Decoders Input: n-bit binary number Output: 1-of-2 n one-hot code 2-to-4 in out 00
Digital Logic (2) Boolean Algebra
Digital Logic (2) Boolean Algebra Boolean algebra is the mathematics of digital systems. It was developed in 1850 s by George Boole. We will use Boolean algebra to minimize logic expressions. Karnaugh
Review for Test 1 : Ch1 5
Review for Test 1 : Ch1 5 October 5, 2006 Typeset by FoilTEX Positional Numbers 527.46 10 = (5 10 2 )+(2 10 1 )+(7 10 0 )+(4 10 1 )+(6 10 2 ) 527.46 8 = (5 8 2 ) + (2 8 1 ) + (7 8 0 ) + (4 8 1 ) + (6 8
Lecture 22 Chapters 3 Logic Circuits Part 1
Lecture 22 Chapters 3 Logic Circuits Part 1 LC-3 Data Path Revisited How are the components Seen here implemented? 5-2 Computing Layers Problems Algorithms Language Instruction Set Architecture Microarchitecture
Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing
IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of
Combinational Logic. By : Ali Mustafa
Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output
Digital Logic Design. Combinational Logic
Digital Logic Design Combinational Logic Minterms A product term is a term where literals are ANDed. Example: x y, xz, xyz, A minterm is a product term in which all variables appear exactly once, in normal
Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary
Number System Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary BOOLEAN ALGEBRA BOOLEAN LOGIC OPERATIONS Logical AND Logical OR Logical COMPLEMENTATION
Systems I: Computer Organization and Architecture
Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept
Part 1: Digital Logic and Gates. Analog vs. Digital waveforms. The digital advantage. In real life...
Part 1: Digital Logic and Gates Analog vs Digital waveforms An analog signal assumes a continuous range of values: v(t) ANALOG A digital signal assumes discrete (isolated, separate) values Usually there
Lecture 2 Review on Digital Logic (Part 1)
Lecture 2 Review on Digital Logic (Part 1) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ Grading Engagement 5% Review Quiz 10% Homework 10% Labs 40%
ECE 2300 Digital Logic & Computer Organization
ECE 23 Digital Logic & Computer Organization Spring 28 Combinational Building Blocks Lecture 5: Announcements Lab 2 prelab due tomorrow HW due Friday HW 2 to be posted on Thursday Lecture 4 to be replayed
Written exam for IE1204/5 Digital Design with solutions Thursday 29/
Written exam for IE4/5 Digital Design with solutions Thursday 9/ 5 9.-. General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 8-794487 Exam text does not have to be returned when
Logic Simplification. Boolean Simplification Example. Applying Boolean Identities F = A B C + A B C + A BC + ABC. Karnaugh Maps 2/10/2009 COMP370 1
Digital Logic COMP370 Introduction to Computer Architecture Logic Simplification It is frequently possible to simplify a logical expression. This makes it easier to understand and requires fewer gates
CSC9R6 Computer Design. Practical Digital Logic
CSC9R6 Computer Design Practical Digital Logic 1 References (for this part of CSC9R6) Hamacher et al: Computer Organization App A. In library Floyd: Digital Fundamentals Ch 1, 3-6, 8-10 web page: www.prenhall.com/floyd/
LOGIC GATES. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Eperiment and Design of Electronics LOGIC GATES Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Boolean algebra Logic gates Karnaugh maps
Fundamentals of Computer Systems
Fundamentals of Computer Systems Sequential Logic Stephen A. Edwards Columbia University Summer 2017 State-Holding Elements Bistable Elements S Latch Latch Positive-Edge-Triggered Flip-Flop Flip-Flop with
Written reexam with solutions for IE1204/5 Digital Design Monday 14/
Written reexam with solutions for IE204/5 Digital Design Monday 4/3 206 4.-8. General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned
Chapter 2: Switching Algebra and Logic Circuits
Chapter 2: Switching Algebra and Logic Circuits Formal Foundation of Digital Design In 1854 George Boole published An investigation into the Laws of Thoughts Algebraic system with two values 0 and 1 Used
EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive
EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive March 30, 2010 John Wawrzynek Spring 2010 EECS150 - Lec19-cl1 Page 1 Boolean Algebra I (Representations of Combinational
DIGITAL LOGIC CIRCUITS
DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memory Components Integrated Circuits Digital Computers 2 LOGIC GATES
Midterm Examination # 1 Wednesday, February 25, Duration of examination: 75 minutes
Page 1 of 10 School of Computer Science 60-265-01 Computer Architecture and Digital Design Winter 2009 Semester Midterm Examination # 1 Wednesday, February 25, 2009 Student Name: First Name Family Name
COMBINATIONAL LOGIC FUNCTIONS
COMBINATIONAL LOGIC FUNCTIONS Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends only on the present
Boolean Algebra, Gates and Circuits
Boolean Algebra, Gates and Circuits Kasper Brink November 21, 2017 (Images taken from Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc.) Outline Last week: Von
Prove that if not fat and not triangle necessarily means not green then green must be fat or triangle (or both).
hapter : oolean lgebra.) Definition of oolean lgebra The oolean algebra is named after George ool who developed this algebra (854) in order to analyze logical problems. n example to such problem is: Prove
( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function
Question Paper Digital Electronics (EE-204-F) MDU Examination May 2015 1. (a) represent (32)10 in (i) BCD 8421 code (ii) Excess-3 code (iii) ASCII code (b) Design half adder using only NAND gates. ( c)
Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.
Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational
Logic Design. Chapter 2: Introduction to Logic Circuits
Logic Design Chapter 2: Introduction to Logic Circuits Introduction Logic circuits perform operation on digital signal Digital signal: signal values are restricted to a few discrete values Binary logic
Written exam with solutions IE Digital Design Friday 21/
Written exam with solutions IE204-5 Digital Design Friday 2/0 206 09.00-3.00 General Information Examiner: Ingo Sander. Teacher: Kista, William Sandvist tel 08-7904487, Elena Dubrova phone 08-790 4 4 Exam
MODULAR CIRCUITS CHAPTER 7
CHAPTER 7 MODULAR CIRCUITS A modular circuit is a digital circuit that performs a specific function or has certain usage. The modular circuits to be introduced in this chapter are decoders, encoders, multiplexers,
Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3
Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 Basic Logic Gates XOR CMPE12 Summer 2009 02-2 Truth Table The most basic representation of a logic function Lists the output for all possible
Combinational Logic. Mantıksal Tasarım BBM231. section instructor: Ufuk Çelikcan
Combinational Logic Mantıksal Tasarım BBM23 section instructor: Ufuk Çelikcan Classification. Combinational no memory outputs depends on only the present inputs expressed by Boolean functions 2. Sequential
Vidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution
![Vidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution](/thumbs/90/103673562.jpg "Vidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution")
. (a) (i) ( B C 5) H (A 2 B D) H S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution ( B C 5) H (A 2 B D) H = (FFFF 698) H (ii) (2.3) 4 + (22.3) 4 2 2. 3 2. 3 2 3. 2 (2.3)
E&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev
E&CE 223 Digital Circuits & Systems Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev 4 of 92 Section 2: Boolean Algebra & Logic Gates Major topics Boolean algebra NAND & NOR gates Boolean
Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS
Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS 1) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction (a) X -Y and (b) Y - X using 2's complements. a) X = 1010100
Combinational Logic Design Combinational Functions and Circuits
Combinational Logic Design Combinational Functions and Circuits Overview Combinational Circuits Design Procedure Generic Example Example with don t cares: BCD-to-SevenSegment converter Binary Decoders
DHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN
DHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I : BOOLEAN ALGEBRA AND LOGIC GATES PART - A (2 MARKS) Number
Philadelphia University Faculty of Engineering
Philadelphia University Faculty of Engineering Marking Scheme Exam Paper BSc CE Logic Circuits (630211) Final Exam First semester ate: 03/02/2019 Section 1 Weighting 40% of the module total Lecturer: Coordinator:
Binary addition example worked out
Binary addition example worked out Some terms are given here Exercise: what are these numbers equivalent to in decimal? The initial carry in is implicitly 0 1 1 1 0 (Carries) 1 0 1 1 (Augend) + 1 1 1 0
Number System conversions
Number System conversions Number Systems The system used to count discrete units is called number system. There are four systems of arithmetic which are often used in digital electronics. Decimal Number
Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University
Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University Original Source: Aby K George, ECE Department, Wayne State University Contents The Map method Two variable
CHAPTER 12 Boolean Algebra
318 Chapter 12 Boolean Algebra CHAPTER 12 Boolean Algebra SECTION 12.1 Boolean Functions 2. a) Since x 1 = x, the only solution is x = 0. b) Since 0 + 0 = 0 and 1 + 1 = 1, the only solution is x = 0. c)
Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps
EE210: Switching Systems Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps Prof. YingLi Tian Feb. 21/26, 2019 Department of Electrical Engineering The City College of New York
Logic. Combinational. inputs. outputs. the result. system can
Digital Electronics Combinational Logic Functions Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends
Chapter 2: Boolean Algebra and Logic Gates
Chapter 2: Boolean Algebra and Logic Gates Mathematical methods that simplify binary logics or circuits rely primarily on Boolean algebra. Boolean algebra: a set of elements, a set of operators, and a
Lecture A: Logic Design and Gates
Lecture A: Logic Design and Gates Syllabus My office hours 9.15-10.35am T,Th or gchoi@ece.tamu.edu 333G WERC Text: Brown and Vranesic Fundamentals of Digital Logic,» Buy it.. Or borrow it» Other book:
Boolean Algebra & Logic Gates. By : Ali Mustafa
Boolean Algebra & Logic Gates By : Ali Mustafa Digital Logic Gates There are three fundamental logical operations, from which all other functions, no matter how complex, can be derived. These Basic functions
DIGITAL LOGIC CIRCUITS
DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memor Components Integrated Circuits BASIC LOGIC BLOCK - GATE - Logic
Chapter 4: Combinational Logic Solutions to Problems: [1, 5, 9, 12, 19, 23, 30, 33]
![Chapter 4: Combinational Logic Solutions to Problems: [1, 5, 9, 12, 19, 23, 30, 33]](/thumbs/81/84077758.jpg "Chapter 4: Combinational Logic Solutions to Problems: [1, 5, 9, 12, 19, 23, 30, 33]")
Chapter 4: Combinational Logic Solutions to Problems: [, 5, 9, 2, 9, 23, 3, 33] Problem: 4- Consider the combinational circuit shown in Fig. P4-. (a) Derive the Boolean expressions for T through T 4. Evaluate
WEEK 3.1 MORE ON KARNAUGH MAPS
WEEK 3. MORE ON KARNAUGH MAPS Don t Cares Sometimes, we might have inputs and it doesn t matter what the output is; i.e., we don t care what the output is. These situations are called don t cares. Rather
Digital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits.
CS211 Computer Architecture Digital Logic l Topics l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Figures & Tables borrowed from:! http://www.allaboutcircuits.com/vol_4/index.html!
Contents. Chapter 3 Combinational Circuits Page 1 of 36
Chapter 3 Combinational Circuits Page of 36 Contents Combinational Circuits...2 3. Analysis of Combinational Circuits...3 3.. Using a Truth Table...3 3..2 Using a Boolean Function...6 3.2 Synthesis of
Introduction to Karnaugh Maps
Introduction to Karnaugh Maps Review So far, you (the students) have been introduced to truth tables, and how to derive a Boolean circuit from them. We will do an example. Consider the truth table for
Synchronous Sequential Circuit
Synchronous Sequential Circuit The change of internal state occurs in response to the synchronized clock pulses. Data are read during the clock pulse (e.g. rising-edge triggered) It is supposed to wait
Numbers & Arithmetic. Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University. See: P&H Chapter , 3.2, C.5 C.
Numbers & Arithmetic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See: P&H Chapter 2.4-2.6, 3.2, C.5 C.6 Example: Big Picture Computer System Organization and Programming
Combinational Logic Fundamentals
Topic 3: Combinational Logic Fundamentals In this note we will study combinational logic, which is the part of digital logic that uses Boolean algebra. All the concepts presented in combinational logic
Fundamentals of Digital Design
Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric
Design of Sequential Circuits
Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable
Z = F(X) Combinational circuit. A combinational circuit can be specified either by a truth table. Truth Table
Lesson Objectives In this lesson, you will learn about What are combinational circuits Design procedure of combinational circuits Examples of combinational circuit design Combinational Circuits Logic circuit
CS 226: Digital Logic Design
CS 226: Digital Logic Design 0 1 1 I S 0 1 0 S Department of Computer Science and Engineering, Indian Institute of Technology Bombay. 1 of 29 Objectives In this lecture we will introduce: 1. Logic functions
EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits)
EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) September 5, 2002 John Wawrzynek Fall 2002 EECS150 Lec4-bool1 Page 1, 9/5 9am Outline Review of
14:332:231 DIGITAL LOGIC DESIGN
:: DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall Lecture #: Combinational Circuit Synthesis II hat if we have input variables? V = V = of Example with variables
CS470: Computer Architecture. AMD Quad Core
CS470: Computer Architecture Yashwant K. Malaiya, Professor malaiya@cs.colostate.edu AMD Quad Core 1 Architecture Layers Building blocks Gates, flip-flops Functional bocks: Combinational, Sequential Instruction
Logic Design Combinational Circuits. Digital Computer Design
Logic Design Combinational Circuits Digital Computer Design Topics Combinational Logic Karnaugh Maps Combinational uilding locks Timing 2 Logic Circuit logic circuit is composed of: Inputs Outputs Functional
Every time has a value associated with it, not just some times. A variable can take on any value within a range
Digital Logic Circuits Binary Logic and Gates Logic Simulation Boolean Algebra NAND/NOR and XOR gates Decoder fundamentals Half Adder, Full Adder, Ripple Carry Adder Analog vs Digital Analog Continuous»
Philadelphia University Student Name: Student Number:
Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2017/2018 Dept. of Computer Engineering Course Title: Logic Circuits Date: 29/01/2018
Sample Test Paper - I
Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:
Outline. EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) Combinational Logic (CL) Defined
EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) January 30, 2003 John Wawrzynek Outline Review of three representations for combinational logic:
CS/EE 181a 2010/11 Lecture 4
CS/EE 181a 21/11 Lecture 4 General topic of today s lecture: Logic Optimization Karnaugh maps. Quine-McCluskey tabulation method (not in detail). Non series-parallel networks (some care is required). Reference
Karnaugh Maps (K-Maps)
Karnaugh Maps (K-Maps) Boolean expressions can be minimized by combining terms P + P = P K-maps minimize equations graphically Put terms to combine close to one another B C C B B C BC BC BC BC BC BC BC
Floating Point Representation and Digital Logic. Lecture 11 CS301
Floating Point Representation and Digital Logic Lecture 11 CS301 Administrative Daily Review of today s lecture w Due tomorrow (10/4) at 8am Lab #3 due Friday (9/7) 1:29pm HW #5 assigned w Due Monday 10/8
BOOLEAN ALGEBRA. Introduction. 1854: Logical algebra was published by George Boole known today as Boolean Algebra
BOOLEAN ALGEBRA Introduction 1854: Logical algebra was published by George Boole known today as Boolean Algebra It s a convenient way and systematic way of expressing and analyzing the operation of logic
Karnaugh Map & Boolean Expression Simplification
Karnaugh Map & Boolean Expression Simplification Mapping a Standard POS Expression For a Standard POS expression, a 0 is placed in the cell corresponding to the product term (maxterm) present in the expression.
Latches. October 13, 2003 Latches 1
Latches The second part of CS231 focuses on sequential circuits, where we add memory to the hardware that we ve already seen. Our schedule will be very similar to before: We first show how primitive memory
Class Website:
ECE 20B, Winter 2003 Introduction to Electrical Engineering, II LECTURE NOTES #5 Instructor: Andrew B. Kahng (lecture) Email: abk@ece.ucsd.edu Telephone: 858-822-4884 office, 858-353-0550 cell Office:
COSC 243. Introduction to Logic And Combinatorial Logic. Lecture 4 - Introduction to Logic and Combinatorial Logic. COSC 243 (Computer Architecture)
COSC 243 Introduction to Logic And Combinatorial Logic 1 Overview This Lecture Introduction to Digital Logic Gates Boolean algebra Combinatorial Logic Source: Chapter 11 (10 th edition) Source: J.R. Gregg,
Slides for Lecture 19
Slides for Lecture 19 ENEL 353: Digital Circuits Fall 2013 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 23 October, 2013 ENEL 353
ELCT201: DIGITAL LOGIC DESIGN
ELCT2: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 4 Following the slides of Dr. Ahmed H. Madian محرم 439 ه Winter 28
Philadelphia University Student Name: Student Number:
Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, Second Semester: 2015/2016 Dept. of Computer Engineering Course Title: Logic Circuits Date: 08/06/2016
EE 209 Logic Cumulative Exam Name:
EE 209 Logic Cumulative Exam Name: 1.) Answer the following questions as True or False a.) A 4-to-1 multiplexer requires at least 4 select lines: true / false b.) An 8-to-1 mux and no other logi can be
E&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev. Section 2: Boolean Algebra & Logic Gates
Digital Circuits & Systems Lecture Transparencies (Boolean lgebra & Logic Gates) M. Sachdev 4 of 92 Section 2: Boolean lgebra & Logic Gates Major topics Boolean algebra NND & NOR gates Boolean algebra
Unit 3 Session - 9 Data-Processing Circuits
Objectives Unit 3 Session - 9 Data-Processing Design of multiplexer circuits Discuss multiplexer applications Realization of higher order multiplexers using lower orders (multiplexer trees) Introduction
Digital Circuit And Logic Design I. Lecture 3
Digital Circuit And Logic Design I Lecture 3 Outline Combinational Logic Design Principles (). Introduction 2. Switching algebra 3. Combinational-circuit analysis 4. Combinational-circuit synthesis Panupong
CS/COE1541: Introduction to Computer Architecture. Logic Design Review. Sangyeun Cho. Computer Science Department University of Pittsburgh
CS/COE54: Introduction to Computer Architecture Logic Design Review Sangyeun Cho Computer Science Department Logic design? Digital hardware is implemented by way of logic design Digital circuits process
Propositional Logic. Logical Expressions. Logic Minimization. CNF and DNF. Algebraic Laws for Logical Expressions CSC 173
Propositional Logic CSC 17 Propositional logic mathematical model (or algebra) for reasoning about the truth of logical expressions (propositions) Logical expressions propositional variables or logical
Chapter-2 BOOLEAN ALGEBRA
Chapter-2 BOOLEAN ALGEBRA Introduction: An algebra that deals with binary number system is called Boolean Algebra. It is very power in designing logic circuits used by the processor of computer system.
ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN VALUES
EC 216(R-15) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, DECEMBER- 2016 First Semester ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN
Chapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal
CMPE12 - Notes chapter 2. Digital Logic. (Textbook Chapters and 2.1)"
CMPE12 - Notes chapter 2 Digital Logic (Textbook Chapters 3.1-3.5 and 2.1)" Truth table" The most basic representation of a logic function." Brute force representation listing the output for all possible
Chapter 2 (Lect 2) Canonical and Standard Forms. Standard Form. Other Logic Operators Logic Gates. Sum of Minterms Product of Maxterms
Chapter 2 (Lect 2) Canonical and Standard Forms Sum of Minterms Product of Maxterms Standard Form Sum of products Product of sums Other Logic Operators Logic Gates Basic and Multiple Inputs Positive and
CS/COE0447: Computer Organization and Assembly Language
CS/COE0447: Computer Organization and Assembly Language Logic Design Introduction (Brief?) Appendix B: The Basics of Logic Design Dept. of Computer Science Logic design? Digital hardware is implemented
CHAPTER 7. Exercises 17/ / /2 2 0
CHAPTER 7 Exercises E7. (a) For the whole part, we have: Quotient Remainders 23/2 /2 5 5/2 2 2/2 0 /2 0 Reading the remainders in reverse order, we obtain: 23 0 = 0 2 For the fractional part we have 2