Testimonials AVIRUP MULLICK, AIR 5, GATE EC 2014

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1 Testimonials AVIRUP MULLICK, AIR 5, GATE EC 214 I have secured AIR 5 and scored 1 in Gate 214. First of all, I would like to thank my parents and friends who have supported me throughout my preparation phase. I had appeared in Gate 213 casually and secured a rank of 357. Then again I decided to appear in Gate 214 as I was not happy with the IT Company in which I have got placed during campus placement. I started my preparation from June 213. I read standard textbooks for all subjects first and then referred the Gate MCQ Electronics and Communication Engineering 7th Edition. The book has exhaustive collection of all kind of possible problems on all subjects. The Books are just awesome in the sense that all the questions are well complied and each and every problem is conceptual. If one can solve these books with 75-8% accuracy, I am sure he/she can easily get a rank below 5. I would like to thank the entire Nodia Publications for publishing such wonderful books which are apt for Gate preparation. There are numerous books available in the market for GATE but quality wise, RK Kanodia books come right at the top. I would strongly recommend these books to any serious Gate aspirant in future. KULDEEP KAUSHIK, AIR-6, GATE EE 214 I solved all the volumes of the book GATE Electrical Engineering by Kanodia. These are excellent books with variety of problems. I used to study from standard books and solve problems from this book. It is 99% error less. The book can be recommended as an essential and best practice guide for the GATE aspirants. My overall reaction to this book is overwhelmingly favorable. Thanks a lot to NODIA publication! PAWAN PAREEK, AIR 8, EC GATE 212 I have secured AIR 8 and scored 1/1 in gate 212 (Roll no ). It is my Good Luck that I studied all the books of Nodia Publication and thus firmly say that R. K. Kanodia books are must for every gate aspirant. For through and basic understanding of every subject these books are the best and the most useful books available in the market. In fact R. K. Kanodia s books are so exhaustive and complete that after going through these books thoroughly, one is fully confident for appearing in any competitive examination. I strongly recommend all Nodia Publicaitons books for future gate aspirants and sincerely applaud the efforts of Nodia publication in producing such a quality and wonderful books. AVIK RAY, AIR 1, EC GATE 27 Whichever book you plan to follow for GATE preparation, I would recommend you to start with the books by R. K. Kanodia. It has an exceptional collection of objective problems. By solving them you will get a thorough grasp of the underlying theoretical concepts. Most importantly the book is mixed bag of varied problems on one given topic which gives the reader a thorough understanding of the topic.

2 COMPLEMENTARY RESOURCES Purchase all five volumes and get following complimentary resources : 1. Full Online Test Series (web-based) provided by of worth Rs GATE Electrical Engineering Solved Paper Book of worth Rs. 6. How to get Complimentary Resources : 1. Purchase all five volumes of GATE Electrical Engineering by R.K. Kanodia 2. Fill your details asked on next page in each volume. 3. Take a snapshot of the next page with your filled-details. Snapshot must have full view of the page. 4. Follow step 2 and 3 for all five volumes (Vol-1, Vol-2, Vol-3, Vol-4 and Vol-5). 5. Send these four snapshots to by Whatsapp. The test series will be activated in 2-3 working days after receiving your details. We will take your shipping address after receiving these details. The solved paper book will be delivered to your address by post. The above procedure is only for the students who purchase the books from market. For our online customers all the resources will be delivered automatically.

3 3e GATE ELECTRICAL ENGINEERING Vol 5 of 5 RK Kanodia Ashish Murolia Fill all details in Capital Letter : Book : GATE Electrical Vol 5 of 5 Name : Home Town : College : Passing Year : ID Mobile No : : NODIA & COMPANY

4 ISBN : GATE Electrical Engineering Vol 5, 3e RK Kanodia & Ashish Murolia Copyright By NODIA & COMPANY Information contained in this book has been obtained by author, from sources believes to be reliable. However, neither NODIA & COMPANY nor its author guarantee the accuracy or completeness of any information herein, and NODIA & COMPANY nor its author shall be responsible for any error, omissions, or damages arising out of use of this information. This book is published with the understanding that NODIA & COMPANY and its author are supplying information but are not attempting to render engineering or other professional services. MRP 69. NODIA & COMPANY B 8, Dhanshree Ist, Central Spine, Vidyadhar Nagar, Jaipur 3239 Ph : enquiry@nodia.co.in Printed by Nodia and Company, Jaipur

5 PREFACE The 3rd edition of GATE Electrical Engineering has been revised exhaustively as per new GATE Syllabus. The book has been completely revised in this edition, with the purpose not only of updating the material, but just as important, making the book a better learning aid. This new edition is enriched by increasing the number of problems as well as covering more topics of a subject. The book includes both the Multiple Choice Questions (MCQ) and Numerical Answer Type (NAT) problems. Each problem is accompanied by a step-by-step and well-explained solution. To improve the readability, the contents are represented with illustrative diagrams, standard notations, relatively consistent variable naming and easy-to-understand explanations. This new edition is the outcome of 1 successive years of compilation, revision & improvement of contents by the authors and their team. In the past few years, a rumor was spread to defame the book that it has some errors. After continuously reviewing each edition, we must say that the book is completely error-free from typos or any other errors. Some of our friends and colleagues teaching in various GATE coachings also claimed that a few solutions in the books are erroneous. We individually worked on those solutions and discussed them with some distinguish professors of respective subjects. We must conclude that there is only a difference in method of solving which has been interpreted as an Error by many readers. Also, the book has been thoroughly edited to remove many errors (mostly typos) which had crept into the previous editions. The few significant changes in this edition are as follows: 1. The chapter inclusions and organization of each subject has been modified as per New GATE Syllabus. 2. Number of problems in each subject has been increased. 3. Some of the explanations have been simplified to make them more understandable to the students. A student that has studied almost the syllabus of GATE during his/her B. Tech needs to enhance and practice a standard and vast collection of problems based on fundamentals of the subjects. By studying and reviewing so many solved problems and seeing how each problem is approached and how it is solved, a student can learn the skills of solving problems easily and increase his/her store of necessary Knowledge. We would like to emphasize that there is no short cut to learning except by doing. It is hoped that with these changes the book will prove more useful to the students and the teachers. There is no doubt that aspirants will benefit from this well placed book to score a good rank. R. K. Kanodia Ashish Murolia

6 SYLLABUS Section 1: Engineering Mathematics Linear Algebra: Matrix Algebra, Systems of linear equations, Eigenvalues, Eigenvectors. Calculus: Mean value theorems, Theorems of integral calculus, Evaluation of definite and improper integrals, Partial Derivatives, Maxima and minima, Multiple integrals, Fourier series, Vector identities, Directional derivatives, Line integral, Surface integral, Volume integral, Stokes s theorem, Gauss s theorem, Green s theorem. Differential equations: First order equations (linear and nonlinear), Higher order linear differential equations with constant coefficients, Method of variation of parameters, Cauchy s equation, Euler s equation, Initial and boundary value problems, Partial Differential Equations, Method of separation of variables. Complex variables: Analytic functions, Cauchy s integral theorem, Cauchy s integral formula, Taylor series, Laurent series, Residue theorem, Solution integrals. Probability and Statistics: Sampling theorems, Conditional probability, Mean, Median, Mode, Standard Deviation, Random variables, Discrete and Continuous distributions, Poisson distribution, Normal distribution, Binomial distribution, Correlation analysis, Regression analysis. Numerical Methods: Solutions of nonlinear algebraic equations, Single and Multi-step methods for differential equations. Transform Theory: Fourier Transform, Laplace Transform, z-transform. Section 2: Electric Circuits Network graph, KCL, KVL, Node and Mesh analysis, Transient response of dc and ac networks, Sinusoidal steadystate analysis, Resonance, Passive filters, Ideal current and voltage sources, Thevenin s theorem, Norton s theorem, Superposition theorem, Maximum power transfer theorem, Two-port networks, Three phase circuits, Power and power factor in ac circuits. Section 3: Electromagnetic Fields Coulomb s Law, Electric Field Intensity, Electric Flux Density, Gauss s Law, Divergence, Electric field and potential due to point, line, plane and spherical charge distributions, Effect of dielectric medium, Capacitance of simple configurations, Biot-Savart s law, Ampere s law, Curl, Faraday s law, Lorentz force, Inductance, Magnetomotive force, Reluctance, Magnetic circuits,self and Mutual inductance of simple configurations. Section 4: Signals and Systems Representation of continuous and discrete-time signals, Shifting and scaling operations, Linear Time Invariant and Causal systems, Fourier series representation of continuous periodic signals, Sampling theorem, Applications of Fourier Transform, Laplace Transform and z-transform.

7 Section 5: Electrical Machines Single phase transformer: equivalent circuit, phasor diagram, open circuit and short circuit tests, regulation and efficiency; Three phase transformers: connections, parallel operation; Auto-transformer, Electromechanical energy conversion principles, DC machines: separately excited, series and shunt, motoring and generating mode of operation and their characteristics, starting and speed control of dc motors; Three phase induction motors: principle of operation, types, performance, torque-speed characteristics, no-load and blocked rotor tests, equivalent circuit, starting and speed control; Operating principle of single phase induction motors; Synchronous machines: cylindrical and salient pole machines, performance, regulation and parallel operation of generators, starting of synchronous motor, characteristics; Types of losses and efficiency calculations of electric machines. Section 6: Power Systems Power generation concepts, ac and dc transmission concepts, Models and performance of transmission lines and cables, Series and shunt compensation, Electric field distribution and insulators, Distribution systems, Per-unit quantities, Bus admittance matrix, Gauss-Seidel and Newton-Raphson load flow methods, Voltage and Frequency control, Power factor correction, Symmetrical components, Symmetrical and unsymmetrical fault analysis, Principles of over-current, differential and distance protection; Circuit breakers, System stability concepts, Equal area criterion. Section 7: Control Systems Mathematical modeling and representation of systems, Feedback principle, transfer function, Block diagrams and Signal flow graphs, Transient and Steady-state analysis of linear time invariant systems, Routh-Hurwitz and Nyquist criteria, Bode plots, Root loci, Stability analysis, Lag, Lead and Lead-Lag compensators; P, PI and PID controllers; State space model, State transition matrix. Section 8: Electrical and Electronic Measurements Bridges and Potentiometers, Measurement of voltage, current, power, energy and power factor; Instrument transformers, Digital voltmeters and multimeters, Phase, Time and Frequency measurement; Oscilloscopes, Error analysis. Section 9: Analog and Digital Electronics Characteristics of diodes, BJT, MOSFET; Simple diode circuits: clipping, clamping, rectifiers; Amplifiers: Biasing, Equivalent circuit and Frequency response; Oscillators and Feedback amplifiers; Operational amplifiers: Characteristics and applications; Simple active filters, VCOs and Timers, Combinational and Sequential logic circuits, Multiplexer, Demultiplexer, Schmitt trigger, Sample and hold circuits, A/D and D/A converters, 885Microprocessor: Architecture, Programming and Interfacing. Section 1: Power Electronics Characteristics of semiconductor power devices: Diode, Thyristor, Triac, GTO, MOSFET, IGBT; DC to DC conversion: Buck, Boost and Buck-Boost converters; Single and three phase configuration of uncontrolled rectifiers, Line commutated thyristor based converters, Bidirectional ac to dc voltage source converters, Issues of line current harmonics, Power factor, Distortion factor of ac to dc converters, Single phase and three phase inverters, Sinusoidal pulse width modulation. ************

8 CONTENTS ANALOG ELECTRONICS CHAPTER 1 Diode Circuits 3-52 CHAPTER 2 BJT Biasing CHAPTER 3 BJT Amplifiers CHAPTER 4 FET Biasing CHAPTER 5 FET Amplifiers CHAPTER 6 Output Stages and Power Amplifiers CHAPTER 7 Op-Amp Characteristics and Basic Circuits CHAPTER 8 Op-Amp Application CHAPTER 9 Active Filters DIGITAL ELECTRONICS CHAPTER 1 Number System and Codes 3-26 CHAPTER 2 Boolean Algebra and Logic Simplification CHAPTER 3 The K-Map CHAPTER 4 Combinational Circuits CHAPTER 5 Sequential Circuits CHAPTER 6 Logic Families CHAPTER 7 Logic Families CHAPTER 8 Microprocessors POWER ELECTRONICS CHAPTER 1 Power Semiconductor Devices 3-14 CHAPTER 2 Diode Circuits and Rectifiers CHAPTER 3 Thyristor CHAPTER 4 Phase Controlled Converters CHAPTER 5 Choppers CHAPTER 6 Inverters CHAPTER 7 AC and DC Drives ********** ALL RIGHT RESERVED BY NODIA AND COMPANY

9 GATE Electrical Engineering-217 in 5 Volumes by R.K. Kanodia & Ashish Murolia Page 117 Sequential Circuits Chapter 5 CHAPTER 5 QUESTION 5.1 The input signal V i shown below is applied to the FF in given figure when initially in state. Assume all timing constraints are satisfied. The output Q is SEQUENTIAL CIRCUITS QUESTION 5.2 o.in o.in The input signal V i shown in figure below is applied to a FF in given figure when initially in its -state. Assume all timing constraints are satisfied. The output Q is *Shipping Free* Buy Online all GATE Books: *Maximum Discount*

10 GATE EE vol-1 General Aptitude GATE EE vol-2 Engineering Mathematics QUESTION 5.3 *FREE Previous year GATE Solved Paper* GATE EE vol-3 Electric Circuits, Electromagnetic Fields, Signals and Systems QUESTION 5.6 GATE EE vol-4 Electrical Machines, Power Systems, Control Systems, Electrical & Electronic Measurements GATE EE vol-5 Analog Electronics, Digital Electronics, Power Electronics Consider the circuit shown below. The expression for the next state Q + is (A) (B) xq xq (C) x Q (D) xuq QUESTION 5.4 In previous question, let the clock pulses numbered 1,2,3,... after the point at which the FF set ( ). The circuit is a (A) even parity checker (B) odd parity generator (C) Both A and B (D) None of the above QUESTION 5.5 An AB flip-flop is constructed from an SR Flip-flop below. The expression for next state Q + is (A) AB + AQ (B) AB + BQ (C) Both A and B o. wn od in A latch is to defined inputs L and M (an LM latch). The table specifying the desired next state at a clock pulse is given in below. The expression for the next state Q + is a(a) L M Q Q LM + MQ (B) LM + LQ (C) LM + MQ (D) LM + LQ QUESTION 5.7 The J clocked (A) 1 (B) (C) 1 1 (D) K inf shown below is initially cleared and then pulses, the sequence at the Q output will be (D) None of these Buy Online all GATE Books: *Shipping Free* *Maximum Discount*

11 GATE Electrical Engineering-217 in 5 Volumes by R.K. Kanodia & Ashish Murolia Page 119 Sequential Circuits Chapter 5 QUESTION 5.8 QUESTION 5.1 Consider a latch circuit shown in figure below, Which of the following set of input is invalid for circuit (A) R, H = (B) R, H = 1 (C) R 1, H = 1 (D) R 1, H = QUESTION 5.9 Consider the circuit shown below inn The input signal V 1 and V 2 shown below is applied to the above circuit. Assume initially output is in -state and all timing constraints are satisfied. The output Q is o.in For the circuit shown below, what is the frequency of the output Q (A) Twice the input clock frequency (B) Half the input clock frequency (C) Sam (D) QUESTION 5.11 he input clock frequency se of the propagation delay of the flip-flop Which of the following circuit functions as a J-K flip flop? *Shipping Free* Buy Online all GATE Books: *Maximum Discount*

12 GATE EE vol-1 General Aptitude GATE EE vol-2 Engineering Mathematics QUESTION 5.12 *FREE Previous year GATE Solved Paper* GATE EE vol-3 Electric Circuits, Electromagnetic Fields, Signals and Systems QUESTION 5.14 GATE EE vol-4 Electrical Machines, Power Systems, Control Systems, Electrical & Electronic Measurements GATE EE vol-5 Analog Electronics, Digital Electronics, Power Electronics In shown below initially A = 1 and B = 1, the input B is now replaced by a sequence the outputs X and Y will be (A) Fixed at and 1, respectively (B) Fixed at 1 and, respectively (C) X = while Y = (D) X = while Y = QUESTION 5.13 Consider a reset-dominant S R flip hown in figure below, which is reset when S R = racteristic equation of the flip-flop is given as Q n+ 1 = SR + RQ n Then combinational logic is (A) S A S + (B) S SR A (C) S SR A (D) S A SR R aco n In the following circuit, Initially flip flop is cleared. If input clock frequency is f, then frequency at output will be (A) 2f (B) f 2 (C) will be same as input QUESTION 5.15 The digital circuit shown in the figure works as (A) lip-flop RS flip-flop a.cclocked a(c) T - flip-flop (D) Ring counter QUESTION 5.16 A J-K flip flop can be made from and S-R flip flop by using two additional (A) AND gates (B) OR gates (C) NOT gates (D) NOR gates Buy Online all GATE Books: *Shipping Free* *Maximum Discount*

13 GATE Electrical Engineering-217 in 5 Volumes by R.K. Kanodia & Ashish Murolia Page 121 Sequential Circuits Chapter 5 QUESTION 5.17 QUESTION 5.19 A sequential circuit using D flip-flop and logic gates is shown below where X and Y are the inputs and Z is the output. The circuit is (A) S R FF with inputs X R and Y S (B) S R FF with inputs X S and Y R (C) J K FF with inputs X J and Y K (D) J K FF with inputs X K and Y J QUESTION 5.18.c oin in Consider a circuit shown in figure. The circuit functions as (A) D-flip-flop (B) T-flip-flop (C) Output remains stable at '1' (D) Output remains stable at '' in An X Y flip-flop whose characteristic table is given below is to be implemented using a J-K flip-flop X Y Q n Q n 1 Q n 1 1 This can be done by using (A) J iny (B K Y cox,k J Y,,KK X (D) J Y, K X QUESTION 5.2 The digital block shown below realized using two positive edge triggered D-flip-flop. Assume that for t t, ircuit in the digital block is given by *Shipping Free* Buy Online all GATE Books: *Maximum Discount*

14 GATE EE vol-1 General Aptitude GATE EE vol-2 Engineering Mathematics QUESTION 5.21 *FREE Previous year GATE Solved Paper* GATE EE vol-3 Electric Circuits, Electromagnetic Fields, Signals and Systems QUESTION 5.23 GATE EE vol-4 Electrical Machines, Power Systems, Control Systems, Electrical & Electronic Measurements GATE EE vol-5 Analog Electronics, Digital Electronics, Power Electronics Consider the following circuit The flip-flop are positive edge trigger red D FFs. Each state is designated as a two bit string QQ 1. Let the initial state be. The state transition sequence is QUESTION 5.22 How many flip flops will be complemented in a 1-bit ripple counter to reach the next count after (A) 4 (B) 5 (C) 6 (D) 9 in y ount odi.c o. n Consider the partial implementation of a 2-bit counter using T flip-flop following the sequence as shown below To compl (A) (C) Q Q 1 a.( ) (D) Q Q 2 QUESTION 5.24 e circuit the input X should be The following serial data are applied to the flip-flop through the AND gates as shown in figure. There is one clock pulse for each bit time. Q is initially and PRE and CLR are high. If leftmost bits are applied first then output Q is J 1 : 1111, J 2 : 1111, J 3 : 1111 K 1 : 111, K 2 : 1111, K 3 : 1111 (A) 111 (B) 11 (C) 11 (D) 1111 Buy Online all GATE Books: *Shipping Free* *Maximum Discount*

15 GATE Electrical Engineering-217 in 5 Volumes by R.K. Kanodia & Ashish Murolia Page 123 Sequential Circuits Chapter 5 QUESTION 5.25 QUESTION 5.28 The circuit shown in figure below is (A) a MOS-2 counter (B) a MOD-3 counter (C) generate sequence, 1, 1,... (D) generate sequence, 1,, 1,... QUESTION 5.26 Consider a sequential circuit shown in figu ially all the flip-flop are reset. Output QQQQ 1 Q 2 afte pulse is (A) 1 (B) 11 (C) 11 (D) 111 QUESTION 5.27 o.in in.c o.in A 4 bit modulo - 6 ripple counter uses JK flip-flop. If the propagatuion delay of each FF is 5 ns, the maximum clock frequency that can be used is equal to The counter shown in figure below is a (A) MOD- up counter (B) M down counter (C OD-6 up counter ) MOD-6 down counter QUESTION 5.29 For the circuit shown in figure below, what is the output QQQQ 1, after four clock pulses. Initially all flip-flop are reset (A) 1 (B) 11 (C) 11 (D) 1 MHz *Shipping Free* Buy Online all GATE Books: *Maximum Discount*

16 GATE EE vol-1 General Aptitude GATE EE vol-2 Engineering Mathematics QUESTION 5.3 *FREE Previous year GATE Solved Paper* GATE EE vol-3 Electric Circuits, Electromagnetic Fields, Signals and Systems QUESTION 5.32 GATE EE vol-4 Electrical Machines, Power Systems, Control Systems, Electrical & Electronic Measurements GATE EE vol-5 Analog Electronics, Digital Electronics, Power Electronics The counter shown in figure below counts from (A) to (B) to (C) 1 to (D) to 1 QUESTION and 31 : Consider the circuit shown in followin e : The correct input output relationship between Y a is (A) Y = +XX (B) Y X 1 2 X 1 X 2 (C) Y X15 X2 (D) Y X15 X2 ac o.i o 2 ) o,x od Xd In previous question, the D-flip-flop are initialized to QQQQ 2 3 = after 1 clock cycle, QQQQ 2 3 is equal to (A) 11 (B) 1 (C) 1 (D) 11 QUESTION 5.33 Cons sequential circuit using three J-K flip-flops and on D gate shown in figure. Output of the circuit becomes cter every N -clock cycles. The value of N is QUESTION 5.34 The mod-number of the asynchronous counter shown in figure below is Buy Online all GATE Books: *Shipping Free* *Maximum Discount*

17 GATE Electrical Engineering-217 in 5 Volumes by R.K. Kanodia & Ashish Murolia Page 125 Sequential Circuits Chapter 5 QUESTION 5.35 QUESTION 5.37 The three-stage Johnson counter as shown in figure below is clocked at a constant frequency of f c from the starting state of QQQQ 1 = 11. The frequency of output QQQQ 1 will be (A) (B) (C) (D) f 8 c f 6 c f 3 c f 2 c QUESTION 5.36 contents of the 4-bit serial-in-parallel-out right- hift, register shown in fig. below is 1 1. After three clock a.cinitial pulses are applied, the contents of the shift register will be ac The counter shown in the figure below has initially QQQQ 1 =. The status of Q QQ 1 after the first pulse is (A) 1 (B) 1 (C) 1 (D) 1 1 in A 4 bit ripple counter and a 4 bit synchronous counter are made by flips flops having a propagation delay of 1 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then (A) R = 1 ns, S = 4 ns (B) R = 4 ns, S = 1 ns (C) R = 1 ns, S = 3 ns (D) R = 3 ns, S = 1 ns QUESTION 5.38 (A) (B) 1 1 (C) (D) 1 1 QUESTION 5.39 A 4-bit right shift register is initialized to value 1 for (, Q2, Q, Q ). The D input is derived from Q, Q 2 and Q 3 through two XOR gates as shown in fig. below. The pattern 1 will appear at th pulse *Shipping Free* Buy Online all GATE Books: *Maximum Discount*

18 GATE EE vol-1 General Aptitude GATE EE vol-2 Engineering Mathematics QUESTION 5.4 *FREE Previous year GATE Solved Paper* GATE EE vol-3 Electric Circuits, Electromagnetic Fields, Signals and Systems QUESTION 5.43 GATE EE vol-4 Electrical Machines, Power Systems, Control Systems, Electrical & Electronic Measurements GATE EE vol-5 Analog Electronics, Digital Electronics, Power Electronics The 8-bit left shift register and D flip-flop shown in fig. below is synchronized with same clock. The D flip-flop is initially cleared. The circuit act as (A) Binary to 2 s complement converter (B) Binary to Gray code converter (C) Binary to 1 s complement converter (D) Binary to Excess-3 code converter QUESTION 5.41 in In previous question, if initially register contains byte B7, then after 4 clock pulse contents of register will be (A) 73 (B) 72 (C) 7E (D) 74 QUESTION 5.42 The frequency of the pulse at z in t figure below is work shown in Hz A Mealy system produces a 1 output if the input has been for at least two consecutive clocks followed immediately by two or more consecutive 1 s. The minimum state for this system is QUESTION 5.44 In previous question, the flip-flop required to implement this system are QUESTION 5.45 The output of a Mealy system is 1 if there has been a pattern of 11, otherwise. The minimum state for this system is QUESTION 5.46 To from to 124 the number of required flip-flop is QUESTION 5.47 Four memory chips of 16 4 # size have their address buses connected together. This system will be of size (A) 64 4 # (B) 32 8 # (C) # (D) # Buy Online all GATE Books: *Shipping Free* *Maximum Discount*

19 GATE Electrical Engineering-217 in 5 Volumes by R.K. Kanodia & Ashish Murolia Page 127 Sequential Circuits Chapter 5 QUESTION 5.48 QUESTION 5.51 For the circuit shown below consider the statement : Assertion (A) : The circuit is sequential Reason (R) : There is a loop in circuit Choose correct option (A) Both A and R true and R is the correct explanation of A (B) Both A and R true but R is not a correct explanation on of A (C) A is true but R is false (D) A is false QUESTION 5.49 In the given counter each flip-flop has a propagation delay of 8 n sec. The worst-case (longest) delay time from a clock arrival of the counter in a given state is QUESTION 5.5 ho nano sec o the. in A binary counter is being pulsed by a 256 khz clock signal. The output frequency from the last flip-flop is 2 khz. The MOD number is It is required to obtain 62.5 khz from 1 MHz clock. Which of the following block diagram represent it correctly? QUESTION 5.52 Consider the following decoder used as a generator of control signal. If RESET pulse occurs only at time t then the control waveform for 32 clock pulse is given by : *Shipping Free* Buy Online all GATE Books: *Maximum Discount*

20 GATE EE vol-1 General Aptitude GATE EE vol-2 Engineering Mathematics QUESTION 5.53 *FREE Previous year GATE Solved Paper* GATE EE vol-3 Electric Circuits, Electromagnetic Fields, Signals and Systems QUESTION 5.56 GATE EE vol-4 Electrical Machines, Power Systems, Control Systems, Electrical & Electronic Measurements GATE EE vol-5 Analog Electronics, Digital Electronics, Power Electronics Consider the following 4-bit asynchronous binary counter. If each flip-flop has a propagation delay for 1 ns, then the maximum clock frequency is QUESTION 5.54 Consider the following counter MHz n If counter starts at, what will be the count after 13 clock pulses? (A) 1 (B) 11 (C) 11 (D) 111 QUESTION 5.55.c n The address bus width of a memory of size # bits is The MOD number of the given counter is QUESTION 5.57 Consider the following register which initially starts at state. The state of register after 1 clock pulse is (A) (B) (C) (D) Buy Online all GATE Books: *Shipping Free* *Maximum Discount*

21 GATE Electrical Engineering-217 in 5 Volumes by R.K. Kanodia & Ashish Murolia Page 129 Sequential Circuits Chapter 5 QUESTION 5.58 Consider the following sequential circuit. For the given sequential circuit the next state equations for flip-flop A and B are + (A) A = A( Bl+ X) + Al( BXl+ BlX) + and B = ABlX+ B( Al+ Xl) + (B) A = A( BlX) + Al( BXl+ BlX) + and B = A( Bl+ X) + B( AlXl) + (C) A = A( BlX) + Al( BXl) + and B = A( BlX) + B( AlXl) + (D) A = A( Bl+ X) + Al( BXl+ BlX) + and B = AlX+ BlXlAl ************ *Shipping Free* Buy Online all GATE Books: *Maximum Discount*

22 GATE EE vol-1 General Aptitude GATE EE vol-2 Engineering Mathematics SOLUTION 5.1 Correct option is (C). Given FF is a negative edge triggered T flip-flop. So at the negative edge of clock V i FF will invert the output if there is 1 at input. SOLUTION 5.2 Correct option is (A). At first rising edge of clock, D is HIGH. S be high till 2nd rising edge of clock. At 2nd risin p.nill pd is low so Q will be LOW till 3rd rising edge of c At 3rd rising edge, D is HIGH, so Q will be HIGH HIGH till 5th rising. edge. At 5th rising edge, D is LOW, so Q will be LOW till 6th rising edge. SOLUTION 5.3 Correct option is (C). The truth table is shown below x Q S R Q *FREE Previous year GATE Solved Paper* GATE EE vol-3 Electric Circuits, Electromagnetic Fields, Signals and Systems SOLUTIONS SOLUTION 5.4 Correct option is (D). Q + = x Q Q 1 + inq o.. in 3 Q 4 + = = x x, GATE EE vol-4 Electrical Machines, Power Systems, Control Systems, Electrical & Electronic Measurements = x + x = x x 2 5x1 = x x 5x x 4 x GATE EE vol-5 Analog Electronics, Digital Electronics, Power Electronics So this generate the even parity and check odd parity. SOLUTION 5.5 Correct option is (C). The truth table is shown below A B S R Q Q # # Q + = AB + AQ = AB + BQ Buy Online all GATE Books: *Shipping Free* *Maximum Discount*

23 GATE Electrical Engineering-217 in 5 Volumes by R.K. Kanodia & Ashish Murolia Page 131 Sequential Circuits Chapter 5 SOLUTION 5.6 SOLUTION 5.9 Correct option is (D). Q + = LM + LMQ L ( ) LM + LQ The truth table is shown below L M Q Q 1 SOLUTION 5.7 Correct option is (D). The truth table is shown below Initially J K Q Q Q n+ 1 Q n Clock 1st nd rd th th Therefore sequence is SOLUTION 5.8 in n Correct option is (D). Form table we get that R = 1 and H = can no r at the same time R H Q Q # 1 1 # n Correct option is (A). Circuit shown in figure is a D-flip flop with input D V 1 and CLK = V 2 SOLUTION 5.1 Correct option is (B). Input to the D flip-flop is D Q n Output Q D n = Q n So, output will toggle at every clock pulse, outp frequency will be half of input frequency. D n n SOLUTION 5.11 Correct option is (D). In option (D) Output of the MUX is Y = D S SI+ SSIS 1 S SI+ SSI 1 I 1 1 S1 I 2 1S 3 Here, I Q n, I Q n, I 1 =, I 2 = 1 So, Y D = J KQ JK JKQ n Next state + = D inq J KQn (by simplifying) Q n 1 SOLUTION 5.12 Correct option is (A). The truth table is as shown below A B X Y *Shipping Free* Buy Online all GATE Books: *Maximum Discount*

24 GATE EE vol-1 General Aptitude GATE EE vol-2 Engineering Mathematics SOLUTION 5.13 *FREE Previous year GATE Solved Paper* GATE EE vol-3 Electric Circuits, Electromagnetic Fields, Signals and Systems SOLUTION 5.16 GATE EE vol-4 Electrical Machines, Power Systems, Control Systems, Electrical & Electronic Measurements GATE EE vol-5 Analog Electronics, Digital Electronics, Power Electronics Correct option is (D). Characteristic equation for SR flip-flop is given as Q n 1 + = S A R Q A A n Comparing with above equation S A SOLUTION 5.14 Correct option is (B). Here T is T = Q Q T = 1 (always) n & = SR So, output will toggle at each clock pulse. The output sequence is Frequency of output is f 2 SOLUTION 5.15 Correct option is (C). Input to the D-flip-flop can be written as D n = Q X For a D-flip-flop output is Q n 1 + = D Q n 5 X By Drawing the truth table So, Q X Q n Q n Q n for This is a T-flip flop. X = and Q Q o.in n o.in oin in shn for X = 1 Correct option is (A). To realize a J-K flip flop from an S-R flip-flop, we should have S JQ n, R KQ n So, we have to use two additional AND gate. SOLUTION 5.17 Correct option is (D). Z The tru = XQ + YQ e is shown below X Y Z Q Q 1 Comparing from the truth table of J K FF Y J,X, K SOLUTION 5.18 Correct op n is (B). From t mbinational logic Let Q n is present state, Q n+ 1 is next state, then R = D Q, S D5 Q conput, acharacteristic equation of R-S flip-flop is given by Q n+ 1 = S RQ n So, Q n+ 1 = ( ) + ( )Qn = ( ) ( )Qn = ( )(1 5 Q ) ( D5 Qn) = DQ n + DQ For D =, Q Q n D = 1, Q Q n So, the circuit function as a T-flip flop. n Buy Online all GATE Books: *Shipping Free* *Maximum Discount*

25 GATE Electrical Engineering-217 in 5 Volumes by R.K. Kanodia & Ashish Murolia Page 133 Sequential Circuits Chapter 5 SOLUTION 5.19 SOLUTION 5.21 Correct option is (D). Let Q n is the present state and Q n+ 1 is next state of given X Y flip-flop. X Y Q n Q n Solving from K-map we get Characteristic equation of X Q n+ 1 = YQ n +XQ n Characteristic equation of a J Q n 1 + = JQ n + KQ Comparing J Y, K X SOLUTION 5.2 n Y flip-flop is Correct option is (C). The Input and output is as shown below K flip-flop is given Correct option is (D). In the circuit D = Q, od o n in D 1 = Q Q 1 Initial state " Q Q 1 D D (repeat) So, the state transition sequence QQQ 1 is SOLUTION 5.22 Correct option is (A). Count is Next count is 1111 So, no. of F to be complement SOLUTION 5.23 Correct option is (D). Sequence We have T = QQ + QQQ = Q Q T 1 Q 2 Q 1 2 = 4 *Shipping Free* Buy Online all GATE Books: *Maximum Discount*

26 GATE EE vol-1 General Aptitude GATE EE vol-2 Engineering Mathematics SOLUTION 5.24 *FREE Previous year GATE Solved Paper* GATE EE vol-3 Electric Circuits, Electromagnetic Fields, Signals and Systems SOLUTION 5.27 GATE EE vol-4 Electrical Machines, Power Systems, Control Systems, Electrical & Electronic Measurements GATE EE vol-5 Analog Electronics, Digital Electronics, Power Electronics Correct option is (B). Applying the serial bits for J and K inputs of the flip-flop CLK J J J K K K J K Q SOLUTION Correct option is (B). The truth table is shown below Present State FF Input Next State Q A Q B T A T B 1 T Q A + Q B From table it is clear that it is a MOD-3 counter. SOLUTION 5.26 Correct option is (B). This is a 3 bit counter, so the output se CLK Q 2 Q 1 Q Initially o.i inn e is Correct answer is 5 MHz. 4 bit uses 4 FF Total delay Nt d = 4# 5ns = 2 # 1 9 f = 1 9 = 5MHz 2 # 1 SOLUTION 5.28 Correct option is (B). It is a do unter because state of previous FFs change the st next FF. You may trace the following sequence, let state be FF C FF B FF A J K C J K B J K A C + B + A SOLUTION 5.29 acorrect option is (B). The truth table is as shown below Q 2 Q 1 Q D 2 D 1 D Initially 1 At Clock At Clock At Clock At Clock At Clock At Clock Buy Online all GATE Books: *Shipping Free* *Maximum Discount*

27 GATE Electrical Engineering-217 in 5 Volumes by R.K. Kanodia & Ashish Murolia Page 135 Sequential Circuits Chapter 5 SOLUTION 5.3 Correct option is (C). It is a down counter because the inverted FF output drive the clock inputs. The NAND gate will clear FFs A and B when the count tries to recycle to 111. This will produce as result of 1. Thus the counting sequence will be 1, 11, 1, 1,, 1 etc. SOLUTION 5.31 Correct option is (D). From the figure Y = X 1 X + X X + X + X 1 X Y = X 1 ( ) X 2 ( ) A+ B = AB SOLUTION 5.32 Y = XX+ XX + XXX + XXX 1X1 1X = XX + XXX = X X 1X Correct option is (B). Initially QQQQ 2 3 = In the circuit D 1 = X Q 3 = X 2 = = Q 1 D 2 = Y X 5XX = 1 D 3 = = Q 2 1 X 2 Inputs to the flip flops are D 1 =, D 1 = 1, After 1 clock cycle outputs are Q 1 =, SOLUTION 5.33 Correct answer is 6. Let initially output is 1, then Q D Q = p.3 inn CLK Q 2 Q 1 Q Z Initially It is a modulo 6-counter So, output Z will be 1 after every 6 clock pulses SOLUTION 5.34 ect answer is 24. It is a 5 bit ripple counter. At 11 the output of NAND gate is LOW. This will clear all FF. So it is a Mod-24 counter. Note that when 11 occur, the CLR input is activated and all FF are immediately cleared. So it is a MOD 24 counter not MOD 25. SOLUTION 5.35 Correct option is (D). The truth e is as shown below QQQ QQQ 2 QQQ 1 JK J 1 K 1 J K Q + 2 Q Q We see that 1 1 repeat after every two cycles, hence frequency will be f 2 c. SOLUTION 5.36 Correct option is (C). At first cycle *Shipping Free* Buy Online all GATE Books: *Maximum Discount*

28 GATE EE vol-1 General Aptitude GATE EE vol-2 Engineering Mathematics *FREE Previous year GATE Solved Paper* GATE EE vol-3 Electric Circuits, Electromagnetic Fields, Signals and Systems GATE EE vol-4 Electrical Machines, Power Systems, Control Systems, Electrical & Electronic Measurements GATE EE vol-5 Analog Electronics, Digital Electronics, Power Electronics JK 2K2 2 JK JK = 1 & Q2 = 1, 1K1 1 = 1 & Q1 =, K = 1 & Q = SOLUTION 5.37 Correct option is (B). In ripple counter delay 4 d 4ns. The synchronous counter are clocked simultaneously, then its worst delay will be equal to 1 ns. SOLUTION 5.38 Correct option is (D). At pulse 1 input, 1 = 1 So contents are 1 1 1, At pules 2 input 1 1 = So contents are 1 1, At pules 3 input 1 = 1, contents a 1 SOLUTION 5.39 Correct answer is 6. The truth table is as shown below CLK Q 3 Q 2 Q 1 Q XOR 1 XOR 2 Initially 1 1 1st nd rd th 1 1 5th th 1 SOLUTION 5.4 Correct option is (B). ḃ o. o. inn od o.i in The output of XOR gate is Z bi 1 5 bi and this output shift the register to left, Initially Z = After 1st clock Z b 7 5 = b7 After 2nd clock Z b75 b6 3rd clock Z b65 b5 4th clock Z b55 b4 SOLUTION 5.41 Correct option is (C). n , After four clock o.l b 4 = bbbb 3 b2 1 b = 7, o5 bl = b bl = b b = 1, b 6 bl = b b = 1 6 b 5 bl = b b =, = E SOLUTION b 4 Correct a is 5 MHz. 1-bit counter is a MOD-1, so it divides the 16 khz in y 1, therefore, w = 16 khz. The four-bit parallel is a MOD-16. Thus, the frequency at x = 1 khz. The MOD-25 ripple counter produces a frequency at y = 4 Hz a.cter. (1 khz/25 = 4 Hz). The four-bit Johnson Counter is a MOD-8. This, the frequency at z = 5 Hz. SOLUTION 5.43 Correct answer is 4. The state diagram is as shown below Buy Online all GATE Books: *Shipping Free* *Maximum Discount*

29 GATE Electrical Engineering-217 in 5 Volumes by R.K. Kanodia & Ashish Murolia Page 137 Sequential Circuits Chapter 5 SOLUTION 5.47 There are 4 minimum state SOLUTION 5.44 Correct answer is , Thus 2 FF are required. SOLUTION 5.45 Correct answer is 5. The state diagram is shown below There are five minimum state is 5. SOLUTION 5.46 o. inn Correct answer is flip-flop will count from to 123. Hence 11 flip-flop are required to count from to 124. Correct option is (C). Since all chip has same address, the capacity of word will be increased. SOLUTION 5.48 Correct option is (D). There is no active loop in the network because variable b interrupts the loop at two different point. When b =, z = ad c When 1 z, z = e + c As n see from the equation there is no feed back of s in the physical loop, and the circuit is combinational. ad n iz z d o n SOLUTION 5.49 Correct answer is 24 nano sec. t p ( ) = 3(8 ) = 24 n sec SOLUTION 5.5 Co nswer is 128. Number = 256 khz = khz a.cmod SOLUTION 5.51 Correct option is (D). 1 MHz = 1 MHz = 5 MHz = 25 khz = 125 khz = 62.5 khz So the correct answer is *Shipping Free* Buy Online all GATE Books: *Maximum Discount*

30 GATE EE vol-1 General Aptitude GATE EE vol-2 Engineering Mathematics SOLUTION 5.52 *FREE Previous year GATE Solved Paper* GATE EE vol-3 Electric Circuits, Electromagnetic Fields, Signals and Systems SOLUTION 5.56 GATE EE vol-4 Electrical Machines, Power Systems, Control Systems, Electrical & Electronic Measurements GATE EE vol-5 Analog Electronics, Digital Electronics, Power Electronics Correct option is (B). The output O 3 will be LOW only when A2,A A1, A = 11, E3 1,E E2. This condition is present after the 28 th and 29 th negative triggering of the clock. That is : 28 1 = = Thus, O 3 will appear are shown below : SOLUTION 5.53 Correct answer is 25 MHz. t p ( ) = 4 # 1 4 ns So, the maximum clock frequency is f max = 1 = 1 tp ( ) 4 ns = 25 MHz SOLUTION 5.54 o.in Correct option is (B). This is a counter that will recycle every 8 pulses (MOD counter). Count after 13 clock pulses is 5(11). SOLUTION 5.55 Correct answer is 1. There are 124 memory location 124 = 2 1. Hence address bus width = 1 bits. Correct answer is 14. This is a 4-bit counter, which would normally count from through The NAND inputs are DC, and B, which means that the counter will immediately recycle to when the 111 (decimal 14) count is reached. Thus, the counter actually has 14 stable states through 111 and is therefore a MOD 14 counter. SOLUTION 5.57 Correc n is (B). After After SOLUTION 5.58 Initially " st clock " nd clock " After 3 rd clock " After 4 th clock " After 5 th clock " After 6 th clock " After 7 th clock " After 8 th clock " After 9 th clock " iner in1 th clock " Correct option is (A). A + = AK A l + AJ A and B + = BJ B + BK B l = A( ( ) + Al( ) = B ( ) + B(( A + Xl)) l = BAX+B( ) = ABlX +B( ) *********** Buy Online all GATE Books: *Shipping Free* *Maximum Discount*