電子回路論第 12 回 Electric Circuits for Physicists

Size: px

Start display at page:

Download "電子回路論第 12 回 Electric Circuits for Physicists"

Agatha Strickland
5 years ago
Views:

1 電子回路論第 12 回 Electric Circuits for Physicists 東京大学理学部理学系研究科物性研究所勝本信吾 Shingo Katsumoto

2 Review: Sampling theorem x(t) x(t) t t t

3 Review: Sampling theorem 2p/t ω h : Highest frequency in X τ (ω) Pπ(ω) τ 1 π τ π τ w

4 6.4.2 Pulse amplitude modulation (PAM) f(t) s(t) t t t Carrier: δ τ (t) Demodulation = Reconstruction of continuous signal from sampled data.

5 6.4.3 Discrete Fourier transform f (t) 0 z t -z f(t) 0 z t 2z Fourier expansion:

6 6.4.3 Discrete Fourier transform Twiddle factor:

7 6.4.3 Discrete Fourier transform Twiddle factor: Discrete Fourier transform: (DFT)

8 6.4.3 Discrete Fourier transform

9 6.4.4 z-transform Discrete Laplace transform: z-transform one-sided z-transform

10 6.4.4 z-transform

11 6.4.4 z-transform

12 6.4.5 Transfer function for discrete time signal h n : (impulse) response to δ(nτ), Response to discrete signal f n = f τ (nτ) : Transfer function

13 Ch.7 Digital signal and circuits s (t) Discrete time analog d (t) t 2t 5t t Value discretized Digital signal t Signal unit : 0 xor 1 (bit) Boolean algebra : F xor T Voltage level : L xor H Multiple bit binary operation parallel signal

14 7.2 Logic gates Digital signal=logic value Logic operation : logic gates De Morgan's laws: x + y = x y, x y = x + y Combinational logic Truth table Sequential logic Timing chart

15 7.2.1 Combinational logic: Single input gates Truth table Circuit symbol

16 7.2.2 Combinational logic: Double input gates

17 7.2.3 Sequential logic: Flip-Flop (FF) RS (reset-set) Flip-Flop (FF) Truth table Symbol Equivalent circuit with discrete gates

18 7.2.3 Sequential logic: Flip-Flop (FF) JK Flip-Flop Truth table Symbol Equivalent circuit with discrete gates

19 7.2.3 Sequential logic: D-FF, T-FF D-FF Symbol Truth table T-FF Symbol Truth table

20 7.2.4 Sequential logic: Counters Unsynchronized counter (ripple counter) Timing chart

21 7.2.4 Sequential logic: Counters Synchronized counter Equivalent circuit with discrete gates Timing chart

22 7.3 Implementation of logic gates NAND gates TTL (transistor-transistor logic) CMOS (complimentary MOS)

23 7.3 Implementation of logic gates LT Spice simulation

24 7.3 Implementation of logic gates Voltage levels diagram

25 TTL logic family evolution Legacy: don t use in new designs Widely used today

26 CMOS logic family evolusion obsolete General trend: Reduction of dynamic losses through successively decreasing supply voltages: 12V 5V 3.3V 2.5V 1.8V CD4000 LVC/ALVC/AVC Power reduction is one of the keys to progressive growth of integration

27 Summary TTL Logic Family T PD T rise/fall V IH,min V IL,max V OH,min V OL,max Noise Margin CMOS

28 7.4 Circuit implementation and simplification of logic operation Truth table Simplification Circuit diagram Visual method: Karnaugh mapping Simplification Quine-McClusky algorithm Product of all the logic variables: canonical expansion principal disjunctive canonical expansion ( 主加法標準展開 ) Ex) Or in binary: Y =

29 Quein-McClusky algorithm Classification with the number of 1 Y = _+11_1 Num.of 1 smallest compress1 compress _ _ _ 1011 _ _ _1 First simplification smallest _ 11_1 Y = _ Final form

30 Wolfram Alpha

two T-FF Transition state input output state FF

31 Design of sequential logic circuit: State diagram State (transition) diagram: Ex) 2-bit counter with two T-FF Transition state input output state FF output: Karnaugh map simplification Recursion equation:

32 Design of sequential logic circuit: State diagram Characteristic equation (recursion equation) T-FF : y x TFF1 TFF2

Gates and Flip-Flops

Gates and Flip-Flops Chris Kervick (11355511) With Evan Sheridan and Tom Power December 2012 On a scale of 1 to 10, how likely is it that this question is using binary?...4? What s a 4? Abstract The operation