Lecture 25: New Computer Architectures and Models -- Neuromorphic Architecture, Quantum Computing and 3D Integration/Photonics/ Memristor

Transcription

1 Lecture 25: New Computer Architectures and Models -- Neuromorphic Architecture, Quantum Computing and 3D Integration/Photonics/ Memristor CSE 564 Computer Architecture Fall 2016 Department of Computer Science and Engineering Yonghong Yan

2 Acknowledge and Copyright 2

3 REVIEW FOR SYNCHRONIZATIONS 3

4 Data Racing in a Multithread Program Consider: /* each thread to update shared variable best_cost */!! if (my_cost < best_cost)! best_cost = my_cost; two threads, the initial value of best_cost is 100, the values of my_cost are 50 and 75 for threads t1 and t2! T1 T2! if (my_cost (50) < best_cost)! if (my_cost (75) < best_cost)!! best_cost = my_cost;! best_cost = my_cost; best_cost = my_cost; The value of best_cost could be 50 or 75! The value 75 does not correspond to any serialization of the two threads. 4 4

5 Mutual Exclusion using Pthread Mutex int pthread_mutex_lock (pthread_mutex_t *mutex_lock);! int pthread_mutex_unlock (pthread_mutex_t *mutex_lock);! int pthread_mutex_init (pthread_mutex_t const pthread_mutexattr_t *lock_attr);!!*mutex_lock,! pthread_mutex_t cost_lock; int main() { pthread_mutex_lock blocks the calling thread if another thread holds the lock }... pthread_mutex_init(&cost_lock, NULL); pthread_create(&thhandle1, NULL, find_best, ); pthread_create(&thhandle2, NULL, find_best, ); When pthread_mutex_lock call returns 1. Mutex is locked, enter CS 2. Any other locking attempt (call to thread_mutex_lock) will cause the blocking of the calling thread void *find_best(void *list_ptr) {... pthread_mutex_lock(&cost_lock); // enter CS if (my_cost < best_cost) Critical Section best_cost = my_cost; pthread_mutex_unlock(&cost_lock); // leave CS When pthread_mutex_unlock returns 1. Mutex is unlocked, leave CS 2. One thread who blocks on thread_mutex_lock call will acquire the lock and enter CS } 5

6 Choices of Hardware Primitives for Synchronizations -- 2 Compare and Swap (CAS) compare&swap (&address, reg1, reg2) { if (reg1 == M[address]) { M[address] = reg2; return success; } else { return failure; } } Load-linked and Store-conditional load-linked&store conditional(&address) { loop: ll r1, M[address]; movi r2, 1; /* Can do arbitrary comp */ sc r2, M[address]; beqz r2, loop; } 6

7 Improved Hardware Primitives: LL-SC Goals: Test with reads Failed read-modify-write attempts don t generate invalidations Nice if single primitive can implement range of r-m-w operations Load-Locked (or -linked), Store-Conditional LL reads variable into register Follow with arbitrary instructions to manipulate its value SC tries to store back to location succeed if and only if no other write to the variable since this processor s LL» indicated by condition codes; If SC succeeds, all three steps happened atomically If fails, doesn t write or generate invalidations must retry aquire 7

8 Simple Lock with LL-SC lock:!ll!r1, mem[cost_lock]/* LL location to reg1 */ sc!mem[cost_lock], R2 /* SC reg2 into location*/ beqz!r2, lock /* if failed, start again */ ret unlock:!st!mem[cost_lock], #0 /* write 0 to location */ ret Can do more fancy atomic ops by changing what s between LL & SC But keep it small so SC likely to succeed Don t include instructions that would need to be undone (e.g. stores) SC can fail (without putting transaction on bus) if: Detects intervening write even before trying to get bus Tries to get bus but another processor s SC gets bus first LL, SC are not lock, unlock respectively Only guarantee no conflicting write to lock variable between them But can use directly to implement simple operations on shared variables 8

9 Memory Consistency Model One of the most confusing topics (if not the most) in computer system, parallel programming and parallel computer architecture 9

10 VON NEUMANN ARCHITECTURE AND TURING MACHINE 10

11 The Stored Program Computer 1944: ENIAC Presper Eckert and John Mauchly -- first general electronic computer. hard-wired program -- settings of dials and switches. 1944: Beginnings of EDVAC among other improvements, includes program stored in memory 1945: John von Neumann wrote a report on the stored program concept, known as the First Draft of a Report on EDVAC failed to credit designers, ironically still gets credit The basic structure proposed in the draft became known as the von Neumann machine (or model). a memory, containing instructions and data a processing unit, for performing arithmetic and logical operations a control unit, for interpreting instructions More history in the optional online lecture 11

12 John von Neumann 12

13 Von Neumann Architecture (Model) Machine Model Architecture 13

14 The Von Neumann Architecture Model for designing and building computers, based on the following three characteristics: 1) Main sub-systems of computers» Memory» ALU (Arithmetic/Logic Unit)» Control Unit» Input/Output System (I/O) 2) Program is stored in memory during execution. 3) Program instructions are executed sequentially. 14

15 Memory k x m array of stored bits (k is usually 2 n ) Address unique (n-bit) identifier of location Contents m-bit value stored in location Need to distinguish between the address of a memory cell and the content of a memory cell

16 Operations on Memory Fetch (address): Fetch a copy of the content of memory cell with the specified address. Non-destructive, copies value in memory cell. Store (address, value): Store the specified value into the memory cell specified by address. Destructive, overwrites the previous value of the memory cell. The memory system is interfaced via: Memory Address Register (MAR) Memory Data Register (MDR) Fetch/Store signal 16

17 Processing Unit Functional Units ALU = Arithmetic and Logic Unit could have many functional units. some of them special-purpose (multiply, square root, ) Registers Small, temporary storage Operands and results of functional units Word Size number of bits normally processed by ALU in one instruction also width of registers 17

18 Input and Output Devices for getting data into and out of computer memory Each device has its own interface, usually a set of registers like the memory s MAR and MDR Keyboard (input) and console (output) INPUT Keyboard Mouse Scanner Disk OUTPUT Monitor Printer LED Disk keyboard: data register (KBDR) and status register (KBSR) console: data register (CRTDR) and status register (CRTSR) frame buffer: memory-mapped pixels Some devices provide both input and output disk, network Program that controls access to a device is usually called a driver. 18

19 Control Unit (Finite State Machine) Orchestrates execution of the program CONTROL UNIT PC IR Instruction Register (IR) contains the current instruction. Program Counter (PC) contains the address of the next instruction to be executed. Control unit: reads an instruction from memory» the instruction s address is in the PC interprets the instruction, generating signals that tell the other components what to do» an instruction may take many machine cycles to complete 19

20 Instruction Processing Fetch instruction from memory Decode instruction Evaluate address Fetch operands from memory Execute operation Store result 20

21 Driving Force: The Clock The clock is a signal that keeps the control unit moving. At each clock tick, control unit moves to the next machine cycle -- may be next instruction or next phase of current instruction. Clock generator circuit: Based on crystal oscillator Generates regular sequence of 0 and 1 logic levels Clock cycle (or machine cycle) -- rising edge to rising edge 1 0 Machine time Cycle 21

22 Summary -- Von Neumann Model MEMORY MAR MDR INPUT Keyboard Mouse Scanner Disk PROCESSING UNIT ALU TEMP OUTPUT Monitor Printer LED Disk CONTROL UNIT PC IR 22

23 Turing Machine

24 Alan Turing 24

25 Modern Computers Von Neumann Machine implement a universal Turing machine and have a sequential architecture Most computers are based on John Von Neumann architecture and on 1936 Turing architecture 25

26 NEUROMORPHIC COMPUTING 26

27 Why Neuromorphic Computing? 27

28 Brain The Most Efficient Computing Machine 28

29 Biological Neural Systems

30 Artificial Neural Network Each neuron can perform non-linear operations. The algorithm is designed to mimic the behavior of the biological neural network. Currently, the algorithm is running on a normal PC. New parallel computing chips can help to improve the learning process. Neurosynaptic chips/brain-inspired chips The hardware design also mimics the biology brain Deep learning is also based on neural network 30

31 Artificial Neural Network We require exquisite numerical precision over many logical steps to achieve what brains accomplish in very few short steps. - John von Neumann A neural network is a massively parallel distributed processor made up of simple processing unit, which has a natural propensity for storing experiential knowledge and making it available for use. 31

32 Neurosynaptic System n 32

33 Neuromophic System 33

34 Comparison with Conventional Chips Architecture Conventional Computer Brain Inspired Computer Architecture Von Neumann Neural Network Computing unit CPU Synaptic Chip (e.g. TrueNorth) Storing unit Memory Synaptic Chip (e.g. TrueNorth) Computing Serial (multiple cores) Massively Parallel Communication CPU <-> Memory Neurons <-> Neurons Advantage Processing (Logical, Analytical) Learning (Pattern Recognition) Von Neumann bottleneck 34

35 Comparison with Conventional Chips: Architecture Processing and Storage are separated in CPU. CPU is built for a linear process to handle linear sequence of events. Synaptic chip integrates processing with storage. Synaptic chip process the information in a massively parallel fashion. Each neuron is able to process a piece of information and store it locally. Synapses helps with data communication between neurons. Synapses decides the connectivity between neurons and thus be able to rewire them. 35

36 Comparison with Conventional Chips Example: Converting the color image (480x360x3) to gray image Gray value = (red + green + blue)/3; CPU: 480x360 = iterations of linear processing. Synaptic chips, with 480x360x3 input neurons. 480x360 output neurons, For each output neurons, compute the gray value. One iteration of parallel processing CPU is good at linear processing to make sure the logic sequence is correct. Synaptic chip is good at massively parallel processing the image data. Image processing Pattern recognition Network simulation 36

37 Comparison with Conventional Chips Complexity 37

38 Comparison with Conventional Chips: Power Efficiency > 1000 times as efficient as chips made with the conventional architecture. Conventional Chips TrueNorth 50~100 w/(cm*cm) 0.02 w/(cm*cm) In 2012, Sequoia IBM conventional supercomputer simulating brain using 500 billion neurons and 100 trillion synapses, running at 1/1500 of brain speed, requires 12 GW of power. Each TrueNorth consumes 0.07w (Average 63mw, Maximum 72mw). The same simulation requires 27.3~35 kw. Science 8 August 2014: 345 (6197),

39 Comparison with Conventional Chips The efficiency of conventional computers is limited because they store data and program instructions in a block of memory that s separate from the processor that carries out instructions. As the processor works through its instructions in a linear sequence, it has to constantly shuttle information back and forth from the memory store a bottleneck that slows things down and wastes energy. While synaptic chips work parallelly, and the information can be stored in numerous synaptic chips. The integration of processing and storing avoids data shuttling and makes computing more energy efficient. About 176,000 times more efficient than a modern CPU running the same brain-like workload. million-neurons-5-4-billion-transistors 39

40 Comparison with Conventional Chips Power Efficiency 40

41 Comparison with Conventional Chips Denser Package Denser package TrueNorth size is 4.3 cm^2 In order to achieve the same computational performance of Sequoia IBM conventional supercomputer, it requires 400K~500K TrueNorth chips. The size will be about 172~215 m^2. Sequoia supercomputer Synaptic chip wall petaflops-by

42 Comparison with Conventional Chips Faster Speed Faster Speed Multi-object detection and classification with 400-pixel-by-240-pixel threecolor video input at 30 frames per second. more than 160 million spikes per second (5.44 Gbits/sec) TrueNorth vs Intel Core i7 CPU 950 with 4 cores and 8 threads, clocked at 3.07GHz (45nm process, 2009) DC1 42

43 Comparison with Conventional Chips Commercial Availability Hardware CPU Synaptic Chip Dominant Design Intel, AMD No (TrueNorth and NPU are prototypes) Quantity 1 (Generally) ~50K (for Human-brain scale, but growing) Breakthrough Intel 4004 in 1971 IBM TrueNorth in 2014 (not on market) Manufacturing Transistor process Transistor process (45nm, 28nm) Software CPU Synaptic Chip Language C,C++,Java, etc IBM Corelet Language Operating System Windows, ios, Linux New operating system Application Office, Game, etc New application (Corelet Library) Algorithm General (include learning) Learning Algorithm Compiler Available New compiler Debugger Available New debugger Amir, Arnon, et al. "Cognitive computing programming paradigm: a corelet language for composing networks of neurosynaptic cores." Neural Networks (IJCNN), The 2013 International Joint Conference on. IEEE,

44 Comparison with Conventional Chips Commercial Availability Current Status Switching Point Amir, Arnon, et al. "Cognitive computing programming paradigm: a corelet language for composing networks of neurosynaptic cores." Neural Networks (IJCNN), The 2013 International Joint Conference on. IEEE,

45 Comparison with Conventional Chips Qualcomm s zeroth chip (Neural Processing Unit) may be incorporated into the new smartphone. The Zeroth software is being developed to launch with Qualcomm s Snapdragon 820 processor, which will enter production later this year. The chip and the Zeroth software are also aimed at manufacturers of drones and robots. Zeroth_(software) cognitive-technologies/machine-learning 45

46 Performance Neuromorphic Systems Status Stanford Univesity Neurogrid (2009) HRL Neuorm orphic chip (2014) SpiNNake r HBP (2012) HiCANN HBP (2012) IBM TrueNort h (2014) Human Brain Neurons / Prototype 1.00E E E E E+10 Synapses / Prototype Power ConsumpJons (mw/cm^2) Manufacturing process (nm) 8.00E E E E E mw/cm

47 Performance Neuromorphic Systems Status 47

48 Performance of IBM Cognitive Chip Defense Advanced Research Projects Agency (DARPA) SyNAPSE(Systems of Neuromorphic Adaptive Plastic Scalabe Electronics) Brain-inspired computer architecture, event-driven Basical Structure Prototype of IBM cognitive computer

49 Performance of IBM Cognitive Chip Rate of Improvement of IBM TrueNorth Prototype Year Human Brain Neurons 1.00E E E E E+10 Synapses 4.00E E E E+14 Power Consumptions (W) 5.45E

50 Performance of IBM Cognitive Chip CAGR=1160% CAGR=531% CAGR=-172% The compound annual growth rate (CAGR) is the mean annual growth rate of an investment over a specified period of time longer than one year. 50

51 Artificial Neural Network ANN: To simulate the biological brain with nonlinear, dynamic, statistical mathematic model. Blue Brain Project EPFL IBM BlueGene L/P supercomputer Open source simulation software NEURON Blue Brain Project Cortical column (2006) Rat cortical column (2007) Equivalent honey bee brain (2012) Rat brain neocortical (2014) Full human brain (2023) Neurons E E E

52 Artificial Neural Network CAGR=160%

53 Cost Analysis According to the Moore's Law, we can predicte the number of transistors in one chip in the future number of transistors per chip year number 5.40E E E E E E E+11 53

54 Cost Analysis According to the price we assumed previously, we can get the following result: year cost

55 Cost Analysis According to the table below,we can calculate the interval number of chips: Rate of Improvement of IBM TrueNorth Prototype Year Human Brain Neurons 1.00E E E E E+10 Synapses 4.00E E E E+14 Power ConsumpJons (W) 5.45E

56 Cost Analysis The number of chips for one artificial brain year low high low high the number of chips year

57 Cost Analysis Total cost for one artificial brain ($) year low 1.82E high 7.29E low hig h 10 6 total cost ($) 10 5 CAGR=-789% 10 4 CAGR=-253% year 57

58 Application 58

59 Applications Object detection solar-powered leaf detect changes in the environment send out environmental and forest fire alerts. Roller robot l search-and-rescue robots l has 32 video cameras l beam back data from hazardous environments. 59

60 Application Vision assistance for the blind Emulating the visual cortex, low-power, light-weight eye glasses designed to help the visually impaired could be outfitted with multiple video and auditory sensors that capture and analyze this optical flow of data. Image Processing 60

61 Application Vision assistance Synesthetic feedback Surround sound is used to indicate the location of point of interest and provide an audible guidance through the pathway. Visual cues For users with residual sight, point of interest or obstacles can be highlighted by displaying either overlapping symbols or braille keywords. 61

62 Hybrid von Neumann & Neuromophic Architecture with Photonics Interconnect and 3D Stack Chips/Memristor 62

63 Videos and Info from IBM IBM DoE Neuromophic computing workshop IEEE Rebooting Computing Others (link from this site): 63

64 QUANTUM COMPUTING 64

65 Deterministic Binary Logic 0 and 1 Two states High and low voltage Easy to implement 65

66 Quantum Computing A quantum computer is a machine that performs calculations based on the laws of quantum mechanics, which is the behavior of particles at the sub-atomic level. 66

67 Introduction Quantum Mechanics Why? Moore s law (particles become smaller toward atom/ sub-atom) Study of matter at atomic level (The power of atoms) Classical physics laws do not apply Superposition Simultaneously possess two or more values Entanglement Quantum states of two atoms correlated even though spatially separated!!! Albert Einstein baffled spooky action at a distance 67

68 Superposition Simultaneously possess two or more values Schrodinger cat

69 Entanglement Quantum states of two atoms correlated even though spatially separated!!! Acting on a particle here can instantly influence a particle far away, something that is often described as theoretical teleportation. Albert Einstein baffled spooky action at a distance He could not understand ;-) Examples: Sending each of a pair of shoes to two places When one know whether hers is left or right, she knows the other one

70 Feynman to create quantum machine I think I can safely say that nobody understands quantum mechanics Feynman Feynman proposed the idea of creating machines based on the laws of quantum mechanics instead of the laws of classical physics David Deutsch developed the quantum turing machine, showing that quantum circuits are universal Peter Shor came up with a quantum algorithm to factor very large numbers in polynomial time Lov Grover develops a quantum search algorithm with O( N) complexity 70

71 Most Recent Development Two breakthroughs in Isaac Chuang (now an MIT professor, but then working at IBM's Almaden Research Center) used five fluorine atoms to make a crude, five-qubit quantum computer. Researchers at Los Alamos National Laboratory figured out how to make a seven-qubit machine using a drop of liquid. 2005, researchers at the University of Innsbruck added an extra qubit and produced the first quantum computer that could manipulate a qubyte (eight qubits). 2011, a pioneering Canadian company called D-Wave Systems announced in Nature that it had produced a 128-qubit machine. March 2015, the Google team announced they were "a step closer to quantum computation," having developed a new way for qubits to detect and protect against errors. Quantum computing from IBM 71

72 Representation of Data - Qubits A bit of data is represented by a single atom that is in one of two states denoted by 0> and 1>. A single bit of this form is known as a qubit A physical implementation of a qubit could use the two energy levels of an atom. An excited state representing 1> and a ground state representing 0>. Excited State Light pulse of frequency λ for time interval t Ground State Nucleu s Electron State 0> State 1> 72

73 Qubits A single qubit can be forced into a superposition of the two states denoted by the addition of the state vectors A qubit in superposition is in BOTH of the states 1> and 0 at the same time To be or not to be. That is the question William Shakespeare The classic answers: to be or not to be The quantum answers: to be or not to be or a x (to be) + b x (not to be) 73

74 Data Retrieval α represents the probability of the superposition collapsing to 0>. The α s are called probability amplitudes. In a balanced superposition, α = 1/ 2 where n is the number of qubits. If we attempt to retrieve the values represented within a superposition, the superposition randomly collapses to represent just one of the original values. 74

75 Qubits in Quantum Computation Qubit - can be 1, 0 or both 1 and 0 Ψ> - number in Quantum Computer Superposition of states of N qubits: N 2 1 i= 0 a = 1 Where: i s i N 2 1 a i i=

76 Examples

77 Representation of Data - Superposition Light pulse of frequency λ for time interval t/2 State 0> State 0> + 1> Consider a 3 bit qubit register. An equally weighted superposition of all possible states would be denoted by: ψ> = 000> + 001> >

78 Relationships among data - Entanglement Entanglement is the ability of quantum systems to exhibit correlations between states within a superposition. Imagine two qubits, each in the state 0> + 1> (a superposition of the 0 and 1.) We can entangle the two qubits such that the measurement of one qubit is always correlated to the measurement of the other qubit. Used for quantum communication, such as quantum teleportation

79 Quantum Computation Prime factorization (Cryptography) Peter Shor s algorithm Hard classical computation becomes easy quantum computation Factor n bit integer in O(n 3 ) Search an unordered list Lov Grover s algorithm Hard classical computation becomes less hard quantum computation n elements in n 1/2 queries 79

80 Advantages over Classical computers Encode more information Powerful Massively parallel Easily crack secret codes Fast in searching databases Hard computational problems become tractable NP to polynomial 80

81 Defense Cryptography Applications Accurate weather forecasts Efficient search Teleportation Unimaginable 81

82 Information IBM D-Wave Google s Quantum Dream Machine Others 82

83 QUANTUM GATES 83

84 Operations on Qubits - Reversible Logic Due to the nature of quantum physics, the destruction of information in a gate will cause heat to be evolved which can destroy the superposition of qubits. A B Ex. The AND Gate C Input Output A B C In these 3 cases, information is being destroyed This type of gate cannot be used. We must use Quantum Gates. 84

85 Quantum Gates Quantum Gates are similar to classical gates, but do not have a degenerate output. i.e. their original input state can be derived from their output state, uniquely. They must be reversible. This means that a deterministic computation can be performed on a quantum computer only if it is reversible. Luckily, it has been shown that any deterministic computation can be made reversible. (Charles Bennet, 1973) 85

86 Quantum Gates - Hadamard Simplest gate involves one qubit and is called a Hadamard Gate (also known as a square-root of NOT gate.) Used to put qubits into superposition. H H State 0> State 0> + 1> State 1> Note: Two Hadamard gates used in succession can be used as a NOT gate 86

87 Quantum Gates - Controlled NOT A gate which operates on two qubits is called a Controlled-NOT (CN) Gate. If the bit on the control line is 1, invert the bit on the target line. A - Target B - Control A B Input Output A B A B Note: The CN gate has a similar behavior to the XOR gate with some extra information to make it reversible. 87

88 Example Operation - Multiplication By 2 We can build a reversible logic circuit to calculate multiplication by 2 using CN gates arranged in the following manner: Carry Bit Input Ones Bit Carry Bit Output Ones Bit Carry Bit H Ones Bit 88

89 Quantum Gates - Controlled Controlled NOT (CCN) A gate which operates on three qubits is called a Controlled Controlled NOT (CCN) Gate. Iff the bits on both of the control lines is 1,then the target bit is inverted. Input Output A - Target B - Control 1 C - Control 2 A B C A B C A B C

90 A Universal Quantum Computer The CCN gate has been shown to be a universal reversible logic gate as it can be used as a NAND gate. A - Target B - Control 1 C - Control 2 When our target input is 1, our target output is a result of a NAND of B and C. A B C Input Output A B C A B C

91 Shor s Algorithm Shor s algorithm shows (in principle,) that a quantum computer is capable of factoring very large numbers in polynomial time. The algorithm is dependant on Modular Arithmetic Quantum Parallelism Quantum Fourier Transform 91

92 Timeline A research team in Japan demonstrated the first solid state device needed to construct a viable quantum computer First working 7-qubit NMR computer demonstrated at IBM s Almaden Research Center. First execution of Shor s algorithm First working 5-qubit NMR computer demonstrated at IBM's Almaden Research Center. First execution of order finding (part of Shor's algorithm) First working 3-qubit NMR computer demonstrated at IBM's Almaden Research Center. First execution of Grover's algorithm First working 2-qubit NMR computer demonstrated at University of California Berkeley MIT published the first papers on quantum computers based on spin resonance & thermal ensembles Lov Grover at Bell Labs invented the quantum database search algorithm Shor proposed the first scheme for quantum error correction 92