ICTP Latin-American Advanced Course on FPGADesign for Scientific Instrumentation. 19 November - 17 December, 2012.
|
|
- Herbert Griffin
- 5 years ago
- Views:
Transcription
1 ICTP Ltin-Americn Advnced Coure on FPGADeign for Scientific Intrumenttion 19 Novemer - 17 Decemer, 2012 Digitl Deign BAZARGAN SABET Pirouz Univerite Pierre Et Mrie Curie (Vi) Lip6, Deprtement Aim 4. Plce Juieu Pri Cedex 05 FRANCE
2 Outline Digitl CMOS deign Boolen lger Bic digitl CMOS gte Comintionl nd equentil circuit Coding - Repreenttion of numer Pirouz Bzrgn Set ICTP Octoer 2009
3 Bic CMOS Gte How to implement Boolen function in CMOS technology? Which functionlitie re ville Pirouz Bzrgn Set ICTP Octoer 2009
4 Bic CMOS Gte N-MOS trnitor G D D G S S W Si N+ L N+ P- Pirouz Bzrgn Set ICTP Octoer 2009
5 Bic CMOS Gte P-MOS trnitor G S D G S D Si P+ N- P+ P- Pirouz Bzrgn Set ICTP Octoer 2009
6 Bic CMOS Gte In digitl circuit MOS trnitor cn e een Switch G N-MOS P-MOS D D S S G G G S S D D D = S when G = 1 D = S when G = 0 Pirouz Bzrgn Set ICTP Octoer 2009
7 Bic CMOS Gte When driving, MOS trnitor cn e een Reitor Conductnce W L For the me ize, P-MOS i twice more reitive thn n N-MOS Pirouz Bzrgn Set ICTP Octoer 2009
8 Bic CMOS Gte The N-MOS nd P-MOS re not exctly ymmetricl A N-MOS i good trnmitter of 0 A P-MOS i good trnmitter of 1 Pirouz Bzrgn Set ICTP Octoer 2009
9 Bic CMOS Gte y = Notx S G D D 2W/L y Dul CMOS gte x G S W/L x y Pirouz Bzrgn Set ICTP Octoer 2009
10 Bic CMOS Gte y = x 1.x 2 y x 1 x 2 x 2 x 1 y Pirouz Bzrgn Set ICTP Octoer 2009
11 Bic CMOS Gte Deign of dul gte P network The P-network mut e the dul of the N-network x i y Serie Prllel Prllel Serie N network Tke cre of the ize of trnitor Pirouz Bzrgn Set ICTP Octoer 2009
12 Bic CMOS Gte To et the output to 0 pth h to e creted through the N network A erie of N-trnitor mut e conducting Πx i = 1 P network x i N network y Only negtive (inverting) function cn e creted Pirouz Bzrgn Set ICTP Octoer 2009
13 Bic CMOS Gte Implementing Boolen function with CMOS gte? The function mut e inverting in regrd of ll the vrile Put the function in the form of f = g Deign the N-network of g Pirouz Bzrgn Set ICTP Octoer 2009
14 Bic CMOS Gte Implementing Boolen function with CMOS gte? In the expreion of g ech. re two pth in erie In the expreion of g ech + re two pth in prllel The P-network i the dul network of the N-network Avoid putting more thn 3 trnitor in erie Pirouz Bzrgn Set ICTP Octoer 2009
15 Bic CMOS Gte Exmple : f = + (.c) 2W/L c f = + (+c) f =. (+c) g =. (+c) W/L W/L 2W/L W/L c f W/L Pirouz Bzrgn Set ICTP Octoer 2009
16 Bic CMOS Gte Some gte : Inverter : f = 4 W/L Nnd : f =. 4 W/L Nor : f = + y W/L W/L Pirouz Bzrgn Set ICTP Octoer 2009
17 Bic CMOS Gte Some gte : Multiplexer : f =. +. y Pirouz Bzrgn Set ICTP Octoer 2009
18 Bic CMOS Gte Some gte : Multiplexer : f = c d c d Pirouz Bzrgn Set ICTP Octoer 2009
19 Bic CMOS Gte Some gte : Multiplexer : f =. +. Pirouz Bzrgn Set ICTP Octoer 2009
20 Bic CMOS Gte Pirouz Bzrgn Set ICTP Octoer 2009
21 Bic CMOS Gte If = 1 If = 0 f = f i not defined f f Tri-tte driver Pirouz Bzrgn Set ICTP Octoer 2009
22 Bic CMOS Gte Some gte : Multiplexer : f Pirouz Bzrgn Set ICTP Octoer 2009
23 Bic CMOS Gte Some gte : Multiplexer : c d f Pirouz Bzrgn Set ICTP Octoer 2009
24 Bic CMOS Gte Some gte : If = 1 If = 0 f f = f i not defined If = 0 then f = 0 If = 1 then f = 1 - P-trnitor Pirouz Bzrgn Set ICTP Octoer 2009
25 Bic CMOS Gte Some gte : If = 0 If = 1 f f = f i not defined If = 1 then f = 1 If = 0 then f = 0 + P-trnitor Pirouz Bzrgn Set ICTP Octoer 2009
26 Bic CMOS Gte Some gte : If = 1 If = 0 f f = f i not defined If = 0 then f = 0 If = 1 then f = 1 CMOS Switch Pirouz Bzrgn Set ICTP Octoer 2009
27 Bic CMOS Gte Some gte : Multiplexer : f =. +. f Pirouz Bzrgn Set ICTP Octoer 2009
28 Bic CMOS Gte Some gte : Multiplexer : f =. +. f Pirouz Bzrgn Set ICTP Octoer 2009
29 Bic CMOS Gte Some gte : Nxor : f =. +. y I need nd Pirouz Bzrgn Set ICTP Octoer 2009
30 Bic CMOS Gte Some gte : Nxor Xor with P-trnitor : f =. +. f f Pirouz Bzrgn Set ICTP Octoer 2009
CS12N: The Coming Revolution in Computer Architecture Laboratory 2 Preparation
CS2N: The Coming Revolution in Computer Architecture Lortory 2 Preprtion Ojectives:. Understnd the principle of sttic CMOS gte circuits 2. Build simple logic gtes from MOS trnsistors 3. Evlute these gtes
More informationBoolean algebra.
http://en.wikipedi.org/wiki/elementry_boolen_lger Boolen lger www.tudorgir.com Computer science is not out computers, it is out computtion nd informtion. computtion informtion computer informtion Turing
More information1 2 : 4 5. Why Digital Systems? Lesson 1: Introduction to Digital Logic Design. Numbering systems. Sample Problems 1 5 min. Lesson 1-b: Logic Gates
Leon : Introduction to Digitl Logic Deign Computer ided Digitl Deign EE 39 meet Chvn Fll 29 Why Digitl Sytem? ccurte depending on numer of digit ued CD Muic i digitl Vinyl Record were nlog DVD Video nd
More informationexpression simply by forming an OR of the ANDs of all input variables for which the output is
2.4 Logic Minimiztion nd Krnugh Mps As we found ove, given truth tle, it is lwys possile to write down correct logic expression simply y forming n OR of the ANDs of ll input vriles for which the output
More informationElements of Computing Systems, Nisan & Schocken, MIT Press. Boolean Logic
Elements of Computing Systems, Nisn & Schocken, MIT Press www.idc.c.il/tecs Usge nd Copyright Notice: Boolen Logic Copyright 2005 Nom Nisn nd Shimon Schocken This presenttion contins lecture mterils tht
More informationChapter 1: Boolean Logic
Elements of Computing Systems, Nisn & Schocken, MIT Press, 2005 www.idc.c.il/tecs Chpter 1: Boolen Logic Usge nd Copyright Notice: Copyright 2005 Nom Nisn nd Shimon Schocken This presenttion contins lecture
More informationFast Boolean Algebra
Fst Boolen Alger ELEC 267 notes with the overurden removed A fst wy to lern enough to get the prel done honorly Printed; 3//5 Slide Modified; Jnury 3, 25 John Knight Digitl Circuits p. Fst Boolen Alger
More informationBoolean Logic. Building a Modern Computer From First Principles.
Boolen Logic Building Modern Computer From First Principles www.nnd2tetris.org Elements of Computing Systems, Nisn & Schocken, MIT Press, www.nnd2tetris.org, Chpter 1: Boolen Logic slide 1 Usge nd Copyright
More informationOverview of Today s Lecture:
CPS 4 Computer Orgniztion nd Progrmming Lecture : Boolen Alger & gtes. Roert Wgner CPS4 BA. RW Fll 2 Overview of Tody s Lecture: Truth tles, Boolen functions, Gtes nd Circuits Krnugh mps for simplifying
More informationUnit 4. Combinational Circuits
Unit 4. Comintionl Ciruits Digitl Eletroni Ciruits (Ciruitos Eletrónios Digitles) E.T.S.I. Informáti Universidd de Sevill 5/10/2012 Jorge Jun 2010, 2011, 2012 You re free to opy, distriute
More informationCombinational Logic. Precedence. Quick Quiz 25/9/12. Schematics à Boolean Expression. 3 Representations of Logic Functions. Dr. Hayden So.
5/9/ Comintionl Logic ENGG05 st Semester, 0 Dr. Hyden So Representtions of Logic Functions Recll tht ny complex logic function cn e expressed in wys: Truth Tle, Boolen Expression, Schemtics Only Truth
More informationECE223. R eouven Elbaz Office room: DC3576
ECE223 R eouven Elz reouven@uwterloo.c Office room: DC3576 Outline Decoders Decoders with Enle VHDL Exmple Multiplexers Multiplexers with Enle VHDL Exmple From Decoder to Multiplexer 3-stte Gtes Multiplexers
More informationBoolean Algebra. Boolean Algebra
Boolen Alger Boolen Alger A Boolen lger is set B of vlues together with: - two inry opertions, commonly denoted y + nd, - unry opertion, usully denoted y ˉ or ~ or, - two elements usully clled zero nd
More informationIntroduction to Electrical & Electronic Engineering ENGG1203
Introduction to Electricl & Electronic Engineering ENGG23 2 nd Semester, 27-8 Dr. Hden Kwok-H So Deprtment of Electricl nd Electronic Engineering Astrction DIGITAL LOGIC 2 Digitl Astrction n Astrct ll
More informationName: Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 205 Midterm Wednesday, November 4 Point values
More informationControl with binary code. William Sandqvist
Control with binry code Dec Bin He Oct 218 10 11011010 2 DA 16 332 8 E 1.1c Deciml to Binäry binry weights: 1024 512 256 128 64 32 16 8 4 2 1 71 10? 2 E 1.1c Deciml to Binäry binry weights: 1024 512 256
More informationELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Fall Notes - Unit 1
INTRODUTION TO LOGI IRUITS Notes - Unit 1 OOLEN LGER This is the oundtion or designing nd nlyzing digitl systems. It dels with the cse where vriles ssume only one o two vlues: TRUE (usully represented
More informationLecture 3. Introduction digital logic. Notes. Notes. Notes. Representations. February Bern University of Applied Sciences.
Lecture 3 Ferury 6 ern University of pplied ciences ev. f57fc 3. We hve seen tht circuit cn hve multiple (n) inputs, e.g.,, C, We hve lso seen tht circuit cn hve multiple (m) outputs, e.g. X, Y,, ; or
More informationELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter Notes - Unit 1
ELETRIL ND OMPUTER ENGINEERING DEPRTMENT, OKLND UNIVERSIT EE-78: omputer Hrdwre Design Winter 016 INTRODUTION TO LOGI IRUITS Notes - Unit 1 OOLEN LGER This is the oundtion or designing nd nlyzing digitl
More informationFault Modeling. EE5375 ADD II Prof. MacDonald
Fult Modeling EE5375 ADD II Prof. McDonld Stuck At Fult Models l Modeling of physicl defects (fults) simplify to logicl fult l stuck high or low represents mny physicl defects esy to simulte technology
More informationFinite Field Arithmetic and Implementations. Xinmiao Zhang Case Western Reserve University
Finite Field Arithmetic nd Implementtions Xinmio Zhng Cse Western Reserve University Applictions of Finite Field Arithmetic Error-correcting codes Hmming codes BCH codes Reed-Solomon codes Low-density
More informationUnified Hardware Architecture for 128-bit Block Ciphers AES and Camellia. A. Satoh and S. Morioka Tokyo Research Laboratory IBM Japan Ltd.
Unified Hrdwre Architecture for -bit Block Ciphers AS nd Cmelli A. Stoh nd S. Moriok Toko Reserch Lbortor IBM Jpn Ltd. Contents Unified S-Bo Unified Permuttion Ler Unified Dt Pth Architecture ASIC Implementtion
More informationIST 4 Information and Logic
IST 4 Informtion nd Logic T = tody x= hw#x out x= hw#x due mon tue wed thr 28 M1 oh 1 4 oh M1 11 oh oh 1 2 M2 18 oh oh 2 fri oh oh = office hours oh 25 oh M2 2 3 oh midterms oh Mx= MQx out 9 oh 3 T 4 oh
More informationDigital electronic systems are designed to process voltage signals which change quickly between two levels. Low time.
DIGITL ELECTRONIC SYSTEMS Digital electronic systems are designed to process voltage signals which change quickly between two levels. High Voltage Low time Fig. 1 digital signal LOGIC GTES The TTL digital
More informationIST 4 Information and Logic
IST 4 Informtion nd Logic mon tue wed thr fri sun T = tody 3 M1 oh 1 x= hw#x out 10 oh M1 17 oh oh 1 2 M2 oh oh x= hw#x due 24 oh oh 2 oh = office hours oh 1 oh M2 8 3 oh midterms oh oh Mx= MQx out 15
More informationECE 342 Electronic Circuits. Lecture 34 CMOS Logic
ECE 34 Electronic Circuits Lecture 34 CMOS Logic Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 De Morgan s Law Digital Logic - Generalization ABC... ABC...
More informationDigital Control of Electric Drives
igitl Control o Electric rives Logic Circuits - Comintionl Boolen Alger, escription Form Czech Technicl University in Prgue Fculty o Electricl Engineering Ver.. J. Zdenek Logic Comintionl Circuit Logic
More informationAnswers. Name: Grade: Q1 Q2 Q3 Q4 Total mean: 83, stdev: 14. ESE370 Fall 2017
University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2017 Midterm 2 Monday, November 6 Point values
More information6.004 Computation Structures Spring 2009
MIT OpenCourseWre http://ocw.mit.edu 6.004 Computtion Structures Spring 009 For informtion out citing these mterils or our Terms of Use, visit: http://ocw.mit.edu/terms. Cost/Performnce Trdeoffs: cse study
More informationPhysics Lecture 14: MON 29 SEP
Physics 2113 Physics 2113 Lecture 14: MON 29 SEP CH25: Cpcitnce Von Kleist ws le to store electricity in the jr. Unknowingly, he h ctully invente novel evice to store potentil ifference. The wter in the
More informationLecture 6. Notes. Notes. Notes. Representations Z A B and A B R. BTE Electronics Fundamentals August Bern University of Applied Sciences
Lecture 6 epresenttions epresenttions TE52 - Electronics Fundmentls ugust 24 ern University of pplied ciences ev. c2d5c88 6. Integers () sign-nd-mgnitude representtion The set of integers contins the Nturl
More informationCHAPTER 3 LOGIC GATES & BOOLEAN ALGEBRA
CHPTER 3 LOGIC GTES & OOLEN LGER C H P T E R O U T C O M E S Upon completion of this chapter, student should be able to: 1. Describe the basic logic gates operation 2. Construct the truth table for basic
More informationLOGIC GATES (PRACTICE PROBLEMS)
LOGIC GTES (PRCTICE PROLEMS) Key points and summary First set of problems from Q. Nos. 1 to 9 are based on the logic gates like ND, OR, NOT, NND & NOR etc. First four problems are basic in nature. Problems
More informationEE C245 ME C218 Introduction to MEMS Design
EE C45 ME C8 Introduction to MEMS Deign Fall 007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Science Univerity of California at Berkeley Berkeley, CA 9470 Lecture 5: Output t Sening
More informationSolutions Problem Set 2. Problem (a) Let M denote the DFA constructed by swapping the accept and non-accepting state in M.
Solution Prolem Set 2 Prolem.4 () Let M denote the DFA contructed y wpping the ccept nd non-ccepting tte in M. For ny tring w B, w will e ccepted y M, tht i, fter conuming the tring w, M will e in n ccepting
More informationNetwork Analysis and Synthesis. Chapter 5 Two port networks
Network Anlsis nd Snthesis hpter 5 Two port networks . ntroduction A one port network is completel specified when the voltge current reltionship t the terminls of the port is given. A generl two port on
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More informationLogic Gates and Boolean Algebra
Logic Gates and oolean lgebra The ridge etween Symbolic Logic nd Electronic Digital Computing Compiled y: Muzammil hmad Khan mukhan@ssuet.edu.pk asic Logic Functions and or nand nor xor xnor not 2 Logic
More informationCOMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos Combinational vs. Sequential Logic In Logic
More informationSection 6.1 INTRO to LAPLACE TRANSFORMS
Section 6. INTRO to LAPLACE TRANSFORMS Key terms: Improper Integrl; diverge, converge A A f(t)dt lim f(t)dt Piecewise Continuous Function; jump discontinuity Function of Exponentil Order Lplce Trnsform
More informationBoolean Algebra. Boolean Algebras
Boolen Algebr Boolen Algebrs A Boolen lgebr is set B of vlues together with: - two binry opertions, commonly denoted by + nd, - unry opertion, usully denoted by or ~ or, - two elements usully clled zero
More informationITTC Introduction to Digital Logic Design The University of Kansas EECS 140 / 141 Summary
Introduction to Digital Logic Design The University o Kansas EECS 140 / 141 Summary James P.G. Sterbenz Department o Electrical Engineering & Computer Science Inormation Technology & Telecommunications
More informationEE273 Lecture 15 Asynchronous Design November 16, Today s Assignment
EE273 Lecture 15 Asynchronous Design Novemer 16, 199 Willim J. Dlly Computer Systems Lortory Stnford University illd@csl.stnford.edu 1 Tody s Assignment Term Project see project updte hndout on we checkpoint
More informationLecture 9: LTL and Büchi Automata
Lecture 9: LTL nd Büchi Automt 1 LTL Property Ptterns Quite often the requirements of system follow some simple ptterns. Sometimes we wnt to specify tht property should only hold in certin context, clled
More informationDigital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits.
CS211 Computer Architecture Digital Logic l Topics l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Figures & Tables borrowed from:! http://www.allaboutcircuits.com/vol_4/index.html!
More informationGood Review book ( ) ( ) ( )
7/31/2011 34 Boolen (Switching) Algebr Review Good Review book BeBop to the Boolen Boogie: An Unconventionl Guide to Electronics, 2 nd ed. by Clive Mxwell Hightext Publictions Inc. from Amzon.com for pprox.
More informationDIRECT CURRENT CIRCUITS
DRECT CURRENT CUTS ELECTRC POWER Consider the circuit shown in the Figure where bttery is connected to resistor R. A positive chrge dq will gin potentil energy s it moves from point to point b through
More informationLecture 14: Circuit Families
Introduction to CMOS VLSI Design Lecture 4: Circuit Families David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Pseudo-nMOS Logic q Dynamic Logic q
More informationLecture 8: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 004 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates
More informationUNIT 5 QUADRATIC FUNCTIONS Lesson 3: Creating Quadratic Equations in Two or More Variables Instruction
Lesson 3: Creting Qudrtic Equtions in Two or More Vriles Prerequisite Skills This lesson requires the use of the following skill: solving equtions with degree of Introduction 1 The formul for finding the
More informationLecture 9: Combinational Circuit Design
Lecture 9: Combinational Circuit Design Outline Bubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates Skewed Gates Best P/N ratio 0: Combinational Circuits CMOS VLSI Design
More informationDesigning Information Devices and Systems I Discussion 8B
Lst Updted: 2018-10-17 19:40 1 EECS 16A Fll 2018 Designing Informtion Devices nd Systems I Discussion 8B 1. Why Bother With Thévenin Anywy? () Find Thévenin eqiuvlent for the circuit shown elow. 2kΩ 5V
More informationState space systems analysis (continued) Stability. A. Definitions A system is said to be Asymptotically Stable (AS) when it satisfies
Stte spce systems nlysis (continued) Stbility A. Definitions A system is sid to be Asymptoticlly Stble (AS) when it stisfies ut () = 0, t > 0 lim xt () 0. t A system is AS if nd only if the impulse response
More informationPractice 7: CMOS Capacitance
Practice 7: CMOS Capacitance Digital Electronic Circuits Semester A 2012 MOSFET Capacitances MOSFET Capacitance Components 3 Gate to Channel Capacitance In general, the gate capacitance is similar to a
More informationLecture 2 Review on Digital Logic (Part 1)
Lecture 2 Review on Digital Logic (Part 1) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ Grading Engagement 5% Review Quiz 10% Homework 10% Labs 40%
More informationDigital Fundamentals
Digital Fundamentals Tenth Edition Floyd hapter 5 Modified by Yuttapong Jiraraksopakun Floyd, Digital Fundamentals, 10 th 2008 Pearson Education ENE, KMUTT ed 2009 2009 Pearson Education, Upper Saddle
More informationHow do we solve these things, especially when they get complicated? How do we know when a system has a solution, and when is it unique?
XII. LINEAR ALGEBRA: SOLVING SYSTEMS OF EQUATIONS Tody we re going to tlk out solving systems of liner equtions. These re prolems tht give couple of equtions with couple of unknowns, like: 6= x + x 7=
More informationCS 310 (sec 20) - Winter Final Exam (solutions) SOLUTIONS
CS 310 (sec 20) - Winter 2003 - Finl Exm (solutions) SOLUTIONS 1. (Logic) Use truth tles to prove the following logicl equivlences: () p q (p p) (q q) () p q (p q) (p q) () p q p q p p q q (q q) (p p)
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design Prof. blj@eng.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay s CSE477 slides
More informationCMSC 313 Lecture 16 Postulates & Theorems of Boolean Algebra Semiconductors CMOS Logic Gates
CMSC 33 Lecture 6 Postulates & Theorems of oolean lgebra Semiconductors CMOS Logic Gates UMC, CMSC33, Richard Chang Last Time Overview of second half of this course Logic gates & symbols
More informationE40M. Binary Numbers. M. Horowitz, J. Plummer, R. Howe 1
E40M Binary Numbers M. Horowitz, J. Plummer, R. Howe 1 Reading Chapter 5 in the reader A&L 5.6 M. Horowitz, J. Plummer, R. Howe 2 Useless Box Lab Project #2 Adding a computer to the Useless Box alows us
More informationFloating Point Representation and Digital Logic. Lecture 11 CS301
Floating Point Representation and Digital Logic Lecture 11 CS301 Administrative Daily Review of today s lecture w Due tomorrow (10/4) at 8am Lab #3 due Friday (9/7) 1:29pm HW #5 assigned w Due Monday 10/8
More informationMath 154B Elementary Algebra-2 nd Half Spring 2015
Mth 154B Elementry Alger- nd Hlf Spring 015 Study Guide for Exm 4, Chpter 9 Exm 4 is scheduled for Thursdy, April rd. You my use " x 5" note crd (oth sides) nd scientific clcultor. You re expected to know
More informationTopics. CMOS Design Multi-input delay analysis. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics CMO Design Multi-input delay analysis pring 25 Transmission Gate OUT Z OUT Z pring 25 Transmission Gate OUT When is low, the output is at high impedance When is high, the output follows However,
More informationMiscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an N-Switch, the
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: Two-Input NOR Gate (NOR2)
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 14: March 1, 2016 Combination Logic: Ratioed and Pass Logic Lecture Outline! CMOS Gates Review " CMOS Worst Case Analysis! Ratioed Logic Gates!
More informationPASS-TRANSISTOR LOGIC. INEL Fall 2014
PASS-TRANSISTOR LOGIC INEL 4207 - Fall 2014 Figure 15.5 Conceptual pass-transistor logic gates. (a) Two switches, controlled by the input variables B and C, when connected in series in the path between
More informationBoole Algebra and Logic Series
S1 Teknik Telekomunikasi Fakultas Teknik Elektro oole lgebra and Logic Series 2016/2017 CLO1-Week2-asic Logic Operation and Logic Gate Outline Understand the basic theory of oolean Understand the basic
More informationLinear Inequalities. Work Sheet 1
Work Sheet 1 Liner Inequlities Rent--Hep, cr rentl compny,chrges $ 15 per week plus $ 0.0 per mile to rent one of their crs. Suppose you re limited y how much money you cn spend for the week : You cn spend
More informationENGR 3861 Digital Logic Boolean Algebra. Fall 2007
ENGR 386 Digitl Logi Boole Alger Fll 007 Boole Alger A two vlued lgeri system Iveted y George Boole i 854 Very similr to the lger tht you lredy kow Sme opertios ivolved dditio sutrtio multiplitio Repled
More informationImproper Integrals. The First Fundamental Theorem of Calculus, as we ve discussed in class, goes as follows:
Improper Integrls The First Fundmentl Theorem of Clculus, s we ve discussed in clss, goes s follows: If f is continuous on the intervl [, ] nd F is function for which F t = ft, then ftdt = F F. An integrl
More informationThings to Memorize: A Partial List. January 27, 2017
Things to Memorize: A Prtil List Jnury 27, 2017 Chpter 2 Vectors - Bsic Fcts A vector hs mgnitude (lso clled size/length/norm) nd direction. It does not hve fixed position, so the sme vector cn e moved
More information1 From NFA to regular expression
Note 1: How to convert DFA/NFA to regulr expression Version: 1.0 S/EE 374, Fll 2017 Septemer 11, 2017 In this note, we show tht ny DFA cn e converted into regulr expression. Our construction would work
More informationI1 = I2 I1 = I2 + I3 I1 + I2 = I3 + I4 I 3
2 The Prllel Circuit Electric Circuits: Figure 2- elow show ttery nd multiple resistors rrnged in prllel. Ech resistor receives portion of the current from the ttery sed on its resistnce. The split is
More informationVectors , (0,0). 5. A vector is commonly denoted by putting an arrow above its symbol, as in the picture above. Here are some 3-dimensional vectors:
Vectors 1-23-2018 I ll look t vectors from n lgeric point of view nd geometric point of view. Algericlly, vector is n ordered list of (usully) rel numers. Here re some 2-dimensionl vectors: (2, 3), ( )
More informationSection 3.1: Exponent Properties
Section.1: Exponent Properties Ojective: Simplify expressions using the properties of exponents. Prolems with exponents cn often e simplied using few sic exponent properties. Exponents represent repeted
More informationCS 330 Formal Methods and Models
CS 330 Forml Methods nd Models Dn Richrds, section 003, George Mson University, Fll 2017 Quiz Solutions Quiz 1, Propositionl Logic Dte: Septemer 7 1. Prove (p q) (p q), () (5pts) using truth tles. p q
More informationEE141. Administrative Stuff
-Spring 2004 Digital Integrated ircuits Lecture 15 Logical Effort Pass Transistor Logic 1 dministrative Stuff First (short) project to be launched next Th. Overall span: 1 week Hardware lab this week Hw
More informationIntermediate Math Circles Wednesday, November 14, 2018 Finite Automata II. Nickolas Rollick a b b. a b 4
Intermedite Mth Circles Wednesdy, Novemer 14, 2018 Finite Automt II Nickols Rollick nrollick@uwterloo.c Regulr Lnguges Lst time, we were introduced to the ide of DFA (deterministic finite utomton), one
More informationName Ima Sample ASU ID
Nme Im Smple ASU ID 2468024680 CSE 355 Test 1, Fll 2016 30 Septemer 2016, 8:35-9:25.m., LSA 191 Regrding of Midterms If you elieve tht your grde hs not een dded up correctly, return the entire pper to
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS
More informationn f(x i ) x. i=1 In section 4.2, we defined the definite integral of f from x = a to x = b as n f(x i ) x; f(x) dx = lim i=1
The Fundmentl Theorem of Clculus As we continue to study the re problem, let s think bck to wht we know bout computing res of regions enclosed by curves. If we wnt to find the re of the region below the
More informationLecture 8: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 00 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates
More informationDigital Circuits. 1. Inputs & Outputs are quantized at two levels. 2. Binary arithmetic, only digits are 0 & 1. Position indicates power of 2.
Digital Circuits 1. Inputs & Outputs are quantized at two levels. 2. inary arithmetic, only digits are 0 & 1. Position indicates power of 2. 11001 = 2 4 + 2 3 + 0 + 0 +2 0 16 + 8 + 0 + 0 + 1 = 25 Digital
More informationGates and Logic: From switches to Transistors, Logic Gates and Logic Circuits
Gates and Logic: From switches to Transistors, Logic Gates and Logic Circuits Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University See: P&H ppendix C.2 and C.3 (lso, see C.0 and
More informationConverting Regular Expressions to Discrete Finite Automata: A Tutorial
Converting Regulr Expressions to Discrete Finite Automt: A Tutoril Dvid Christinsen 2013-01-03 This is tutoril on how to convert regulr expressions to nondeterministic finite utomt (NFA) nd how to convert
More information1. Twelve less than five times a number is thirty three. What is the number
Alger 00 Midterm Review Nme: Dte: Directions: For the following prolems, on SEPARATE PIECE OF PAPER; Define the unknown vrile Set up n eqution (Include sketch/chrt if necessr) Solve nd show work Answer
More informationAdditional Gates COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals
Additional Gates COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Additional Gates and Symbols Universality of NAND and NOR gates NAND-NAND
More information4. UNBALANCED 3 FAULTS
4. UNBALANCED AULTS So fr: we hve tudied lned fult ut unlned fult re more ommon. Need: to nlye unlned ytem. Could: nlye three-wire ytem V n V n V n Mot ommon fult type = ingle-phe to ground i.e. write
More informationLecture 8: Logic Effort and Combinational Circuit Design
Lecture 8: Logic Effort and Combinational Circuit Design Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q Logical Effort q Delay in a Logic Gate
More informationLecture 9: Digital Electronics
Introduction: We can classify the building blocks of a circuit or system as being either analog or digital in nature. If we focus on voltage as the circuit parameter of interest: nalog: The voltage can
More informationCMOS Digital Integrated Circuits Lec 10 Combinational CMOS Logic Circuits
Lec 10 Combinational CMOS Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic circuit Out In Combinational Logic circuit Out State Combinational The output is determined only by
More informationGUC (Dr. Hany Hammad) 9/19/2016
UC (Dr. Hny Hmmd) 9/9/6 ecture # ignl flw grph: Defitin. Rule f Reductin. Mn Rule. ignl-flw grph repreenttin f : ltge urce. ive gle-prt device. ignl Flw rph A ignl-flw grph i grphicl men f prtryg the reltinhip
More informationCMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411
More informationCPE/EE 427, CPE 527 VLSI Design I L18: Circuit Families. Outline
CPE/EE 47, CPE 57 VLI Design I L8: Circuit Families Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe57-05f
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational
More informationELE B7 Power System Engineering. Unbalanced Fault Analysis
Power System Engineering Unblnced Fult Anlysis Anlysis of Unblnced Systems Except for the blnced three-phse fult, fults result in n unblnced system. The most common types of fults re single lineground
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2018 Final Monday, Apr 0 5 Problems with point weightings shown.
More informationBridging the gap: GCSE AS Level
Bridging the gp: GCSE AS Level CONTENTS Chpter Removing rckets pge Chpter Liner equtions Chpter Simultneous equtions 8 Chpter Fctors 0 Chpter Chnge the suject of the formul Chpter 6 Solving qudrtic equtions
More information