Fundamentals of PLLs (I)

Transcription

1 Phae-Locked Loop Fundamenal of PLL (I) Chng-Yuan Yang Naonal Chung-Hng Unvery Deparmen of Elecrcal Engneerng

2 Why phae-lock? - Jer Supreon - Frequency Synhe T T Skew Reducon T + 2 T + 3 PLL fou = 900 ~ 925 MHz ( n 30 Khz ep ) CK CKc Mcro-proceor Dgal IC PLL CK CK CKc - Clock Recovery Experence Clock Skew Fber Recever CPU MEM I/O Daa Recovered clock 1-1 Chng-Yuan Yang / EE, NCHU

3 Hory of PLL Fr PLL: 1932 by de Belleze, Coheren communcaon Fr PLL IC: 1965, purely analog (Lnear PLL) Fr Dgal PLL: around 1970 (ung Dgal Phae Deecor) All Dgal PLL: Dgal Fler, NCO (Numercally Conrolled Ocllaor), Sofware PLL: Ung DSP 1990: Mo of he PLL Charge Pump PLL 1-2 Chng-Yuan Yang / EE, NCHU

4 Wha PLL? Reference gnal x() Phae Deecor Loop Fler Synchronzed Ocllaor y() Synchronzed gnal Operae on exce phae of x() and y(). Feedback yem wh PD a an error amplfer. Locked when phae dfference beween npu and oupu conan wh me. 1-3 Chng-Yuan Yang / EE, NCHU

5 Termnology Lockng When VCO oupu n phae a well a n frequency wh he reference npu gnal Lock Range Inpu frequency range over whch he loop can manan lockng Capure Range Inpu frequency range ono whch he loop can lock Free Runnng Frequency VCO runnng frequency when no npu appled Acquon Tme: Pull-n me + Selng me Tme requred for he PLL o lock elf on o he reference clock Phae Offe or Phae Error (Seady Sae) When PLL locked, he phae dfference beween npu and oupu 1-4 Chng-Yuan Yang / EE, NCHU

6 Bac feedback nework of PLL v () Vn[()] n() V v () Vco[()] co() V o o o o o o v ()()() K v v where K d m o m K VV n()co() m o o he ranfer conan [1/V] 1 KmVV o n()()() o o o o 2 () n()()() n()()() v K where K K VV c d o o d m o Kd n() e ()() e o [V/rad] 1-5 Chng-Yuan Yang / EE, NCHU

7 v c () change he free runnng frequency c of he VCO. ()() K v where K degnaed a he ocllaor gan [2Hz/V]. ()()() K v d d e() d o c o c o e c o c K K n() d c o d e K n() where and K K K. e o o d K ndcaed a he gan of he PLL [2Hz]. 1-6 Chng-Yuan Yang / EE, NCHU

8 Soluon n he cloed form d e() d K n() / K1 d e() d K n() e 2 1 K e 0 an an 2 2 () K K 4 2 e (A) Snce K, an() jx anh() j x, we have 0 K 1 () 2 2 1() /() Kan( / 4 K / 2) e ln 1() /() K an( / 4 K / 2) e K 1 exp()() K e 2an K exp()() K 2 0 For he eady ae, ha, for, he lh of eq. (A) equal zero wh he reul 1 e n K 1-7 Chng-Yuan Yang / EE, NCHU

9 Lnearzed oluon The me-dependen phae dfference e () a he oupu of he PD n he cloed PLL mall and prone o he mplfcaon n()() e e (Th aumpon uppored wh he realy ha a lo of PD are lnear or nearly lnear n he workng range.) d e() d K n() e d e() d K () e () e where he negraon conan for 0. K K K e e0 e0 The phae dfference n he eady ae: e K 1-8 Chng-Yuan Yang / EE, NCHU

10 Soluon n he frequency doman In he locked ae, = o and e << /2. o()()() c Kovc n[()()] o o c Kovc0 Kd Ko o o c Kovc0 () Kn[()()] Laplace ranform: o o ()()() e o ()()() K o o PLL ranfer funcon o () K H () () K ()()() o e 1() H ()() K fr order 1-9 Chng-Yuan Yang / EE, NCHU

11 Smplfed block dagram of PLL wh ndvdual ranfer funcon v () () () V ()() K d d e Ko Vc ()()() F Vd o()() Vc vo () () () o o PD: we ge a volage v d () proporonal o he phae dfference of he npu. v d () = [ () o ()]K d K d : he phae deecor gan [V/rad] Loop fler: a low-pa fler aenuang carrer wh frequence = o, and deally all undered deband. Noe ha he ueful gnal v c () a lowly varyng DC componen. VCO: v c () = v d () h f () h f (): he me repone of he loop fler c (): he VCO free-runnng frequency ()()() d K v d o o c o c K o : he VCO gan [2Hz/V] In mo cae, K d and K o are volage-dependen. nonlnear model n PLL I lnearzaon, jufed n mall-gnal cae ( eady ae workng mode), provde a good ngh no he problem Chng-Yuan Yang / EE, NCHU

12 Smplfed block dagram of PLL n a feedback pah Kd Ko F () d o () ()()()() o FM K K F o KF()() FM G() H () KF()() FM 1 1() G Forward loop gan K Kd Ko KF()() F Open loop gan G() M 1-11 Chng-Yuan Yang / EE, NCHU

13 Order of PLL Kd Ko F () F() = 1 and F M () = 1, H () K K The PLL degnaed a he fr-order loop nce he large power of n he polynomal of he denomnaor of he order one. Order of PLL accordance wh he order of he repecve polynomal n he denomnaor of ranfer funcon Chng-Yuan Yang / EE, NCHU

14 Type of PLL Kd Ko F () ()()()()()() F and e M o o e 1 e()() 1() G A() Inroducng he gan G(), G(), we ge n B() Laplace lm heorem for he fnal value of e (): KF() n B() ()() A ()() B e n Every PLL conan a lea one negraor, ha, VCO. n 1 (PLL a lea ype 1) Type of PLL: no. of pole ( = 0) n G() no. of negraor n he loop Each negraor conrbue one pole o he TF, o ha (ype no.) (order no.) n1 B() lm() e lm() 0 A n ()() B 1-13 Chng-Yuan Yang / EE, NCHU

15 Seady ae error n1 B() lm() e lm() 1 n 0 n A()() B Phae ep: () lm() e 1 0 The fnal value zero for PLL. Frequency ep: () 2 B(0) lm() e2 Kv: velocy error conan A(0)(0)(0) KF FM Kv n1 In ype-2 PLL wh wo negraor n he loop, he DC gan F(0) very large, o K v and conequenly he eady ae error neglgble. Frequency ramp: () 2 3 B(0) lm() e3 Ka: acceleraon or dynamc rackng error A(0) K n2 a Type-3 PLL can elmnae even he eady ae error e3 for o zero. Frequency locked loop may be condered a ype-0 PLL Chng-Yuan Yang / EE, NCHU

16 Block dagram of he fr-order PLL v () () () V ()() K d d e Ko K A o()() Vc vo () () o () o o() Kd KoK A K Open-loop ranfer funcon G() (loop gan) () Syem ranfer funcon Error ranfer funcon H () e o() G() K () 1() G K e() E() 1() H () K 1-15 Chng-Yuan Yang / EE, NCHU

17 Normalzed ranfer funcon of 1 -order PLL 20log()H jx 20log()E jx j Inroducng jx K K 1 Normalzed loop gan G() Normalzed ranfer funcon 1 H ()() (Low-pa fler) E (Hgh-pa fler) Chng-Yuan Yang / EE, NCHU

18 Phae deecor Phae Deecor A phae deecor a crcu whoe average oupu,, lnearly proporonal o he phae dfference,, beween wo npu. In he deal cae, he relaonhp beween and lnear, crong he orgn for = 0. The operaon of phae deecor mlar o ha of dfferenal amplfer n ha boh ene he dfference beween he wo npu, generang a proporonal oupu. Gan : he lope of he lne, expreed n Chng-Yuan Yang / EE, NCHU

19 Phae deecor : Mulpler Phae Deecor ung Analog Mulpler Glber mulpler Oupu volage dependen on he npu gnal amplude Narrow lnear range (Narrow lock range) Canno dcrmnae frequency dfference V d V d V dm /2 /2 e V V dm V o V d V n( ) V dm e offe 1-18 Chng-Yuan Yang / EE, NCHU

20 Phae deecor : XOR V 1 V 2 V ou V 1 V 2 V ou V K ou PD 2V V0 0 V0 2 ndependen of he npu frequency V 1 V 2 V V 1 2 V ou 0 V o u 2 V ou V 1 V 2 V 1 V V ou V ou Chng-Yuan Yang / EE, NCHU

21 Phae deecor : XOR (con d) When locked, he phae dfference 90 degree Oupu volage ndependen on he npu gnal amplude Oupu volage dependen on he npu duy cycle Narrow lnear range (Narrow lock range) /2 Canno dcrmnae frequency dfference Ue for Daa/Clock Recovery PLL: npu noe domnan - Hybrd PLL (Analog PLL + Dgal PLL) No Dead Zone 1-20 Chng-Yuan Yang / EE, NCHU

22 Concepual operaon of a phae-frequency deecor (PFD) PFD 1-21 Chng-Yuan Yang / EE, NCHU

23 Phae deecor : PFD hree-ae PD A B A B A A Sae I Sae II Sae III Q A Q A A Q A = 1 Q B = 0 Q A = 0 Q B = 0 Q A = 0 Q B = 1 B Q B Q B B B A A Sae dagram B Q A B Q A Q B Q B Tmng dagram 1-22 Chng-Yuan Yang / EE, NCHU

24 Implemenaon of PFD Inpu-oupu characerc: PFD followed by low-pa fler: 1-23 Chng-Yuan Yang / EE, NCHU

25 - Phae deecor : PFD When locked, he phae dfference 0 degree Oupu volage ndependen on he npu gnal amplude Oupu volage ndependen on he npu duy cycle Wde lnear range (Wde lock range) 2 Dcrmnae frequency dfference Ue carefully for Daa/Clock Recovery PLL - Hybrd PLL (Analog PLL + Dgal PLL) Dead Zone problem Due o fne gae delay Inroduce large jer or poor phae noe 1-24 Chng-Yuan Yang / EE, NCHU

26 - The wdh of he narrow ree pule A Q A Q B B A Q A Q A Q B B Q B E F Q B Ree E, F E F E, F Ree 1-25 Chng-Yuan Yang / EE, NCHU

27 PFD- Scheme wh NAND A (REF) UP B (VCO) DN 1-26 Chng-Yuan Yang / EE, NCHU

28 PFD- Dynamc CMOS PFD A (REF) A (REF) Q A (UP) B (VCO) Q A (UP) Q B (DN) A (REF) B (VCO) Q B (DN) B (VCO) Q A (UP) Q B (DN) Km, JSSC, May Chng-Yuan Yang / EE, NCHU