Test Generation for Designs with On-Chip Clock Generators

Transcription

1 Test Generation for Designs with On-Chip Clock Generators Xijiang Lin Mark Kassab Mentor Graphics Corp SW Boeckman Rd. Wilsonville, OR {xijiang_lin, Abstract High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to facilitate the test generation process and it in turn creates additional constraints for the automatic test pattern generation (ATPG) tool. This paper describes an efficient and effective method to take the hardware restriction originated from the on-chip clock generators into account in order to avoid generating clock sequences that cannot be produced by hardware. Experimental results on an industrial design show test pattern reduction and/or ATPG run time reduction when compared with the test generation method that enumerates valid clock sequences explicitly and restricts the test generation within enumerated test sequences. Keywords: ATPG, on-chip clock generator, PLL 1. Introduction Scan-based ATPG solutions have been adopted by industry to ensure high test coverage and reasonable development effort. In scan-based designs, sequential state elements are converted into scan cells such that they become control and observation points during test application. This greatly reduces the test generation cost and simplifies the failure diagnosis process. As gate count grows and transistor feature size shrinks, manufactured chips are more vulnerable to timing-related defects. At-speed delay fault testing has become a requirement to maintain the quality level of chips delivered to customers [1]-[3]. Timing defects typically originate from process variations and random defects. To generate tests detecting timing defects, two commonly used fault models are transition fault model and path delay fault model. The transition fault model [4] considers a gross delay at every gate terminal in the circuit and assumes that the additional delay at the fault site is large enough to cause a logic failure. The path delay fault model [5] focuses on the testing of a predefined structural path in order to detect the accumulated delays along the path. When generating test patterns for both transition and path-delay faults, it is required that each test pattern includes a pair of clock pulses for launching a transition at the fault site and capturing the fault effect at observation points. Based on the strategies of generating launch and capture events, there are two approaches used in industry: one is launch-off-shift and the other is launch-of-capture, or broadside. Figure 1 shows the clock waveforms for these two approaches. Comparing with the launch-off-shift approach, the launch-on-capture approach does not require scan-enable signal change atspeed and reduces the chance of testing non-functional logic. It is the dominant approach used in industry for delay fault testing. Fig. 1: Clock waveforms detecting timing defects ref_clk Clock Scan Enable Clock Scan Enable Last Last Capture (a) Launch-Off- _1 clk_1 PLL _2 CG 1 clk_2 CG 2 Fig. 2: Design with PLL Clock Domain 1 Clock Domain 2 No matter what kind of delay fault models are used, the generated test patterns must be applied at-speed in order to catch the timing defects that make the chips fail normal operation. In the past, the at-speed clock signals were provided from tester directly when testing the chips. However, the clock frequencies that high performance ICs require are difficult and costly to apply from the tester interface. Today, many designs [6]-[9] Launch Capture (b) Launch-On-Capture 1

2 use on-chip PLLs to generated high-speed internal clocks from a far slower external reference clock. The on-chip clocks not only provide more precise clock waveforms for test, but also enable use of low speed testers to test high performance chips. This scenario is shown in Figure 2. The tester provides the slower scan shift clock, reference clock, and control signals, for example, determining the clock source that drives the internal clocks clk_1 and clk_2. During shift, clk_1 and clk_2 are driven by. During capture, the on-chip generated clocks, _1 and _2, are used as launch and capture clocks for at-speed delay fault testing. To meet design requirements, such as timing closure and power consumption, modern designs typically include multiple internal clock domains as shown in Fig. 2. When applying these on-chip generated internal clocks during testing, the clock generators (CGs) are often designed in a programmable way such that each internal clock is controlled by the logic values loaded at a set of dedicated scan cells. The loaded control values determine the operation of the internal clocks during capture, such as whether the internal clock can be pulsed, in which cycle the internal clock is pulsed, and how many cycles the internal clock will be pulsed, etc. On the other hand, clock generation circuits typically require many external cycles to produce several internal clock pulses. ATPG tool often creates a cut at each internal clock and treats all cut internal clocks as primary input in order to dramatically reduce test generation effort [3]. As a result, the ATPG tool cannot arbitrarily generate any combination of internal clock sequences during test generation. The hardware restriction must be taken into account. The straightforward way to consider hardware restriction on clock sequences is to enumerae all or a subset of valid clock sequences explicitly in advance [14]. When doing test generation for a target fault, every valid clock sequence is considered one-by-one until one clock sequence detects the fault or all valid clock sequences have been tried and the fault is proven to be ATPG untestable. The drawbacks of this approach are listed below: Designs often include tens to hundreds of internal clocks and the clock generators can be programmed to pulse each internal clock from one to multiple clock cycles. It is a tedious and error-prone task to enumerate all valid clock sequences. To avoid fault coverage loss, all valid clock sequences must be considered by ATPG even if the faults testable by applying one clock sequence are already be covered by one or more other clock sequences. This may increase test generation effort as well as test pattern count. Besides using on-chip clocks controlled by clock generators for at-speed testing, some designs may also utilize them for detecting other types of defects, such as the defects modeled as stuck-at faults. Enumerating clock sequences explicitly is not an efficient way to apply test pattern compaction techniques using clock domain analysis and clock concatenation [11]. In this paper, we describe an effective and efficient test generation method for designs with internal clocks associated with clock control schemes. Our method takes the individual clock control schemes for each internal clock as input and the test generator implicitly assembles the clock control schemes into valid clock sequences during test generation. The experimental results for an industrial design shows significant test pattern count and/or ATPG running time reduction for stuck-at and broadside transition faults when compared with the test generation method based on enumerating valid clock sequences explicitly. The remainder of the paper is organized as follows. Section 2 gives the implementations of a couple of onchip clock generators for demonstration purpose. The proposed test generation method is described in detail in Section 3. The experimental results on an industrial design are reported in Section 4. Section 5 concludes the paper. 2. On-Chip Clock Generators In this section, we show the implementations of two on-chip clock generators. The first clock generator creates an internal clock in a burst way, i.e., multiple clock pulses must be generated continuously and there is no way to control each clock pulse individually. It is referred as burst clock control in this paper. The second clock generator allows fine control of each clock pulse and it is referred as non-burst clock control. In both implementations, we assume the clocks feeding the clock generators are free running clocks during capture. scan_in PLL SC 1 SC 2 Register Q 1 Q 2 Q 3 Q 4 Q 5 _en Latch scan_out clk_out Fig. 3: Schematic of clock generator for burst clock control Figure 3 shows the schematic of the burst clock control for an internal clock clk_out. It is a modified version of the clock generator proposed in [8]. During shift, is asserted to 1 and clk_out is driven by provided from tester. The shift register including DFFs Q 1 to Q 6 is set to 0 after shifting. During d0 d1 Q 6 g_ d0 d1 2

3 capture, is deasserted to 0, holds at off state, and clk_out is driven by gated clock. The number of continuous clock pulses at clk_out is determined by the loading values at the clock control scan cells SC 1 and SC 2. The burst clock control scheme is listed in Table 1. Table 1: Burst Clock Control Scheme SC 1 SC 2 # of Clock Pulses 0 - None 1 0 Three 1 1 Two Figure 4 shows the clock waveforms generated by loading SC 1 =1 and SC 2 =1. During capture, clock gater enable signal _en is asserted after four cycles that shift the logic value 1 into DFF Q 4 and deasserted after additional two cycles. Asserting _en allows two continuous PLL clock pulses transmit to clk_out. _en g_ clk_out Capture Fig. 4: Clock waveforms when loading SC 1 =1 and SC 2 =1 scan_in PLL Clock Selector SC 1 SC 2 sel_clk Latch scan_out clk_out Fig. 5: Schematic of clock generator for non-burst clock control Figure 5 shows the schematic of the non-burst clock control for an internal clock clk_out. At most two clock pulses can be generated at clk_out during capture and each clock pulse is controlled individually by a corresponding scan cell. During shift, asserting makes drive sel_clk and the gated clock sel_clk is always enabled to be transmitted to clk_out. During capture, deasserting makes drive sel_clk. The first clock pulse at clk_out is controlled by the loading value at the scan cell SC 2. If SC 2 =1, the clock pulse from sel_clk is transmitted to clk_out. Otherwise, the clock pulse at clk_out is disabled. After single clock pulse at sel_clk, the loading value at SC 1 is shifted into SC 2 and it controls the transmission of the clock pulse from sel_clk to clk_out. Both SC 1 and SC 2 are set to be 0 after two sel_clk clock cycles and clk_out stays at off state. The non-burst clock control scheme is shown in Table 2. Table 2: Non-burst Clock Control Scheme SC 1 SC 2 # of Clock Pulses 0 0 None 0 1 One pulse at 1 st cycle 1 0 One pulse at 2 nd cycle 1 1 Two pulses at 1 st and 2 nd cycles 3. Test Generation for Clocks under Control As shown in Figure 4, it requires multiple PLL clock cycles to produce two internal clock cycles at clk_out during capture. To detect defects in the functional logic, the cycles with internal clock pulsed are most important from test generation point of view. On the other hand, the ATPG complexity grows exponentially when increasing the sequential depth to be considered by the test generator. To reduce test generation effort dramatically, we may add cut points at each internal clock and treats the internal clocks as primary inputs in order to avoid justifying clock pulse through clock generators sequentially. This scenario is shown in Figure 6 after cutting the internal clocks clk_1 and clk_2 shown in Figure 2. As a result, test generation effort is reduced by restricting in the cycles with internal clock pulsed. ref_clk _1 PLL _2 CG 1 CG 2 floating pins clk_1 new primary inputs clk_2 Fig. 6: Cuts at internal clocks Clock Domain 1 Clock Domain Description of Clock Control Scheme To avoid generating invalid clock sequences at the internal clocks, the clock control schemes for each cut internal clock must be provided to the ATPG tool. We use the pseudo-codes shown in Figures 7 and 8 to describe the clock control schemes and the ATPG tool loads the pseudo-codes to guide the clock sequences generated at each cut internal clock during test generation. In Figures 7 and 8, the strings shown in bold and italic are keywords and pin pathnames, respectively, and the strings following double slash are comment. The keywords FORCE and CONDITION are used to assign logic value at primary inputs and scan cells, respectively. Moreover, the logic value assigned by using CONDITION refers to the logic value loaded at scan cell right after scan shifting. 3

4 Figure 7 gives the description of the burst clock control scheme for the internal clock clk_out shown in Figure 3. Two {BURST, END} blocks define the conditions producing two and three continuous clock pulses at clk_out, respectively. The two numbers following the keyword BURST define the starting cycle and the ending cycle of the clock pulse at clk_out. The two force statements outside {BURST, END} blocks define the conditions apply to all {BURST, END} blocks during capture. desirable to pulse them simultaneously during test generation since the logic values captured into the interacting state elements are hard to be predicted without timing information [12][13]. We use the pseudocodes shown in Figure 10 to provide this restriction to the ATPG tool. In both {BURST, END} and {ATPG_CYCLE, END} blocks, we add force statements that assign clock-off value to the internal clocks. ATPG tool interrupts the force clock-off statement as not to pulse clk_2 (clk_1) when pulsing clk_1 (clk_2). CLOCK_CONTROL clk_out = FORCE 0; // Deassert scan enable during capture FORCE 0; // Force scan clock stay at off state PLL CG 1 ref_clk clk_1 Logic BURST 1 2 = // Produce two continuous clock pulses at clk_out CONDITION SC 1 1; // Assign loading value at scan cell SC 1 CG 2 clk_2 Logic CONDITION SC 2 1; // Assign loading value at scan cell SC 2 BURST 1 3 = // Produce three continuous clock pulses at clk_out CONDITION SC 1 1; CONDITION SC 2 0; Fig. 7: Description of the burst clock control scheme shown in Figure 3 Figure 8 gives the description of the non-burst clock control scheme for the internal clock clk_out shown in Figure 5. Two {ATPG_CYCLE, END} blocks define the conditions producing clock pulses at clk_out in 1 st and 2 nd clock cycles, respectively. The number following the keyword ATPG_CYCLE defines the clock cycle to pulse clk_out. CLOCK_CONTROL clk_out = FORCE 0; // Deassert scan enable during capture ATPG_CYCLE 1 = // Produce clock pulses at clk_out in 1 st cycle CONDITION SC 2 1; // Assign loading value at scan cell SC 1 ATPG_CYCLE 2 = // Produce clock pulses at clk_out in 2 nd cycle CONDITION SC 1 1; Fig. 8: Description of the non-burst clock control scheme shown in Figure 5 To finely control the internal clocks in each clock domain, multiple clock generators may be used in a design as shown in Figure 9. Since the internal clocks clk_1 and clk_2 are derived from the same PLL clock, ATPG should allow pulse them simultaneously in order to reduce pattern count. However, when there exists clock skew between clk_1 and clk_2, it is not Fig. 9: Multiple clock generators controlled by the same PLL clock CLOCK_CONTROL clk_1 = BURST 1 2 = FORCE clk_2 0; // Prevent clk_2 from pulsing CLOCK_CONTROL clk_2 = ATPG_CYCLE 1 = FORCE clk_1 0; // Prevent clk_1 from pulsing Fig. 10: Prevent incompatible clock from pulsing simultaneously 3.2. Clock-off Control The pseudo-codes shown in Figures 7 and 8 describe the control conditions to pulse the internal clock. Meanwhile, ATPG tool must understand how to turn off the internal clocks during test pattern generations as well. There are two ways to achieve this goal: Similar to describe clock-on conditions, we may use pseudo-codes to explicitly describe the clock-off conditions for each burst and non-burst clock control. When loading the clock-off control condition to the ATPG tool, design rule checking must make sure the 4

5 clock-off conditions and the clock-on control conditions are mutually exclusive. ATPG tool derives the clock-off conditions directly from the clock-on conditions. For example, assuming pin is always constrained to 0 during test generation, the clock-off condition to disable the burst clock control shown in Figure 7 is calculated as follows: SC = 1 SC2 + SC1 SC2 SC1 Note that we exclude =1 as clock-off control condition since is a clock pin. Similarly, the clock-off control conditions for the ATPG cycles 1 and 2 shown in Figure 8 are SC 2 =0 and SC 1 =0, respectively. During test generation, ATPG has freedom to generate test patterns including different clock cycles while satisfying clock control schemes. For example, ATPG may generate one or two clk_out cycles when using the clock control scheme shown in Figure 8. If a test pattern with a single clk_out pulse cycle is generated, SC 2 must be 1 and the value assigned to SC 1 is do-notcare. However, ATPG cannot randomly fill SC 1 since SC 1 and SC 2 are driven by a free-running PLL clock during capture. If filling SC 1 to 1, this value will be shifted into SC 2 after pulsing sel_clk once and it enables to output the second clock pulse at clk_out. As a result, the generated single cycle pattern is an invalid test pattern. To prevent from pulsing clk_out outside the ATPG capture window, we always assign SC 2 =0 when creating test patterns including a single clk_out cycle even if it does not contribute to the control of the first clk_out pulse Deterministic Test Generation In the procedure generate_test(), we show a test generation flow for a target fault f by taking clock control schemes into account. Procedure generate_test(f) 1. Set ATPG window including one clock cycle and inject and activate the fault site f. 2. While there exist unsatisfied propagation objectives and/or justification objectives to detect fault f, do: (1) Make decision at an unsatisfied objective. (2) If the number of ATPG cycles included in the current ATPG window increases, any internal clock with clock control scheme or any primary input forced in the clock control schemes changes its value in any ATPG cycle, or any scan cell conditioned in the clock control scheme changes its value at the first cycle in the current ATPG capture window, do: (a) Check if the clock sequence containing in the ATPG window is valid and add extra cycles to the ATPG window to make the clock sequence containing in the ATPG window become valid if it is necessary. (b) If the clock sequence is invalid, do backtrack. 3. Specify unknown internal clocks, unknown primary inputs, and unknown loading values at scan cells if any clock control scheme is associated with them in order to create a complete test cube that satisfies all clock control schemes. The procedure generate_test() starts ATPG window including a single clock cycle and the ATPG window size can be expanded to include as many ATPG cycles as necessary to detect f. The key step in this procedure is Step 2(2)(a). It checks if it is possible to create a valid clock sequence after making current decision. The difficulty in implementing this check is that we may not be able to deterministically apply the clock control schemes to current ATPG window since: The number of ATPG cycles that should be included in the final test cube is unknown yet. ATPG may expand ATPG window by either inserting extra cycle(s) at the beginning of the window for justification or appending extra cycles(s) at the end of the window for fault effect propagation. To solve this problem, we carry out the checking according to four scenarios listed below. In each scenario, we will convert the ATPG window into fixed size in order make the check for the clock sequence possible. Scenario 1 ATPG window size cannot be changed due to reach the maximal allowed number of ATPG cycles or there is no unsatisfied objective: The clock control schemes for each internal clock can be mapped to ATPG cycle deterministically. Scenario 2 Fault effect is already propagated to observation point: No extra cycle will be appended at the end of ATPG window. Loop variable #_insert from 0 to the maximal number of allowed additional cycles inserted at the beginning of ATPG window. For each #_insert, insert number of #_insert pseudo cycles at the beginning of the window and assume ATPG window size become fixed. Then, check the clock sequence and return pass if the clock sequence containing in the fixed ATPG widow has no conflict with the clock control schemes. Otherwise, execute the above check again after increasing #_insert by 1. Scenario 3 No extra cycle will be inserted at the beginning of ATPG window: Loop variable #_append from 0 to the maximal number of allowed additional cycles appended at the end of ATPG window. For each #_append, append number of #_append pseudo cycles at the end of the window and assume ATPG window size become fixed. Then, check the clock sequence and return pass if the clock sequence containing in the fixed ATPG widow has no conflict with the clock control schemes. Otherwise, execute the above check again after increasing #_append by 1. 5

6 Scenario 4 Extra cycle(s) can be added in either side of ATPG window: Let variable #_insert loop from 0 to the maximal number of allowed additional cycles inserted at the beginning of ATPG window. For each #_insert, insert number of #_insert pseudo cycles at the beginning of the window first. Then, apply the scenario 3 to do the check. During checking the clock sequence, we will expand ATPG window in certain circumstances. For example, if the ATPG window includes one clock cycle and clk_out shown in Figure 3 is used to capture the fault effect at an observation point, at least one extra cycle must be inserted at the beginning of the ATPG window in order to create a valid clock sequence. However, we do not imply any necessary assignment during checking in order to distinguish the assignments at primary inputs and scan cells between the bits used to detect the fault and the bits used to create the valid clock sequence for test compaction purpose. We will give more explanation later in this section. In our implementation, we treat all specified bits before executing Step 3 in the procedure generate_test() as the test cube C d for fault detection and all additional bits specified after Step 3 as the test cube C c for clock control. Clock domain analysis and clock concatenation [11] are powerful methods to reduce test pattern count in the designs with multiple clocks. Blindly filling the unspecified internal clocks in Step 3 may increase test pattern count. For example, let us assume that design includes three internal clocks associated with clock control scheme and there is no interaction between clk 1 and clk 2 and between clk 1 and clk 3, but clk 2 and clk 3 are interacting clocks, i.e., test generator should not pulsed them simultaneously. To detect a fault f 1, let us assume that a test cube including one clock cycle is created after Step 2 and the test cube pulses clk 1 but the other two clocks are unspecified. When executing Step 3 to generate a complete test cube that satisfies all clock control schemes, we have to make a decision about how to fill unspecified internal clocks clk 2 and clk 3. Among three possible choices, if we select the one that pulses clk 2 and turns clk 3 off, the fault f 2 requiring pulse clk 3 cannot be compacted with this test cube. On the other hand, we are unable to apply clock concatenation approach to compact f 2 by appending one additional cycle at the end of the test cube since the test cube generated after Step 3 must disable for pulsing all internal clocks outside ATPG window. We lose compaction here. By separating the assignments in a test cube to two test cubes, C d and C c, we could apply the fault detection test cube C d to incrementally target next secondary fault during compaction. If the compaction succeeds, we execute Step 3 again to generate a new clock control test cube C c. At the end of the compaction, C d and C c are merged together and the merged test cube is sent to fault simulator for fault simulation. The strategy described above avoids losing the effectiveness of the test compaction when applying clock domain analysis and clock concatenation for test pattern count reduction. 4. Experimental Results The proposed test generation method for the design with on-chip clock generators was implemented in a commercial tool. An industrial design is used to evaluate the test generation results by applying the proposed methods. (We will add test generation results for more designs if the paper gets accepted.) In Table 1, we list the characteristics of the design. The number of gates and the number of scan cells in the design are shown under the columns # Gates and # Scan Cells, respectively. The design includes 52 internal clocks and each internal clock is controlled by individual non-burst clock control scheme that allows generating at most two clock pulses. The greedy algorithm is used to classify 52 internal clocks into 8 clock groups. There is no interaction among the internal clocks in the same group. The total number of non collapsed faults is listed under the column # Non-Collapsed Faults. Table 3: Design characteristics # # Non- # Scan # Clock # Gates Internal Collapsed Cells Groups Clocks Faults 8.02M 559.6K M Obviously, enumerating all possible clock sequences for 52 internal clocks is a not only time consuming but also error-prone task. It is much easier to write 52 clock control pseudo codes and let ATPG tool to manipulate them implicitly during test generation. The test generation results by the applying the proposed method are shown in Table 4 under the column Proposed for both stuck-at faults and broadside transition faults. The number of generated test patterns and the fault coverage in percentage are given under the columns # Pat and FC, respectively. When generating test patterns for broadside transition faults, we restrict ATPG to always pulse the same set of clocks continuously in the two capture cycles in order to avoid testing cross clock domain faults. For example, if two non-interacting clocks, clk i and clk j, are pulsed in the launch cycle, they must be pulsed in the following capture cycle. Table 4: Test generation results Fault Type Enumerate Clock Run Proposed Pattern Sequences Time Reduction # Pat. FC % # Pat. FC % Ratio Stuck-at % 7.42 Transition % 0.87 For comparison, we also created a subset of clock sequences by explicitly enumerating the clock control schemes and make the test generator run under the constraints of these clock sequences. For stuck-at faults, 6

7 8 clock sequences were carefully created by taking both clock domain analysis and clock concatenation into account. For example, if there is no interaction between clk 1 and clk 2 and between clk 1 and clk 3, but clk 2 and clk 3 are interacting clocks, we will create a clock sequence shown below: Cycle 1: pulse clk 1 and clk 2. Cycle 2: pulse clk 3. For transition faults, another 8 clock sequences were created by always pulsing the same subset of clocks continuously. By using above example, we will create two clock sequences shown below: (a) Clock sequence 1: Cycle 1: pulse clk 1 and clk 2. Cycle 2: pulse clk 1 and clk 2. (b) Clock sequence 2: Cycle 1: pulse clk 3. Cycle 2: pulse clk 3. The test generation results based on enumerating clock sequences are given under the column Enumerate Clock Sequences. When comparing the proposed test generation method with the enumeration method, the test pattern reduction in percentage and the run time ratio (The run time consumed by the enumeration method over that consumed by the proposed method) are given under the columns Pattern Reduction and Running Time Ratio, respectively. It can be seen that significant test pattern reduction is achieved by using the proposed method. It is because the proposed method gives the test compaction more freedom to choose valid clock sequences. When comparing run time, the proposed method is 7.4 times faster than the enumeration method for stuck-at faults. But it is little bit slower for transition faults. The main reason of the slower performance for transition faults is caused by several optimization strategies we implemented for the enumeration method. Moreover, using the enumeration method may reduce the searching space since the clock sequences are already known before targeting a fault and it may make the ATPG tool abort less faults. 5. Conclusions In this paper, we present a test generation method for designs with on-chip clock generators. The proposed method provides an efficient and effective way to guide the deterministic test generator to generate test patterns that meet the clock control schemes restricted by the onchip clock generators. Compared with the enumeration test generation method, it avoids the time consuming and error-prone task that explicitly enumerates valid clock sequences before test generation. It also provides more freedom for test compaction such that smaller test set can be generated for both stuck-at and broadside transition faults. Significant speedup is achieved for the test generation when targeting stuck-at faults. Although the test generation method described in this paper focuses on the on-chip PLLs, it is worth to point out that the proposed method can be applied when the internal clocks associated with clock control schemes are derived from other clock sources, such as tester. References [1] K. S. Kim, S. Mitra, and P. G. RyanP. Girard, "Delay defect Characteristics and Testing Strategies", IEEE Design & Test of Computers, pp. 8-16, Sep.-Oct., [2] B. Benware, R. Madge, C. Lu, and R. Daasch, Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs, IEEE VLSI Test Symposium, pp , [3] X. Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson, and N. Tamarapalli, High-Frequency, At- Speed Scan Testing, IEEE Design & Test of Computers, pp , Sep.-Oct., [4] J.A. Waicukauski, E. Lindbloom, B.K. Rosen, and V.S. Iyengar, Transition Fault Simulation, IEEE Design & Test of Computer, pp , Apr [5] G.L. Smith, Model for Delay Faults Based Upon Paths, Proc. Intl. Test Conf., pp , [6] N. Tendolkar; R. Molyneaux, C. Pyron, and R. Raina, At-speed testing of delay faults for Motorola's MPC7400, a PowerPC TM microprocessor, IEEE VLSI Test Symposium, pp. 3-8, [7] T. McLaurin, F. Frederick, R. Slobodnik, The Testability Features of the ARM1026EJ Microprocessor Core, Proc. Intl. Test Conf., pp , [8] M. Beck, O. Barondeau, M. Kaibel, F. Poehl, X. Lin; and R. Press, Logic design for on-chip test clock generation - implementation details and impact on delay test quality, Proc. Design, Automation, and Test in Europe, 2005, pp [9] R. Press and J. Boyer, Easily Implement PLL Clock Switching for At-speed Test, Chip Design Magazine, February-March, [10] N. Tendolkar, R. Raina, R. Woltenberg, X. Lin; B. Swanson, and G. Aldrich, Novel techniques for achieving high at-speed transition fault test coverage for Motorola's microprocessors based on PowerPC instruction set architecture, IEEE VLSI Test Symposium, 2002, pp [11] X. Lin and R. Thompson, Test Generation for Designs with Multiple Clocks, Int. Conf. on Design Auto. Conf., pp , [12] V. Jain and J. Waicukauski, Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique, Int. Test Conf., pp , [13] X. Lin, S.M. Reddy, and I. Pomeranz, Test Pattern Reduction by Simultaneously Pulsing Interacting Clocks, VLSI Design and Test Symposium, [14] Scan and ATPG Process Guide, Mentor Graphics Corp. 7