Across-wafer CD Uniformity Enhancement through Control of Multi-zone PEB Profiles

Transcription

1 Across-wafer CD Uniformity Enhancement through Control of Multi-zone PEB Profiles Qiaolin Zhang *a, Paul Friedberg b, Cherry Tang c Bhanwar Singh c, Kameshwar Poolla a, Costas J. Spanos b a Dept of Mechanical Engineering, University of California, Berkeley b Dept of Electrical Engineering, University of California, Berkeley c Submicron Development Center, Advanced Micro Devices ABSTRACT This paper describes a novel approach to improving across-wafer CD uniformity through the litho-etch sequence. Our approach is to compensate for systematic CD perturbations by employing all available control authority though the litho-etch process sequence. In particular, we find that the most effective control input for regulating spatial variations in CD is found in the post exposure bake (PEB) process step. More precisely, we construct offset models that relate the PEB temperature profiles of multi-zone bake plates to their zone offsets using wireless, in-situ temperature sensors from OnWafer Technologies 1. A second model relating across-wafer CD to PEB bake plate zone offsets is then identified from CD data measured by CD-SEM. The CD-to-offset model and the temperature-to-offset model are used with knowledge of the resist sensitivity to determine optimal bake plate zone offsets which minimize post-etch CD variation. This is done using constrained quadratic optimization techniques. Partial experimental work and simulation results show the promise of our approach. We demonstrate through simulation that across-wafer CD variation can be significantly reduced for 15nm technology node and beyond. Keyword: Critical Dimension uniformity (CDU), across-wafer CDU, multi-zone PEB bake plate, zone offsets, process control, process modeling, nonlinear optimization. 1. INTRODUCTION As the semiconductor industry approaches the sub-.1 µm technology node, control of gate critical dimension (CD) becomes increasingly important and the constraints on across-wafer CD variation become substantially more stringent. Extensive research has been conducted on controlling wafer-averaged CD with schemes ranging from feed-forward to feed-forward/feedback closed-loop control. 2,3,4,5,6 In these papers, CD data was used to correct perturbations from litho-etch sequence in order to regulate the wafer-averaged CD to target and to minimize wafer-to-wafer and lot-to-lot CD variation. However the control of across-wafer CD variation is not explicitly treated in the existing literature. Effective control of across-wafer CD variation would result in a tighter distribution of transistor speeds. This, in turn, results in more consistent device performance and higher yield. Various sources contribute to CD variation through the lithography and etch sequence. These can be classified as in Table 1 below. Process step Tool Type of variation Coat Track across wafer (AW), wafer-to-wafer (w2w) Bake Track AW, w2w Expose Scanner AW, intra die, w2w Develop Track AW, w2w Etch Etcher AW, w2w Table. 1: Source and characteristics of several types of CD variation. * qzhang@eecs.berkeley.edu, Telephone: , Fax: , Address: 55L Cory Hall, University of California, Berkeley, CA 9472

2 From Table 1, it is apparent that the simplest approach to reduce across-wafer CD variation is to make each process step uniform. Several researchers have addressed improving single processing step uniformity. W. Ho et al proposed a cascade control structure 7 to reduce the coated resist film non-uniformity to less than 1nm by manipulating the temperature distribution of a multi-zone bake plate. A novel develop application technique of K. Sakamoto was shown to minimize the develop non-uniformity resulting in 6nm (3 sigma) within wafer CD variation 8. However, not every processing step through the litho-etch sequence offers spatial control authority. We note that in typical etch processes, spatial control is severely limited. The only potentially available control mechanism is the adjustment of backside helium pressure in dual-zone ESC cooling systems. However, such dual helium zone systems are not widely available for polysilicon etching. Moreover, backside helium pressure regulation offers very limited control authority during the etch process. Photolithography offers much more spatial control opportunities. This ranges from die-by-die exposure dose adjustment to compensation of spatial temperature profiles in the PEB step by adjusting heater zone offsets and PID settings. These two control authorities are generally easy to access. The central idea of our work is to use these control mechanisms to improve post-etch across wafer CD uniformity. In this paper, we limit our control actions to the PEB step. The exploration of the exposure settings is a subject left to be analyzed at a later time. To illustrate our approach, consider the typical process flow show in Figure 1 below. Across-wafer (AW) CD variation can be minimized if the overall AW CD variation sources can be balanced by properly tuning AW PEB temperature profiles of multi-zone bake plate. Spin/ Coat PAB Exposure PEB Develop Optimal multi-zone offsets Optimizer AW CD Metrology Fig. 1: Schematic view of lithography process control framework. The optimal heater zone offsets which correspond to the desired AW PEB temperature profile that minimizes the CD spread can be obtained through the CD offset model relating AW CD to multi-zone bake plate zone offsets. This model was constructed through a set of designed experiments. The photoresist PEB thermal sensitivity and temperature offset models relating AW PEB temperature profiles of the bake plate to its zone offsets were also extracted through parallel designed experiments. 15:15 nm DUV resist (295 Å) 2 Å SiRN Si substrate Fig. 2: 248nm process stack in experiment.

3 The designed set of experiments used a 248nm lithography process consisting of 2Å SiRN anti-reflectant coating and 295Å DUV resist on a bare silicon substrate. The lithography tool is a 248nm wavelength scanner along with a modern track featuring a multi-zone PEB bake plate module. The temperature of each zone of the multi-zone PEB bake plate is individually controlled by its zone offset. A CD-SEM was used to measure the resist CD at 45 die across each wafer. 2. CDU CONTROL METHODOLOGY: MODELING AND OPTIMIZATION 2.1 CDU Control Methodology with CD Offset Model As long as there is systematic AW CD variation due to disturbances in the litho sequence such as resist thickness signature from spin/coat and development signature from develop, it is feasible to tune AW PEB profiles of the multi-zone bake plate to compensate for these systematic perturbations to improve AW CDU. This approach relies on both the accurate measurement of the systematic across-wafer CD variation (for example by using a CD-SEM tool) as well as the effective control of the spatial distribution of PEB temperature in a multi-zone bake plate. Assuming the CD metrology tool has sufficient precision, the baseline systematic AW CD variation CD sys can be observed. CD sys is defined as: CD sys = CD baseline CD Following the estimation of the systematic CD variation, zone offsets of multi-zone bake plate could be optimized to counteract the estimated systematic AW CD variation. In this experiment, only zone offsets for the inner 7 zones corresponding to 2mm region of multi-zone bake plate are altered, leaving the outer 8 zone offsets, exposure dose, focus and all other parameters in their (nominal) baseline condition. Then the AW CDs can be expressed as: t arg et CD CD1 f CD2 f. = =.. CDn f 1 2 n ( O1, O2... O7 ) ( O, O... O ) ( O ) 1, O2... O7 (1) where O j is the offset for zone j and n is number of dies each wafer. The CD for die i, denoted CD i, is a function of the 7 zone offsets of the bake plate since each zone offset affects PEB temperature globally across the plate. This is principally due to the excellent thermal conductivity of bake plate. Generally, CDi = fi ( O1, O2... O7 ) is a nonlinear function, and the designed experiment was used to extract the nonlinear CD offset model. With the CD offset model (1) established, the CDU enhancement problem is formulated to a constrained nonlinear quadratic programming problem as follows: While 248nm lithography process was used here for convenience, we expect that this method will be most effective on 193nm lithography process, due to its increased resist sensitivity. The metrology noise level shall be much smaller than the baseline process variation (i.e., a third of the baseline process variation).

4 Minimize: CD CD T CD CD t t arg et arg et (2) Under Constraint: O L O OU (3) This defines the allowable operation region of zone offsets ( O, O O ) find the optimal zone offsets which minimize (2) A nonlinear optimizer was used to 2.2 CDU Control Methodology with PEB temperature Offset Model and resist PEB sensitivity We also used the temperature offset model and resist PEB thermal sensitivity to implement our CDU control approach. Previous research 9 shows that both the heating transient PEB temperature and the steady-state PEB temperature influence CD. The time-based PEB temperature model can be expressed as: T1 ( t) g T2 ( t) g. T ( t) = =.. T ( t) g 1 2 ( O1, O2... O7, t) ( O, O... O, t) ( O, O... O t) n n, (4) In this experiment, PEB temperature offset models at transient phase and steady-state phase were built. Assuming resist PEB thermal sensitivity is constant across the wafer, PEB temperature offset model can be transformed to the CD offset model: CD = )) ( T ( tr ) T baseline ( tr )) W tr + ( T ( st ) T baseline ( st W st S resist + CD baseline (5) Here S resist is the photoresist PEB thermal sensitivity, and W tr and W st are the weighting factors for transient PEB temperature and steady-state PEB temperature, respectively. With the transformed CD offset model (5), the CDU enhancement problem is also a constrained quadratic programming problem as in part 2.1 and has similar solution. 3. EXPERIMENTAL DESIGN The CD offset model (1) and the PEB temperature offset model (4) are the basic elements of the CDU control methodology. In order to extract the proposed nonlinear CD offset model and temperature offset model with high confidence level, a 7-factor DOE experiment involving various combinations of the 7 zone offsets was designed and carried out. To find the PEB temperature offset model relating AW PEB temperature profile to bake plate zone offsets, a wireless sensor wafer 1 capable of measuring PEB temperature trajectories (with an accuracy of.1 C, and a repeatability of.1 C) of 42 evenly distributed sites on 2mm bake plate was used to collect temperature data through the entire PEB cycle for each DOE run. Following each temperature measurement, a device wafer was patterned in parallel under the same PEB settings, using the standard lithography flow.

5 Using the CD data collected by the CD-SEM for all DOE runs, the CD offset model was extracted. The PEB temperature offset model was also used to check the validity of bake plate s CD offset model by evaluating the correlation between the PEB temperature offset model and the bake plate s CD offset model. 4. EXPERIMENTAL RESULTS AND DISCUSSION The proposed CDU control approach heavily depends on the multi-zone bake plate s capability to tune AW CD by manipulating its offsets, and this capability can be verified by the correlation between the AW CD and PEB temperature signatures. Fig. 3 and Fig. 4 show that both AW steady state PEB temperature and AW transient PEB temperature correlate strongly with the AW CD, with AW transient PEB temperature having larger temperature range. AW CD 16 AW steady state PEB temperature Fig. 3: AW CD and steady state PEB temperature signature (correlation =.82). AW CD 16 AW transient PEB temperature Fig. 4: AW CD and transient PEB temperature signature (correlation =.73). The photoresist s PEB thermal sensitivity (~-2nm/ºC) was extracted from the wafer-averaged CD and waferaveraged PEB temperature data for several DOE runs CD = *Temperature 151 CD [nm] PEB temperature [deg C] Fig. 5: PEB thermal sensitivity of 248nm resist used in this experiment.

6 The CD offset model (1) is illustrated in Fig. 6 and Fig. 7 by a snapshot of each zone offset s effect on across wafer CD for 1 unit increment of zone offset. These figures show that each zone offset can control the CD distribution on certain regions of the bake plate, indicating that the desired AW CD distribution can be approached by properly choosing the 7 zone offsets. 1.5 Fig. 6: Effect of zones 1, 2 and 3 on across wafer CD Fig. 7: Effect of zones 4, 5, 6 and 7 on across wafer CD. Similarly, the temperature offset model (4) was obtained from the temperature measurements, and each zone offset s effect on AW steady-state/transient PEB temperature for 1 unit increment of zone offset is illustrated in Figures 8, 9, 1 and Fig. 8: Effect of zones 1, 2 and 3 on AW steady-state PEB profile.

7 Fig. 9: Effect of zones 4, 5, 6 and 7 on AW steady-state PEB profile Fig. 1: Effect of zones 1, 2 and 3 on AW transient PEB profile Fig. 11: Effect of zones 4, 5, 6 and 7 on AW transient PEB profile. Comparing the above snapshots of the PEB temperature offset models to those of the CD offset model, it is clear that the coordinates of the PEB temperature offset models need to be rotated by about 9 o clockwise to match the CD offset model. This can be explained by the fact that the orientations of the sensor wafer and the device wafer on the bake plate are different, since the device wafers are aligned by the scanner but the sensor wafer is not. Further investigation found that a 9 o clockwise rotation of coordinates of the PEB temperature

8 offset model maximized its correlation with the CD offset model. Fig. 12 is the snapshot of the CD offset model, steady-state temperature offset model and transient temperature offset model of offset 4. Quantitative correlation analysis revealed that zone 4 s steady-state PEB temperature offset model correlates more strongly with its CD offset model than its transient temperature offset model does, which reinforces steady-state PEB temperature s larger effect on CD. Fig. 12: Effect of zone 4 on AW CD, AW steady-state and transient PEB profiles. Fig. 13: Effect of zone 4 on AW CD, AW steady-state and transient PEB profiles (after orientation correction). The stronger correlation between CD offset model and steady-state PEB temperature offset model indicates the steady-state PEB temperature profile s larger effect on AW CD variation, which is also reinforced by the longer temporal length of steady-state phase of PEB cycle shown in Fig PEB Cycle 12 Temperature [deg C] Transient Steady-state Time [sec] Fig. 14: Transient phase and steady-state phase in a PEB Cycle.

9 Since both steady PEB temperature profiles and transient PEB temperature profiles influence AW CD variation, with steady-state PEB profiles being the larger contributor, the AW steady-state/transient PEB temperatures can be tuned to compensate for other systematic AW CD variation sources in order to minimize AW CD variation. To achieve the best AW CD uniformity, CD t arg et was set to be an nx1 vector with 15nm as each entry, nonlinear optimization found the optimal zone offsets which minimized CD variation. Fig. 15 shows the baseline AW CD variation and simulated optimized AW CD variation after proper zone offsets correction. baseline Baseline CDU CDU 154 optimized Optimized CDU CDU Fig. 15: Baseline CD variation and optimized CD variation. The baseline across-wafer 1-sigma CD variation was 2.1nm. Using our CDU enhancement approach AW 1- sigma CD variation was narrowed down to 1.1nm in simulation, which verified the efficacy of the proposed approach. In addition to improving the post-develop resist CD uniformity, the proposed approach could also be used to improve post-etch poly/metal CD uniformity by tuning the AW post-develop CD profile to compensate for plasma etching induced systematic CD signature. In order to verify the capability of this type of compensation, the 7 zone offsets were optimized to push the AW post-develop CD distribution to follow a bowl shape and a tilted shape respectively. The simulation results are shown in Fig Fig. 16: Bowl shape and tilted shape across wafer post-develop CD.

10 The experiment and simulation results confirmed the validity of our approach to improve AW CDU. We used the CD-SEM (which has higher metrology noise than some scatterometry tools) for all our CD measurements. The optimal zone offsets of the bake plate were computed offline. The relatively high metrology noise of CD- SEM and the delay between metrology, optimization and application of the PEB recipe correction could deteriorate the performance of proposed CDU enhancement approach. Using scatterometry as an inline/integrated metrology tool, a real time feedback control framework based on control framework in Fig.1 could be easily implemented. We expect that this would offer significantly better performance. Due to the higher PEB thermal sensitivity (~-8nm/ºC) of 193nm resist, the proposed CDU control approach would also be more efficient in 193nm processing than current 248nm processing, and could potentially offer critical aid in the full transition of the 193nm process to production. 5. CONCLUSION An AW CDU enhancement approach was investigated through designed experiments using a 248nm lithography process and simulation. Temperature offset and CD offset models of multi-zone bake plate were extracted from experimental data, and zone offsets of multi-zone bake plate were then optimized to minimize AW CD variation. Experiment and simulation results verified that multi-zone bake plate can be tuned to compensate for other AW CD variation through the litho sequence to reduce post-develop CD variation. Using analogous techniques, PEB regulation makes it possible to engineer target AW post-develop CD maps to compensate for various etching induced systematic CD variations. ACKNOWLEDGEMENTS The authors would like to thank OnWafer Technologies for providing BakeTemp sensor wafers to support this project. This work was funded by Advanced Micro Devices, Applied Materials, Atmel, Cadence, Canon, Cymer, DuPont, Ebara, Intel, KLA-TENCOR, Mentor Graphics, Nikon Research, Novellus Systems, Panoramic Technologies, Synopsis, Tokyo Electron, and the UC Discovery Grant. REFERENCES 1. OnWafer Technologies: 2. S.W. Butler and J.A. Stefani, IEEE Trans. Semicond. Manuf. 7, 193, C. El-Chemali and J.S. Freudenberg, SEMATCH AEC/APC XIII Proceedings, Banff, Alberta, Canada, Oct D. S.L. Mui, H.Sasano, W.Liu, J. Kretz and J. Yamartina, Semiconductor International, June 22, P G.P.Kota, J.Luque, V.Vahedi, A. Khathuria, T. Dziura and A. Levy, Advanced process control for polysilicon gate etching using integrated CD metrology, SPIE microlithography, Santa Clara, CA, 23, S.Ruegsegger, A. Wagner, J.S. Freudenberg and D.S. Grimard, IEEE Trans. Semicond. Manuf. 12, 493, W. Ho, L. Lee, A. Tay and C. Schaper Resist film uniformity in the microlithography process, IEEE Trans. Semicond. Manufact., vol. 15, no. 3, Aug K. Sakamoto, Novel Develop Application Method to Improve Critical Dimension Control, Advances in Resist Technology and Processing XVIII, Proceedings of SPIE, vol. 4345, M. D. Smith, C. A. Mack, J. S. Petersen, Modeling the impact of thermal history during post exposure bake on the lithographic performance of chemically amplified resists, in Advances in Resist Technology and Processing XVIII, F. Houlihan, ed., Proc. SPIE 4345, pp , 21.