ICS reserves the right to make changes in the device data identified in

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1 ICS reserves the right to make changes in the device data identified in 查询 ICS1523 供应商捷多邦, 专业 PCB 打样工厂,24 小时加急出货

3 S

4 PIN NO. 1 VDDD 2 VSSD 3 SDA 4 SCL 5 PDEN 6 EXTFB 7 HSYNC PIN NAME 8 EXTFIL 9 XFILRET 10 VDDA 11 VSSA 12 OSC 13 I 2 CADR 14 LOCK/REF (SSTL) 15 FUNC (SSTL) 16 CLK/2 (SSTL) 17 CLK (SSTL) 18 VDDQ 19 VSSQ 20 CLK (PECL) 21 CLK+ (PECL) 22 CLK/2 (PECL) 23 CLK/2+ (PECL) 24 IREF TYPE PWR PWR IN/OUT IN IN IN IN IN IN PWR PWR IN DESCRIPTION Digital supply Digital ground Serial data I 2 -bus 3.3V to digital sections C 1 Serial clock I 2 -bus PFD enable External feedback in Horizontal sync External filter External filter return Analog supply Analog ground Oscillator IN I 2 C address OUT OUT OUT OUT PWR PWR OUT OUT OUT OUT IN Lock indicator/reference Function output Pixel clock/2 out Pixel clock out Output driver supply Output driver ground C 1 1 Suspends charge pump External divider input to 1 Clock input to PLL External PLL loop filter COMMENTS 1 PFD External PLL loop filter return 3.3V for analog circuitry Ground for analog circuitry Input from crystal oscillator 2 Chip I C address select Low = 4Dh read, 4Ch write High = 4Fh read, 4Eh write 1, 2 package Displays PLL or DPA lock or REF input SSTL_3 selectable HSYNC output SSTL_3 driver to ADC demux input SSTL_3 driver to ADC 3.3V to output drivers Ground for output drivers P ixel clock out Inverted PECL driver to ADC. Open drain. P ixel clock out PECL driver to ADC. Open drain. Pixel clock/2 out Inverted PECL driver to ADC demux input. Open drain. P ixel clock/2 out PECL driver to ADC demux input. Open drain. Reference current Reference current for PECL outputs

6 Register Index Name Access Bit Name Bit # Reset Value Description 0h Input Control R / W PDen 0 1 Phase Detector Enable (0=External Enable, 1=Always Enabled) PD_Pol 1 0 Phase Detector Enable Polarity (0=Not Inverted, 1=Inverted) Ref_Pol 2 0 External Reference Polarity (0=Positive Edge, 1=Negative Edge) Fbk_Pol 3 0 External Feedback Polarity (0=Positive Edge, 1=Negative Edge) Fbk_Sel 4 0 External Feedback Select (0=Internal Feedback, 1=External) Func_Sel 5 0 Function Out Select (0=Recovered HSYNC, 1=Input HSYNC) EnPLS 6 1 Enable PLL Lock/Ref Status Output (0=Disable 1=Enable) EnDLS 7 0 Enable DPA Lock/Ref Status Output (0=Disable 1=Enable) 1h Loop Control R / W * PFD Phase Detector Gain Reserved 3 0 Reserved PSD Post-Scaler Divider (0 = 2, 1 = 4, 2 = 8, 3 = 16) Reserved Reserved 2h FdBk Div 0 R / W * FBD FF PLL FeedBack Divider LSBs (bits 0-7) * 3h FdBk Div 1 R / W * FBD F PLL Feedback Divider MSBs (bits 8-11) * Reserved Reserved 4h DPA Offset R / W DPA_OS Dynamic Phase Aligner Offset Reserved 6 0 Reserved Fil_Sel 7 0 Loop Filter Select (0=External, 1=Internal) 5h DPA Control R / W ** DPA_Res DPA Resolution (0=16 delay elements, 1=32, 2=Reserved, 3=64) Metal_Rev Metal Mask Revision Number 6h Output Enables R / W OE_Pck 0 0 Output Enable for PECL PCLK Outputs ( 0=High Z, 1=Enabled) OE_Tck 1 0 Output Enable for STTL_3 CLK Output ( 0=High Z, 1=Enabled) OE_P2 2 0 Output Enable for PECL CLK/2 Outputs ( 0=High Z, 1=Enabled) OE_T2 3 0 Output Enable for STTL_3 CLK/2 Output ( 0=High Z, 1=Enabled) OE_F 4 0 Output Enable for STTL_3 FUNC Output ( 0=High Z, 1=Enabled) Ck2_Inv 5 0 CLK/2 Invert (0=Not Inverted, 1= Inverted) Out_Scl SSTL Clock Scaler (0 = 1, 1 = 2, 2 = 4, 3 = 8) 7h Osc_Div R / W Osc_Div Osc Divider modulus In-Sel 7 1 Input Select (0=HSYNC Input, 1=Osc Divider) 8h Reset Write DPA 0-3 x Writing xah resets DPA and loads working register 5 PLL 4-7 x Writing 5xh resets PLL and loads working registers h Chip Ver Read Chip Ver Chip Version 23 Dec (17 Hex) as in h Chip Rev Read Chip Rev Initial value 01h. Value Increments with each all-layer change. 12h Rd_Reg Read DPA_Lock 0 N/A DPA Lock Status (0=Unlocked, 1=Locked) PLL_Lock 1 N/A PLL Lock Status (0=Unlocked, 1=Locked) Reserved Reserved * Identifies double-buffered registers. Working registers are loaded during software PLL reset. ** Identifies double-buffered register. Working registers are loaded during software DPA reset.

7 PDen PD_Pol Phase/Frequency Detector Is Enabled When: 0 0 PDEN= 1 X 1 Always (Default) 1 0 PDEN = 0

8 EnPLS EnDLS I N_SEL LOCK/REF(14) 0 0 N/ A N/ A 1 if DPA locked, 0 otherwise 1 0 N/ A 1 if PLL locked, 0 otherwise Post Schmitt trigger HSYNC(7) XOR Ref_Pol F osc Osc_Div

9 Bit 2 Bit 1 Bit 0 PFD Gain (µa/ 2π rad) Bit 5 Bit 4 PSD Divider (default)

10 Selects clock edge offset in discrete steps from zero to one clock period minus one step. Resolution (number of delay elements per clock cycle) is selected by DPA_Res0-1 (Reg 5:0-1). Note: Offsets equal to or greater than one clock period are neither recommended nor supported. Example: For DPA_Res0-1=01H, the clock can be delayed from 0 to 31 steps.

11 Bit 1 Bit 0 Delay Elements CLK Range, MHz Reserved Revision Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 A B C C D E F G

12 Bit 7 Bit 6 CLK Divider

13 Value xa Resets DPA 5x PLL 5A DPA and PLL

17 RANDOM REGISTER WRITE PROCEDURE S x W A A A P 7 bit address register address data Acknowledge Acknowledge STOP condition START condition WRITE command Acknowledge RANDOM REGISTER READ PROCEDURE S X W A A S X R A A P 7 bit address register address 7 bit address data Acknowledge Repeat START Acknowledge STOP condition START condition WRITE command Acknowledge READ command NO Acknowledge SEQUENTIAL REGISTER WRITE PROCEDURE S X W A A A A A P 7 bit address register address data data Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge START condition WRITE command STOP condition SEQUENTIAL REGISTER READ PROCEDURE S X W A A S X R A A A P 7 bit address register address 7 bit address data data Acknowledge Repeat START Acknowledge NO Acknowledge START condition WRITE command Acknowledge READ command Acknowledge STOP condition Direction: From bus host to device From device to bus host

20 Unterminated Outputs Terminated Outputs

22 DC Supply Current Supply Supply Supply PARAMETER Current, Digital Current, Output Drivers Current, Analog SYMBOL IDDD CONDITIONS MIN MAX UNITS V DDD = 3.6V 25 ma I DDQ V DDQ = 3.6V, no output drivers enabled. 6 ma IDDA Digital Inputs (SDA, SCL, PDEN, EXTFB, HSYNC, OSC, I 2 C ADR) Input Input PARAMETER High Voltage Low Voltage SYMBOL V DDA = 3.6V 5 ma CONDITIONS MIN MAX UNITS VIH V VIL VSS V Input Hysteresis V Input Input Input High Current Low Current Capacitance SDA (In Output Mode: SDA is Bidirectional) Output PARAMETER Low Voltage IIH V IH = VDD ± 10 µ A IIL V IL = 0 ± 200 µ A C in 10 pf SYMBOL VOL PECL Outputs (CLK+, CLK, CLK/2+, CLK/2 ) Output PARAMETER High Voltage Output Low Voltage (Note: VOL must not fall below the level given so that the correct value for IOUT can be maintained.) SYMBOL CONDITIONS IOUT = 3 ma. VOH = 6.0V maximum as determined by the external pull-up resistor. CONDITIONS MIN MIN MAX UNITS 0.4 V MAX VOH I OUT = 0 VDD VOL S STL-3 Outputs (CLK, CLK/2, FUNC, LOCK/REF) PARAMETER SYMBOL UNITS IOUT = programmed value 1. 0 V CONDITIONS MIN MAX V UNITS Output Resistance R O 1 < VO< 2V 80 AC Input Characteristics PARAMETER SYMBOL CONDITIONS MIN MAX UNITS HSYNC Input Frequency fhsyn C Reg 7:7 = MHz OSC Input Frequency fos C Reg 7:7 = MHz

23 VCO Output Frequency and Intrinsic Jitter Frequency (Slow: 70ºC) 600 Frequency (Nominal: 30ºC) 500 Frequency (Fast: 0ºC) Jitter 70ºC) 500 VCO Frequency (MHz) Jitter 30ºC) Jitter 0ºC) Frequency Jitter Jitter (ps) VCO Voltage

24 ns Delay MHz - 72 Hz MHz - 85 Hz DPA Delay-16 Element Resolution DPA Setting ns Delay DPA Delay - 32 Element Resolution MHz - 60 Hz MHz - 75 Hz DPA Setting DPA Delay - 64 Element Resolution ns Delay MHz - NTSC 39.8 MHz DPA Setting

26 Symbol t R t P t S t F Timing Description Rise Fall Units REF ns PECL CLK ns SSTL-CLK ns FUNC_OUT ns Symbol Timing Description Min Typ Max Units t 0 t 1 HSYNC to REF delay ns REF to PECL clock delay ns t 2, t3 PECL clock duty cycle % t 4 PECL clock to SSTL_3 clock delay ns t 5 PECL clock to FUNC_OUT delay ns t 6 PECL clock to PECL/2 clock ns t 7 PECL clock to SSTL_3 CLK/2 delay ns t 8, t9 SSTL clock duty cycle %

27 ICS reserves the right to make changes in the device data identified in

White Electronic Designs

查询 WS1M32-25HSCA 供应商 White Electronic Designs 捷多邦, 专业 PCB 打样工厂,24 小时加急出货 1Mx32 SRAM MODULE FEATURES Access Times of 17, 20, 25ns Packaging 4 lead, 2mm CQFP, (Package 511) 66 pin PGA Type, 1 35" sq, Hermetic