MC74VHC1GT125. Noninverting Buffer / CMOS Logic Level Shifter with LSTTL Compatible Inputs
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1 C74CGT Noninvering Buffer / COS ogic evel Shifer wih STT Compaible Inpus The C74CGT is a single gae noninvering buffer fabricaed wih silicon gae COS echnology. I achieves high speed operaion similar o equivalen Bipolar Schoky TT while mainaining COS low power dissipaion. The C74CGT requires he 3 sae conrol inpu () o be se igh o place he oupu ino he high impedance sae. The device inpu is compaible wih TT ype inpu hresholds and he oupu has a full COS level oupu swing. The inpu proecion circuiry on his device allows overvolage olerance on he inpu, allowing he device o be used as a logic level ranslaor from 3 COS logic o COS ogic or from.8 COS logic o 3 COS ogic while operaing a he high volage power supply. The C74CGT inpu srucure provides proecion when volages up o 7 are applied, regardless of he supply volage. This allows he C74CGT o be used o inerface circuis o 3 circuis. The oupu srucures also provide proecion when CC = 0. These inpu and oupu srucures help preven device desrucion caused by supply volage inpu/oupu volage mismach, baery backup, ho inserion, ec. Feaures igh Speed: PD = 3. ns (Typ) a CC = ow Power Dissipaion: I CC = A (ax) a T A = C TT Compaible Inpus: I = 0.8 ; I = COS Compaible Oupus: O > 0.8 CC ; O < 0. Power Down Proecion Provided on Inpus and Oupus Balanced Propagaion Delays Pin and Funcion Compaible wih Oher Sandard ogic Families Chip Complexiy: FETs = 6; Equivalen Gaes = 6 Pb Free Packages are Available SC 88A/SOT 33/SC 70 DF SUFFIX CASE 49A TSOP /SOT 3/SC 9 DT SUFFIX CASE 483 W PSSIGNENT 3 4 ARKING DIAGRAS = Device Code = Dae Code* = Pb Free Package W W (Noe: icrodo may be in eiher locaion) *Dae Code orienaion and/or posiion may vary depending upon manufacuring locaion. CC CC 3 4 A Inpu FUNCTION TABE Inpu Oupu Figure. Pinou (Top iew) X Z Figure. ogic Symbol ORDERING INFORATION See deailed ordering and shipping informaion in he package dimensions secion on page 4 of his daa shee. Semiconducor Componens Indusries, C, 007 Publicaion Order Number: C74CGT/D
2 C74CGT AXIU RATINGS Symbol Characerisics alue Uni CC DC Supply olage 0. o +7.0 IN DC Inpu olage 0. o +7.0 OUT DC Oupu olage CC = 0 igh or ow Sae 0. o o CC + 0. I IK Inpu Diode Curren 0 ma I OK Oupu Diode Curren OUT < ; OUT > CC +0 ma I OUT DC Oupu Curren, per Pin + ma I CC DC Supply Curren, CC and +0 ma P D Power Dissipaion in Sill Air SC 88A, TSOP 00 mw JA Thermal Resisance SC 88A, TSOP 333 C/W T ead Temperaure, mm from Case for 0 s 60 C T J Juncion Temperaure Under Bias +0 C T sg Sorage Temperaure 6 o +0 C ESD ESD Wihsand olage uman Body odel (Noe ) achine odel (Noe ) Charged Device odel (Noe 3) > 000 > 00 N/A I achup achup Performance Above CC and Below a C (Noe 4) ±00 ma Sresses exceeding aximum Raings may damage he device. aximum Raings are sress raings only. Funcional operaion above he Recommended Operaing Condiions is no implied. Exended exposure o sresses above he Recommended Operaing Condiions may affec device reliabiliy.. Tesed o EIA/JESD A4 A. Tesed o EIA/JESD A A 3. Tesed o JESD C0 A 4. Tesed o EIA/JESD78 RECOENDED OPERATING CONDITIONS Symbol Characerisics in ax Uni CC DC Supply olage. IN DC Inpu olage 0.0. OUT DC Oupu olage 0.0 CC T A Operaing Temperaure Range + C r, f Inpu Rise and Fall Time CC =.0 ± ns/ Device Juncion Temperaure versus Time o 0.% Bond Failures Juncion Temperaure C Time, ours Time, ears 80,03, , , , , ,800.0 NORAIZED FAIURE RATE FAIURE RATE OF PASTIC = CERAIC UNTI INTERETAICS OCCUR TJ = 30 C TJ = 0 C TJ = 0 C TJ = 00 C TJ = 90 C TJ = 80 C TIE, EARS 40 8,900.0 Figure 3. Failure Rae vs. Time Juncion Temperaure
3 C74CGT DC EECTRICA CARACTERISTICS CC T A = C T A 8 C T A C Symbol Parameer Tes Condiions () in Typ ax in ax in ax Uni Î I inimum igh evel Î Inpu olage Î..0.0 Î Î I aximum ow evel Î Inpu olage Î Î Î Î 0.8Î Î O Î inimum igh evel Î IN = I or I Oupu olage I O Î.9.9 Î = 0 A IN = I or I Î IN = I or I Î Î I O = 4 ma.8.48 Î Î.34 Î I O = 8 ma Î O Î Î aximum ow evel IN = I or I Î Oupu olage Î I O = 0 A Î Î IN = I or I Î IN = I or I I Î O = 4 ma I O = 8 ma Î Î I IN Î aximum Inpu Î IN =. or 0 o ± 0.0 ±.0 eakage Curren. ±.0 A Î I CC Î Î aximum Quiescen IN = CC or. Î Supply Curren Î.0 0Î Î 40 A Î I CCT Î Quiescen Supply Î Inpu: IN = 3.4. Curren Oher Inpu: Î CC or Î ma Î I OPD Î Oupu eakage Î OUT = A Curren I Î OZ aximum 3 Sae Î eakage Curren Î IN = I or I. OUT = CC or Î ± 0. ±.Î Î ±. A Î I OPD Î Oupu eakage Î OUT = A Curren AC EECTRICA CARACTERISTICS Inpu r = f = ns T A = C Î T A 8 C T A C Î Symbol Parameer Tes Condiions in Typ ax in axî in ax Uni Î P, aximum Propagaion CC = 3.3 ± 0.3 C = pf Î P Delay, A o Î ns C = 0pF (Figures 3 and.) CC =.0 ± 0. C = pf Î C = 0pF Î Î PZ, aximum Oupu CC = 3.3 ± 0.3 C = pf Î PZ Enable TIme, o Î ns R = R I = 00 C = 0pF (Figures 4 and ) CC =.0 ± 0. C = pf Î R = R I = 00 C = 0pF Î Î PZ, aximum Oupu CC = 3.3 ± 0.3 C = pf Î PZ Disable Time, o Î R = R I = 00 C = 0pF 8.0 (Figures 4 and ) Î 4..0 ns 8.0 CC =.0 ± 0. C = pf Î R = R I = 00 C = 0pF Î Î C in aximum Inpu Capaciance Î 4 0 Î 0 pf Î C ou aximum Three Sae 6 pf Oupu Capaciance (Oupu in igh Impedance Sae) C, CC =.0 C PD Power Dissipaion Capaciance (Noe ) 4 pf. C PD is defined as he value of he inernal equivalen capaciance which is calculaed from he operaing curren consumpion wihou load. Average operaing curren can be obained by he equaion: I CC(OPR) = C PD CC f in + I CC / 4 (per buffer). C PD is used o deermine he no load dynamic power consumpion; P D = C PD CC f in + I CC CC. 3
4 C74CGT SWITCING WAEFORS A 0% CC 0% PZ PZ P P 0% CC 0% CC PZ PZ 0% CC Figure 4. Swiching Waveforms Figure. CC IG IPEDANCE O O 0.3 IG IPEDANCE DEICE UNDER TEST OUTPUT TEST POINT C * DEICE UNDER TEST TEST POINT k OUTPUT C * CONNECT TO CC WEN TESTING PZ AND PZ. CONNECT TO WEN TESTING PZ AND PZ. *Includes all probe and jig capaciance Figure 6. Tes Circui *Includes all probe and jig capaciance Figure 7. Tes Circui INPUT Figure 8. Inpu Equivalen Circui ORDERING INFORATION Device Package Shipping C74CGTDF 74CGTDFG C74CGTDF 74CGTDFG SC 88A / SOT 33 / SC 70 SC 88A / SOT 33 / SC 70 SC 88A / SOT 33 / SC 70 SC 88A / SOT 33 / SC /Tape & Reel C74CGTDT 74CGTDTG TSOP / SOT 3 / SC 9 TSOP / SOT 3 / SC 9 For informaion on ape and reel specificaions, including par orienaion and ape sizes, please refer o our Tape and Reel Packaging Specificaions Brochure, BRD80/D. 4
5 C74CGT PACKAGE DIENSIONS TSOP CASE ISSUE F X X NOTE 0.0 T 0.0 T G A B C D X 0.0 C A B T S SEATING PANE J K DETAI Z DETAI Z NOTES:. DIENSIONING AND TRANCING PER ASE 4., CONTROING DIENSION: IIETERS. 3. AXIU EAD TICKNESS INCUDES EAD FINIS TICKNESS. INIU EAD TICKNESS IS TE INIU TICKNESS OF BASE ATERIA. 4. DIENSIONS A AND B DO NOT INCUDE OD FAS, PROTRUSIONS, OR GATE BURRS.. OPTIONA CONSTRUCTION: AN ADDITIONA TRIED EAD IS AOWED IN TIS OCATION. TRIED EAD NOT TO EXTEND ORE TAN 0. FRO BOD. IIETERS DI IN AX A 0 BSC B.0 BSC C D G 0.9 BSC J K S.0 0 SODERING FOOTPRINT* SCAE 0: mm inches *For addiional informaion on our Pb Free sraegy and soldering deails, please download he ON Semiconducor Soldering and ouning Techniques Reference anual, SODERR/D. 6 C74CGT/D
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