Reliable Power Delivery for 3D ICs

Transcription

1 Relable Power Delvery for 3D ICs Pngqang Zhou Je Gu Pulkt Jan Chrs H. Km Sachn S. Sapatnekar Unversty of Mnnesota Power Supply Integrty n 3D Puttng the power n s as mportant as gettng the heat out Hgher current densty, faster current transents t worsen supply nose Greater challenge n 3D due to va resstance, lmted number of supply pns Pns (ma) Current per Power Pn ( Current The Trend per of Current power per Power pn Pn (2D) from ITRS ITRS D 3D Year 3D Crcut [IBM] 2 1

2 Thermal challenges Each layer generates heat Heat snk at the end(s) Smple analyss Layer 5 Power(3D)/Power(2D) = m m = # layers Layer 4 Let R snk = thermal resstance of heat snk T = Power R snk Layer 3 m tmes worse for 3D! And ths does not account for Layer 2 Increased effectve R snk Leakage power effects, T-leakage feedback Layer 1 Thermal bottleneck: a maor problem for 3D Bulk Substrate 3 Power delvery challenges Each layer draws current from the power grd Power pns at the extreme end ter(s) Smple analyss Current(3D)/Current(2D) = m m = # layers Let R grd = resstance of power grd V drop = Current R grd m tmes worse for 3D! Layer 5 Layer 4 Layer 3 And ths does not account for Increased effectve R grd Layer 2 Leakage power effects, ncreased current due to T-leakage feedback Power bottleneck: a maor problem for 3D Layer 1 Bulk Substrate 4 2

3 Power Supply Integrty Characterstcs 2D versus 3D Low frequency nose: 3D > 2D Md frequency nose: 3D 2D Hgh frequency nose: 3D 2D Resonant frequency: 2D > 3D Ter versus ter Low/md frequency nose: Z1 > Z2 > Z3 Hgh frequency nose: Z3 > Z1 > Z2 Resonant frequency: Z1 Z2 Z3 5 Packagng technologes Wre bondng Stacked package/stacked de Flp-chp 3D ntegraton [Stedl, EDN] Chp Packag e ] [Das et al., ISPD04] 6 3

4 Tradtonal power delvery Requrements V dd, GND sgnals should be at correct levels (low V drop) Electromgraton constrants Current densty must never exceed a specfcaton For each wre, I /w < J spec di/dt constrants Need to manage di/dt to reduce nductve effects Technques for meetng constrants Wdenng wres Usng approprate topologes Addng decouplng capactances Already challenged for 2D technologes Relable power delvery hard Decaps get leaky Crcut + CAD approaches necessary 7 Outlne of the talk Motvaton Swtched decaps Multstory Vdd CMOS+MIM decaps 8 4

5 Actve supply nose cancellaton Charge provded by swtched decap (=0.5C Vdd+C Vdd/2) much larger than that of a conv. decap (=2C Vdd) For a supply nose ( Vdd) of 5%, effectve decap value s boosted by 7.5X 9 Supply nose cancellaton: Results Nose (V) Normal Decap 1200pF Normal Decap 400pF Swdecap 200pF 0.02 Dgtal Swtched Decap Crcut Frequency (MHz) 200pF swtched decap has lower nose than 1200pF conventonal decap 5 11X boost over passve decaps dependng on supply nose magntude 10 5

6 Proof of concept: Swtched decap test chp Technology Quescent Current Regulaton Freq. Regulator Area (w/o decap) Regulator Area (w/ 300pF decap) Total De Area 0.13µm CMOS 0.54mA 10MHz-300MHz 100µmx70µm 190µmx220µm 0.9mmx1.8mm Swdecap off Swdecap on 25ns (40MHz) Tme (ns) dB reducton of the 40MHz resonant nose usng pF swtched decaps 11 Comparson wth passve dampng Swdecap Value Resonant Suppresson Equvalent Passve Decap Decap Boost 100pF 2.2dB 500pF 5X 200pF 5.5dB 1500pF 7.5X 300pF 9.8dB 3500pF 11X 12 6

7 Outlne of the talk Motvaton Swtched decaps Multstory Vdd CMOS+MIM decaps 13 Mult-story power supply 1-story 2-story Improved supply nose due to: Reduced current magntude Cleaner mddle supply voltage Attractve for 3D chps: Isolated substrate for each ter Chp s naturally parttoned Current 2I I Voltage Vdd 2Vdd Power 2Vdd I 2Vdd I Nose 15%Vdd < 8%Vdd 14 7

8 Mult-story power supply: Test layout A test layout n MITLL s SOI process shows a 5.3% area overhead 15 CAD solutons for mult-story crcuts 2V dd V dd R GND 16 8

9 Overall Desgn Flow Netlst and block nformaton Floorplannng nvolvng regular modules and regulators Assgnng modules usng a graph partton-based algorthm Module assgnment 17 Estmatng the wasted power R 1 0 x 1 M works between 2V M works between V dd dd andv dd and GND R 3 mn I ( t) R n 1 I ( t) (1 2x ) R 2 mn n 2 2 I ( t) ( I ( t)) 4 I ( t) I ( t) ( x x 2x x ) R 1 x 1 = 0 x 3 = 1 max S I ( t) I ( t)( x x 2x x ) = 0 f x = x = 1 f x x x 2 = 0 x 4 = 1 Graph parttonng problem!

10 Constructng the graph V 1 A B M 2 M 1 M 5 V 2 V 5 M A B M 4 3 V 3 V 4 w( V, V ) ( K k 1 S k S S S k ) I ( t) I ( t) 19 3D benchmarks Exercsed on GSRC floorplannng benchmarks Largest floorplan has 300 modules Comparson wth (slow)smulated annealng method Runtme Comparson: > 10 3 x speedup over SA

11 Outlne of the talk Motvaton Swtched decaps Multstory Vdd CMOS+MIM decaps 21 MIM decaps Capactance densty* CMOS ff/µm 2 at 90nm MIM ff/µm 2 Leakage densty* CMOS e-4 A/ cm 2 MIM - 3.2e-8 A/cm 2 Congeston MIM routng blockage [Roberts 2005] * Numbers deduced from Roberts et al., IEDM05 and PTM smulatons 22 11

12 Overall flow of the algorthm 3D layout nfo. Technology parameters Buld 3D power grd Transent power grd analyss Nose metrc S 0? yes Lnear programmng based decap allocaton no stop 23 Metrcs Nose: optmze the ntegral of nose volaton over tme V + z() Waveform of node on VDD grd Z= z() Lnearzed congeton metrc t Cong ( y ) k R k R k s the set of grd cells adacent to grd k λ reflects the effect on the congeston of grd k after nsertng a small MIM decap y n grd. 12

13 Sequence of lnear programs: formulaton Obectve mn α S + (1-α) P S = k (a k x k +b k y k ) = change of volaton area P = k (c k x k + d k y k ) = change n leakage x k : Newly added CMOS decap to grd k y k : Newly added MIM decap to grd k Constrants Congeston constrant Congk Cong k Decap resource constrant 0 x k 0 y k mn{ mn{ CMOS MIM, C, C k CMOS k MIM } } 25 Expermental results Ckt # Nodes Worst V droop (V) # nodes wth nose volatons Volaton Area S (V ns) Ibm123 18, Ibm05 12, bm08 17, bm10 29, bm18 75,

14 Expermental results: bm18 Volaton Area log 10 (S) CMOS MIM CMOS+MIM Leakage ent (ma) Leakage curre CMOS CMOS+MIM Concluson Power delvery nto a 3D chp s a crtcal problem for next-generaton desgns Incremental solutons wll only take us so far Already stretched even for 2D desgns Need nnovatve desgn + CAD solutons 28 14