POWER AND PERFORMANCE OPTIMIZATION OF STATIC CMOS CIRCUITS WITH PROCESS VARIATION

Transcription

1 POWER AND PERFORMANCE OPTIMIZATION OF STATIC CMOS CIRCUITS WITH PROCESS VARIATION Except where reference s made to the work of others, the work descrbed n ths dssertaton s my own or was done n collaboraton wth my advsory commttee. Ths dssertaton does not nclude propretary or classfed nformaton. Yuanln Lu Certfcate of Approval: Fa Foster Da Assocate Professor Electrcal & Computer Engneerng Vshwan D. Agrawal, Char James J. Danaher Professor Electrcal & Computer Engneerng Charles E. Stroud Professor Electrcal & Computer Engneerng Joe F. Pttman Interm Dean Graduate School

2 POWER AND PERFORMANCE OPTIMIZATION OF STATIC CMOS CIRCUITS WITH PROCESS VARIATION Yuanln Lu A Dssertaton Submtted to the Graduate Faculty of Auburn Unversty n Partal Fulfllment of the Requrements for the Degree of Doctor of Phlosophy Auburn, Alabama August 4, 2007

3 POWER AND PERFORMANCE OPTIMIZATION OF STATIC CMOS CIRCUITS WITH PROCESS VARIATION Yuanln Lu Permsson s granted to Auburn Unversty to make copes of ths dssertaton at ts dscreton, upon the request of ndvduals or nsttutons and at ther expense. The author reserves all publcaton rghts. Sgnature of Author Date of Graduaton

4 VITA Yuanln Lu, daughter of Rongchang Lu and Afeng Kong, was born n Nanjng, P. R. Chna. She attended Southeast Unversty n 1995 and graduated wth a Bachelor of Engneerng degree n Electronc Informaton Engneerng n She entered the Graduate School at Southeast Unversty n 1999 and receved the Master of Scence degree n Crcut and System n In January 2004, she joned the Ph.D. program of the Department of Electrcal and Computer Engneerng, Auburn Unversty. v

5 DISSERTATION ABSTRACT POWER AND PERFORMANCE OPTIMIZATION OF STATIC CMOS CIRCUITS WITH PROCESS VARIATION Yuanln Lu Doctor of Phlosophy, August 4, 2007 (M.S., Southeast Unversty, 2002) (B.S., Southeast Unversty, 1999) 142 Typed Pages Drected by Vshwan D. Agrawal Wth the contnung trend of technology scalng, leakage power has become a man contrbutor to power consumpton. Dual threshold (dual-v th ) assgnment has emerged as an effcent technque for decreasng leakage power. In ths work, a mxed nteger lnear programmng (MILP) technque smultaneously mnmzes the leakage and gltch power consumpton of a statc CMOS (Complementary Metal Oxde Semconductor) crcut for any specfed nput-to-output crtcal path delay. Usng dual-threshold devces, the number of hgh-threshold devces s maxmzed and a mnmum number of delay elements s nserted to reduce the dfferental path delays below the nertal delays of the ncdent gates. The key features of the method are that the constrant set sze for the MILP model s lnear n the crcut sze and a power-performance tradeoff s allowed. v

6 Expermental results show 96%, 28% and 64% reductons of leakage power, dynamc power and total power, respectvely, for the benchmark crcut C7552 mplemented n BPTM 70nm CMOS technology. Due to the exponental relaton between subthreshold current and process parameters, such as the effectve gate length, oxde thckness and dopng concentraton, process varatons can severely affect both power and tmng yelds of the desgns obtaned by the MILP formulaton. We propose a statstcal mxed nteger lnear programmng method for dual-v th desgn that mnmzes the leakage power and crcut delay n a statstcal sense such that the mpact of process varaton on the respectve yelds s mnmzed. Expermental results show that 30% more leakage power reducton can be acheved by usng a statstcal approach when compared wth the determnstc approach that has to consder the worst case n the presence of process varatons. Compared to subthreshold leakage, dynamc power s less senstve to the process varaton due to ts lnear dependency on the process parameters. However, the determnstc technques usng path balancng to elmnate gltches, becomes neffectve when process varaton s consdered. Ths s because the perfect hazard flterng condtons can easly be destroyed even by a small varaton n some process parameters. We present a statstcal MILP formulaton to acheve a process-varaton-resstant gltchfree crcut. Expermental results on an example crcut prove the effectveness of ths method. v

7 ACKNOWLEDGMENTS I would lke to express my apprecaton and sncere thanks to my advsor, Dr. Vshwan D. Agrawal, who guded and encouraged me throughout my studes. Hs advce and research atttude have provded me wth a model for my entre future career. I also wsh to thank my advsory commttee members, Dr. Fa Foster Da and Dr. Charles E. Stroud for ther gudance and advce on ths work. Apprecaton s expressed to Badhr Upplappan who gave me a great help durng my nternshp n Analog Devce Inc. I also apprecate those who have made contrbutons to my research. Thanks to Jns Alexander, Hllary Grmes, Kyungseok Km, Khushboobenumesh Sheth, Fan Wang and Ntn Yog for ther cooperaton and helpful dscussons throughout the course of ths research. Fnally, I would lke to thank, although ths s too weak a word, my parents and sster, all the other famly members and my frends for ther contnual encouragement and support throughout ths work. v

8 Style manual or journal used: Bblography follows those of the transactons of the Insttute of Electrcal and Electroncs Engneers and s sorted n alphabetcal order. Computer software used: Mcrosoft Word 2003 v

9 TABLE OF CONTENTS LIST OF FIGURES LIST OF TABLES x xv CHAPTER 1 INTRODUCTION Motvaton Leakage Power Gltch Power Process Varaton Problem Statement Orgnal Contrbutons Organzaton of the Dssertaton 5 CHAPTER 2 PRIOR WORK: TECHNIQUES FOR LOW POWER DESIGN Components of Power Consumpton Dynamc Power Leakage Power Technques for Leakage Reducton Dual-V th Assgnment Mult-Threshold-Voltage CMOS Adaptve Body Bas Transstor Stackng Optmal Standby Input Vectors Power cutoff Technques for Dynamc Power Reducton Logc Swtchng Power Reducton 17 x

10 2.3.2 Gltch Power Elmnaton Power Optmzaton wth Process Varaton Leakage Mnmzaton wth Process Varaton Gltch Power Optmzaton wth Process Varaton Summary 28 CHAPTER 3 DETERMINISTIC MILP FOR LEAKAGE AND GLITCH MINIMIZATION Leakage and Delay A Determnstc MILP for Power Mnmzaton Objectve Functon Constrants Delay Element Implementaton Delay Element Comparson Capactances of a Transmsson-Gate Delay Element MILP and Heurstc Algorthms Summary 46 CHAPTER 4 STATISTICAL MILP FOR LEAKAGE OPTIMIZATION UNDER PROCESS VARIATION Effects of Process Varaton on Leakage Power Overvew of Determnstc Dual-V th Assgnment by MILP Statstcal Dual-V th Assgnment Statstcal Subthreshold Leakage Modelng Statstcal Delay Modelng MILP for Statstcal Dual-V th Assgnment Lnear Approxmatons Summary 63 CHAPTER 5 TOTAL POWER MINIMIZATION WITH PROCESS VARIATION BY DUAL-THRESHOLD DESIGN, PATH BALANCING AND GATE SIZING 64 x

11 5.1 Determnstc MILP for Total Power Optmzaton by Dual-V th, Path Balancng and Gate Szng Gate Szng for Dynamc Power Reducton Determnstc MILP for Total Power Reducton Results Statstcal MILP for Total Power Optmzaton The Impact of Process Varaton on Dynamc Power Statstcal MILP for Power Optmzaton wth Process Varaton Mnmzng Impact of Process Varaton on Leakage or Gltch Power Summary 93 CHAPTER 6 RESULTS Results of Determnstc MILP (Chapter 3) for Total Power Optmzaton Leakage Power Reducton Leakage, Dynamc Gltch and Total Power Reducton Tradeoff Between Gltch Power Reducton and Area/Power Overhead Contrbuted by the Delay Elements Results of Statstcal MILP (Chapter 4) for Leakage Optmzaton Run Tme of MILP Algorthms Summary 110 CHAPTER 7 CONCLUSION AND FUTURE WORK Concluson Future Work Gate Leakage Technques for Gltch Elmnaton wth Process Varaton Improvement of the MILP formulaton Complexty of the MILP formulaton 116 BIBLIOGRAPHY 118 x

12 LIST OF FIGURES Fgure 2.1 Leakage currents n an nverter Fgure 2.2 An example dual-v th crcut Fgure 2.3 Schematc of MTCMOS, (a) orgnal MTCMOS, (b) PMOS nserton MTCMOS, (c) NMOS nserton MTCMOS Fgure 2.4 Scheme of an adaptve body based nverter Fgure 2.5 Comparson of leakage for (a) one sngle off transstor n an nverter and (b) two serally-connected off transstors n a 2-nput NAND gate Fgure 2.6 Scheme of cluster voltage scalng Fgure 2.7 Example crcut for llustratng ECVS Fgure 2.8 Tmng wndow for an n-nput NAND gate Fgure 2.9 Gltch elmnaton methods, (a) gltches at the output of a NAND gate, (b) gltch elmnaton by hazard flterng, and (c) gltch elmnaton by path delay balancng Fgure 2.10 Usng redundant mplcant to elmnate hazards, (a) a multplexer wth hazards, and (b) a redundant mplementaton of multpler free from certan hazards Fgure 3.1 Crcut for explanng MILP constrants Fgure 3.2 (a) An unoptmzed crcut wth hgh leakage and potental gltches, and (b) ts correspondng optmzed gltch-free crcut wth low leakage Fgure 3.3 A full adder crcut wth all gates assgned low V th (Ileak = 161 na) Fgure 3.4 (a) Dual-V th assgnment and delay element nserton for T max = T c. (Ileak = 73 na), and (b) Dual-V th assgnment and delay element nserton for T max = 1.25T c. (Ileak = 16 na) Fgure 3.5 Delay elements: (a) CMOS transmsson gate and (b) Cascaded nverters x

13 Fgure 3.6 Capactances n a MOS transstor Fgure 3.7 (a) Dstrbuted and (b) Lumped RC models of a NMOS transmsson gate Fgure 3.8 Comparson of MILP wth heurstc backtrackng algorthm Fgure 4.1 Leakage power dstrbuton of un-optmzed C432 under local effectve gate length varaton Fgure 4.2 Leakage power dstrbutons of the determnstcally optmzed dual-v th C432 due to process parameter varatons, (a) global varatons, (b) local varatons, (c) effectve gate length varatons, and (d) threshold voltage varatons Fgure 4.3 Basc dea of usng MILP to optmze leakage Fgure 4.4 Detaled determnstc MILP formulaton for leakage mnmzaton Fgure 4.5 Monte Carlo Spce smulaton for leakage dstrbuton of one MUX cell n TSMC 90nm CMOS technology Fgure 4.6 Basc MILP for statstcal dual-v th assgnment Fgure 4.7 Detaled formulaton of statstcal dual-v th assgnment MILP Fgure 5.1 Extended cell lbrary wth 6 corners for gate szng Fgure 5.2 Comparson of dynamc power optmzaton of crcuts mplemented by 2- corner and 6-corner cell lbrary wth dfferent weght factors Fgure 5.3 Optmzaton space comparson between leakage and dynamc power of 90ºC Fgure 5.4 Achevng the mnmum total power by adjustng the weght factor (W) Fgure 5.5 Three possble gltch flterng condtons Fgure 5.6 Three possble gltch flterng condtons under process varaton Fgure 5.7 Dynamc power dstrbuton of un-optmzed (wth-gltch) C432 under local delay varaton Fgure 5.8 Dynamc power dstrbuton of optmzed (gltch-free) C432 under local delay varaton Fgure 5.9 Comparson of the mpacts of 15% local process varaton on the dynamc power n C432 whch s optmzed by the statstcal MILP wth the emphass on the resstance of dynamc power to process varaton n Secton , or x

14 by the determnstc MILP n Secton (N=1, s the expected normalzed mnmum dynamc power n the optmzed gltch-free C432) Fgure 5.10 Comparson of the mpacts of 15% local L eff process varaton on the leakage power n C432 whch are optmzed by the statstcal MILP wth the emphass on the resstance of dynamc power to process varaton n Secton , or by the determnstc MILP n Secton (N1 and N2 are the normalzed nomnal leakage power n the optmzed gltch-free C432) Fgure 5.11 Flowchart of makng a decson as to whch one, leakage or dynamc power, should be optmzed wth process varaton Fgure 6.1 Tradeoffs between leakage power and performance Fgure 6.2 (a) dynamc power reducton by delay elements wth a certan delay D, and (b) cumulatve dynamc power reducton by delay elements wth delay 0~D Fgure 6.3 The relaton between the number of nserted delay elements (assorted by ther contrbuton to the dynamc power reducton) and the correspondng percentage of gltch power reducton Fgure 6.4 Power-delay curves of determnstc and statstcal approaches for C Fgure 6.5 Leakage power dstrbuton of dual-v th C7552 optmzed by determnstc method, statstcal methods wth 99% and 95% tmng yelds, respectvely. 107 Fgure 7.1 An example crcut used for llustratng the tmng volaton Fgure 7.2 Flowchart of an teratve power optmzaton procedure xv

15 LIST OF TABLES Table 3.1 Leakage currents for low and hgh V th NAND gates Table 3.2 Delays of low and hgh V th NAND gates Table 4.1 Leakage power dstrbuton of un-optmzed C432 under local effectve gate length varaton Table 4.2 Comparson of leakage power of determnstcally optmzed dual-v th C Table 5.1 Extended cell lbrary wth 6 corners for gate szng Table 5.2 Comparson of dynamc power optmzaton of C432 mplemented by 2 corners and 6 corners cell lbrary, respectvely Table 5.3 Normalzed dynamc power dstrbuton of un-optmzed C432 under local delay varaton Table 5.4 Normalzed dynamc power dstrbuton of optmzed C432 under local delay varaton Table 6.1 Leakage reducton alone due to dual-v th assgnment (27 C ) Table 6.2 Comparson of the percentage of gltches n unoptmzed crcuts wth the real percentage of dynamc power reducton acheved by path balancng wth consderng the addtonal loadng capactances contrbuted by delay elements Table 6.3 Leakage, gltch and total power reducton for ISCAS 85 benchmark crcuts (90 C ) Table 6.4 Number of delay elements for optmzaton Table 6.5 Comparson of leakage power savng due to statstcal modelng wth two dfferent tmng yelds (η) Table 6.6 Monte Carlo Spce smulaton results for the mean and the standard devaton of the leakage dstrbutons of ISCAS 85 crcuts optmzed by determnstc method, statstcal methods wth 99% and 95% tmng yelds, respectvely. 108 xv

16 CHAPTER 1 INTRODUCTION The prmary contrbuton of ths work s a new desgn methodology to mnmze the total power consumpton n a statc CMOS (Complementary Metal Oxde Semconductor) crcut. A mxed nteger lnear programmng (MILP) formulaton s proposed to optmze leakage power and dynamc gltch power, wthout reducng crcut performance, by dual- V th assgnment, path balancng and gate szng. To consder the process varaton, statstcal delay and leakage models are adopted to optmze power consumpton n a statstcal sense such that the mpact of process varaton on the power and tmng yelds s mnmzed. 1.1 Motvaton Wth the contnuous ncrease of the densty and performance of ntegrated crcuts due to the scalng down of the CMOS technology, reducng power dsspaton becomes a serous problem that every crcut desgner has to face Leakage Power In the past, the dynamc power domnated the total power dsspaton of a CMOS devce. Snce dynamc power s proportonal to the square of the power supply voltage, lowerng the voltage reduces the power dsspaton. However, to mantan or ncrease the performance of a crcut, ts threshold voltage should be decreased by the same factor, 1

17 whch causes the subthreshold leakage current of transstors to ncrease exponentally and make t a major contrbutor to power consumpton. To reduce leakage power, many technques have been proposed, ncludng transstor szng 45, 72], mult-v th 12, 19, 103], dual-v th 31, 45, 70, 72, ], optmal standby nput vector selecton 69, 84], transstor stackng 64, 65, 106], body bas 10, 91], etc. As the threshold voltage (V th ) of transstors n a CMOS logc gate s ncreased, the leakage current s reduced but the gate slows down. Dual-V th assgnment s an effcent technque for leakage reducton. The basc dea s utlzng the tmng slack on noncrtcal paths to mnmze the leakage power by assgnng hgh V th to some or all gates on non-crtcal paths Gltch Power Gltches as unnecessary sgnal transtons account for 20%-70% of the dynamc swtchng power 20]. To elmnate gltches, a desgner can adopt technques of hazard flterng 7, 38, 46, 83, 104] and path balancng 8, 46, 74]. In Hazard flterng, gate szng or transstor szng s used to ncrease the gate s nertal delay to flter out the gltches. An obvous dsadvantage of such hazard flterng, when used alone, s that t may ncrease the crcut delay due to the ncrease of the gate delay. Alternatvely, any gven performance can be mantaned by path delay balancng, although the area overhead and addtonal power consumpton of the nserted delay elements can become a major concern. The best way to elmnate gltches s to combne these two technques 8]. 2

18 1.1.3 Process Varaton The ncrease n varablty of several key process parameters can sgnfcantly affect the desgn and optmzaton of low power crcuts n the nanometer regme 61]. Due to the exponental relaton of leakage current wth some process parameters, such as the effectve gate length, oxde thckness and dopng concentraton, process varatons can cause a sgnfcant ncrease n the leakage current. There are two prncpal components of leakage current. Gate leakage s most senstve to the varaton n oxde thckness (T ox ), whle the subthreshold current s extremely senstve to the varaton n effectve gate length (L eff ), oxde thckness (T ox ) and dopng concentraton (N dop ). Compared to gate leakage, subthreshold leakage s more senstve to parameter varatons 66]. Dynamc power s normally much less senstve to the process varaton because of ts approxmately lnear dependency on the process parameters. However, any determnstc path balancng technque used for elmnatng gltches becomes less effectve under process varaton, snce the perfect hazard flterng condtons can be easly corrupted even wth a small varaton n some process parameters. To make the gltch-free crcuts optmzed by path balancng resstant to process varatons, a statstcal delay model s developed n ths work. 1.2 Problem Statement The problem solved n ths work s: Fnd a determnstc mxed nteger lnear programmng (MILP) formulaton to optmze the total power consumpton by dual threshold voltage (dual-v th ) assgnment, path balancng and gate szng. Further, derve 3

19 a statstcal mxed nteger lnear programmng formulaton to mnmze the mpact of process varatons on the optmal leakage and dynamc gltch power. 1.3 Orgnal Contrbutons In ths dssertaton, we frst propose a determnstc mxed nteger lnear programmng (MILP) formulaton to mnmze the leakage and dynamc power consumpton of a statc CMOS crcut for a gven performance. In a dual-threshold crcut ths method maxmzes the number of hgh-threshold devces and smultaneously elmnates gltches by balancng paths wth the smallest number of delay elements. Gate szng s also consdered to further mnmze the dynamc swtchng power by reducng the loadng capactances of gates. Snce leakage exponentally depends on some key process parameters, t s very senstve to process varatons. We treat gate delay and leakage current as random varables to reflect the mpact of process varaton. A mxed nteger lnear programmng (MILP) method for dual-v th desgn s proposed to mnmze the leakage power and crcut delay n a statstcal sense such that the effect of process varaton on the respectve yelds s mnmzed. Two types of yelds are consdered. Leakage yeld refers to the probablty of an optmzed crcut retanng the leakage current below the specfed value n the presence of random process varatons. Smlarly, tmng yeld s the probablty of the crtcal path delay stayng below the specfcaton. The expermental results show that 30% more leakage power reducton can be acheved by usng the statstcal approach, referred to as statstcal MILP, when compared wth the determnstc approach. 4

20 Gltch-free crcuts optmzed by path balancng are also qute senstve to process varatons. We further extend the statstcal MILP formulaton to optmze the dynamc swtchng power consderng process varaton and acheve process-varaton-resstant gltch-free crcuts. 1.4 Organzaton of the Dssertaton In Chapter 2, the basc components of power consumpton n a statc CMOS crcut are frst dscussed, followed by a survey of the relevant publshed lterature on low power desgn technques at the gate level. Chapter 3 proposes an orgnal mxed nteger lnear programmng (MILP) method for total power mnmzaton by dual-v th assgnment and path balancng. To consder process varaton, statstcal MILP optmzaton of leakage power and dynamc gltch power are presented n Chapter 4 and Chapter 5, respectvely. In Chapter 6, expermental results are presented. Fnally, a concluson and recommendatons for future work are gven n Chapter 7. 5

21 CHAPTER 2 PRIOR WORK: TECHNIQUES FOR LOW POWER DESIGN 2.1 Components of Power Consumpton Power consumpton n a statc CMOS crcut bascally comprses three components: dynamc swtchng power, short crcut power and statc power. Compared to the other two components, short crcut power normally can be gnored n submcron technology Dynamc Power Dynamc power s due to chargng and dschargng the loadng capactances. It can be expressed by the followng equaton 73]: P dyn 1 = C 2 L V 2 dd A F (2.1) where C L s the loadng capactances, ncludng the gate capactance of the drven gate, the dffuson capactance of the drvng gate and the wre capactance; V dd s the power supply voltage; A s the swtchng actvty; F s the crcut operatng frequency. Equaton (2.1) shows that dynamc swtchng power s drectly proportonal to the swtchng actvty, A, or the number of sgnal transtons. More the sgnal transtons, 6

22 hgher s the dynamc power consumpton. After a transton s appled at the nput, the output of a gate may have multple transtons before reachng a steady state (see Fgure 2.9(a)). Among these transtons, at most one s the essental transton, and all others are unnecessary transtons that are called gltches or hazards. Hence, dynamc power s composed of two parts, logc swtchng power whch s contrbuted by the necessary sgnal transtons for logc functons, and gltch power whch s caused by gltches or hazards Leakage Power The leakage current of a transstor s manly the result of reverse-based PN juncton leakage, subthreshold leakage and gate leakage as llustrated n Fgure 2.1. V dd Gate Leakage V dd Subthreshold Leakage Reverse Based PN-Juncton Leakage Gate Leakage Fgure 2.1 Leakage currents n an nverter. In submcron technology, the reverse-based PN juncton leakage s much smaller than subthreshold and gate leakage and hence can be gnored. The subthreshold leakage 7

23 s the weak nverson current between source and dran of an MOS transstor when the gate voltage s less than the threshold voltage 99]. It s gven by 42]: I sub W 2 Vgs V 1.8 th V ds = µ 0Cox VT e exp 1 exp (2.2) Leff nvt VT where µ 0 s the zero bas electron moblty, C ox s the oxde capactance per unt area, n s the subthreshold slope coeffcent, V gs and V ds are the gate-to-source voltage and dran-tosource voltage, respectvely, V T s the thermal voltage, V th s the threshold voltage, W s the channel wdth and L eff s the effectve channel length, respectvely. Due to the exponental relaton between I sub and V th, an ncrease n V th sharply reduces the subthreshold current. Gate leakage s the oxde tunnelng current due to the low oxde thckness and the hgh electrc feld whch ncreases the possblty that carrers tunnel through the gate oxde. Tunnelng current wll become a factor and may even be comparable to subthreshold leakage when oxde thckness s less than 15-20Å 102]. Unlke subthreshold leakage, whch only exsts n weakly turned-off transstors, gate leakage always exsts no matter whether the transstor s turned on or turned off 100]. Equaton (2.3) gves the expresson of the gate leakage 64]. I gate = W eff L eff 3 V ox 2 B 1 (1 ) V φox ox 2 A( ) exp V (2.3) Tox ox φox 8

24 where V ox s the potental drop across the thn oxde, Φ ox s the barrer heght for the tunnelng partcle (electron or hole), and T ox s the oxde thckness. A and B are physcal parameters gven by 64], 3 q A = and 16π 2 hφ ox 4 2mφ 2 ox B =, 3hq 3 where m s the effectve mass of the tunnelng partcle, q s the electronc charge, and h s the reduced Plank s constant. The oxde thckness T ox decreases wth the technology scalng to avod the short channel effects. Equaton (2.3) shows that gate leakage ncreases sgnfcantly wth the decrease of T ox. In ths work, we use BPTM (Berkeley Predctve Technology Models) 70nm technology 1] to mplement our desgns. Snce BPTM 70nm technology s characterzed by BSIM3.5.2, whch cannot correctly model gate leakage, gate leakage s omtted n ths work, and all the technques dscussed n Secton 2.2 am at subthreshold leakage reducton. 2.2 Technques for Leakage Reducton Leakage s becomng comparable to dynamc swtchng power wth the contnuous scalng down of CMOS technology. To reduce leakage power, many technques have been proposed, ncludng dual-v th, mult-v th, optmal standby nput vector selecton, transstor stackng, and body bas. 9

25 2.2.1 Dual-V th Assgnment Dual-V th assgnment s an effcent technque for leakage reducton. In ths method, each cell n the standard cell lbrary has two versons, low V th and hgh V th. Gates wth low V th are fast but have hgh subthreshold leakage, whereas gates wth hgh V th are slower but have much reduced subthreshold leakage. Tradtonal determnstc approaches for dual-threshold assgnment utlze the tmng slack of non-crtcal paths to assgn hgh V th to some or all gates on those non-crtcal paths to mnmze the leakage power. A B S C Co Fgure 2.2 An example dual-v th crcut. Fgure 2.2 gves an example dual-v th crcut. The bold lnes represent the crtcal paths. To keep the hghest crcut performance, all gates on the crtcal paths are assgned low V th (whte gates), whle some gates on those non-crtcal paths can be assgned hgh V th (black gates) to reduce the leakage snce there are tmng slacks left on those noncrtcal paths. Based on the technques used for determnng whch gates on non-crtcal paths should be assgned hgh V th, the dual-v th approaches can be bascally dvded nto 10

26 two groups: heurstc algorthms 45, 72, ] and lnear programmng algorthms 31, 70]. Among heurstc algorthms, the backtrackng algorthm 97, 98] used to determne the dual-v th assgnment only gves a possble soluton, not usually an optmal one (see example n Fgure 3.8 n Secton 3.4). Because the backtrackng search drecton for noncrtcal paths s always from prmary outputs to prmary nputs, the gates close to the prmary outputs have a hgher prorty for hgh V th assgnment, even though ther leakage power savngs may be smaller than those of gates close to the prmary nputs. In 96], dual-v th assgnment s descrbed as a constraned 0-1 programmng problem wth nonlnear constrant functons. Wang et al. use a heurstc algorthm based on crcut graph enumeraton to solve ths problem. Although ther swappng algorthm tres to avod the local optmzaton, a global optmzaton stll can not be guaranteed. Unlke a heurstc algorthm that can only guarantee a locally optmal soluton, a lnear programmng (LP) formulaton ensures a global optmzaton by descrbng both the objectve functon and constrants as lnear functons. Nguyen et al. 70] use LP to mnmze the leakage and dynamc power by gate szng and dual-v th devce assgnment. The optmzaton work s separated nto several steps. An LP s frst used to dstrbute slack to gates wth the objectve of maxmzng total power reducton. Then, an ndependent algorthm s needed to resze gates and assgn threshold levels. Ths means that n 70] LP stll needs the assstance of a heurstc algorthm to complete the optmzaton. The method of 31] also uses MILP to optmze the total power consumpton by dual-threshold assgnment and gate szng. Dual-V th assgnment can reduce leakage n both actve and standby modes snce some gates reman dle even when the whole crcut or system s n the actve mode. But 11

27 the effectveness of ths method depends on the crcut structure. A symmetrc crcut wth many crtcal paths leaves a much reduced optmzaton space for leakage reducton Mult-Threshold-Voltage CMOS A Mult-Threshold-Voltage CMOS (MTCMOS) crcut 12, 19, 103] s mplemented by nsertng hgh V th transstors between the power supply voltage and the orgnal transstors of the crcut 68]. Fgure 2.3(a) shows a schematc of a MTCMOS NAND gate. The orgnal transstors are assgned low V th to enhance the performance whle hgh- V th transstors are used as sleep controllers. In actve mode, SL s set low and sleep control hgh-v th transstors (MP and MN) are turned on. Ther on-resstance s so small that VSSV and VDDV can be treated as almost beng equal to the real power supply. In the standby mode, SL s set hgh, MN and MP are turned off and the leakage current s low. The large leakage current n the low-v th transstors s suppressed by the small leakage n the hgh-v th transstors. By utlzng the sleep control hgh-v th transstors, the requrements for hgh performance n actve mode and low statc power consumpton n standby mode can both be satsfed. To reduce the area, power and speed overhead contrbuted by the sleep control hgh- V th transstors, only one hgh-v th transstor s needed. Fgure 2.3(b) and 2.3(c) show the PMOS nserton MTCMOS and NMOS nserton MTCMOS. NMOS nserton MTCMOS s preferred because for any gven sze, an NMOS transstor has smaller on-resstance than a PMOS transstor 100]. Compared to the dual-v th technque, MTMOS can only reduce leakage n the standby mode and has addtonal area-, power-, and speed overheads. 12

28 VDD VDD SL MP SL MP VDDV VDDV VDD Vdd Hgh Vth Low Vth VSSV VSS VSSV SL MN SL MN VSS VSS (a) (b) (c) Fgure 2.3 Schematc of MTCMOS, (a) orgnal MTCMOS, (b) PMOS nserton MTCMOS, (c) NMOS nserton MTCMOS Adaptve Body Bas The threshold voltage of a short-channel NMOSFET can be expressed by the followng equaton 47]. V th ( φs Vbs φs ) DIBLVdd + VNW = Vth0 + γ θ (2.4) where V th0 s the threshold voltage wth a zero body bas, Φ S, γ and θ DIBL are constants for a gven technology, V bs s the voltage appled between the body and source of the transstor, V NW s a constant that models narrow wdth effect, and V dd s the supply voltage. Equaton (2.4) shows that a reverse body bas leads to an ncrease of the threshold voltage and a forward body bas decreases the threshold voltage. Leakage power reducton can be acheved by dynamcally adjustng the threshold voltage through adaptve body bas accordng to the dfferent operaton modes. In the actve mode, forward body (or zero) bas s used to reduce the threshold voltage, whch results n a hgher performance. In the standby mode, leakage power s greatly reduced by 13

29 the optmal reverse body bas, whch ncreases threshold voltages. The basc scheme of an adaptve-body-based nverter s shown n Fgure ]. Smlar to the MTCMOS, adaptve body bas 11, 13, 28, 54, 63, 90] only reduces the leakage power n the standby mode. Wth the contnuous technology scalng, the optmal reverse body bas becomes closer to the zero body bas and thus the technque of adaptve body bas becomes less effectve 44]. VDD standby Vbp actve VSS actve Vbn standby Fgure 2.4 Scheme of an adaptve body based nverter Transstor Stackng The two serally-connected devces n the off state have sgnfcantly lower leakage current than a sngle off devce. Ths s called the stackng effect 64, 65, 106]. In Fgure 2.5(b), when both M1 and M2 are turned off, V m has a postve value due to the leakage current flowng through M1 and M2. Assumng the bodes of M1 and M2 are both connected to the ground, V bs of M1 becomes negatve and leads to an ncrease of M1 s threshold voltage. At the same tme, V gs and V ds of M1 are both reduced. Accordng to equaton (2.2), the subthreshold leakage n M1 s decreased sharply and suppresses the 14

30 relatve larger leakage current n M2. On the contrary, V m n Fgure 2.4(a) s always equal to zero and has no effect on V bs, V gs and V ds of M and hence on ts subthreshold leakage. Vdd Vdd Vm M Vdd=Vds 0 0 M1 Vm M2 Vdd=Vds1+ Vds2 GND GND (a) (b) Fgure 2.5 Comparson of leakage for (a) one sngle off transstor n an nverter and (b) two serally-connected off transstors n a 2-nput NAND gate. Wth transstor stackng 40, 51, 55], by replacng one sngle off transstor wth a stack of serally-connected off transstors, leakage can be sgnfcantly reduced. The dsadvantages of ths technque are also obvous. Such a stack of transstors causes ether performance degradaton or more dynamc power consumpton Optmal Standby Input Vectors Subthreshold leakage current depends on the vectors appled to the gate nputs because dfferent vectors cause dfferent transstors to be turned off. From the llustraton n Secton 2.2.4, a 2-nput NAND gate has the smallest subthreshold leakage due to the stackng effect when the nput vector s 00. When a crcut s n the standby mode, one 15

31 could carefully choose an nput vector and let the total leakage n the whole crcut to be mnmzed 6, 22, 32, 52, 69, 84]. Gao et al. n 32] model leakage current by means of lnearzed pseudo-boolean functons. An exact ILP model was frst dscussed to mnmze leakage wth respect to a crcut s nput vector. A fast heurstc MILP was then proposed to selectvely relax some bnary constrants of the ILP model to make a tradeoff between runtme and optmalty Power cutoff Yu and Bushnell 108, 109] present a novel actve leakage power reducton method called the dynamc power cutoff technque (DPCT). The power supply to each gate s only connected n ts swtchng wndow, durng whch the gate makes ts transton wthn a clock cycle. The crcut s optmally parttoned nto groups based on the mnmal swtchng wndow (MSW) of gates and power cutoff transstors are nserted nto each group to control the power connecton of that group. Snce the power supply of each gate s only turned on durng a small tmng wndow wthn a clock cycle, sgnfcant actve leakage reducton can be acheved. One key of ths leakage reducton technque s the mplementaton of the cutoff transstors, whch can be ether mplemented by hgh-v th transstors as dscussed n Secton 2.2.2, or by low-v th transstors that are overdrven by a power supply larger than V dd for PMOS cutoff transstors or lower than V ss for NMOS cutoff transstors. 16

32 2.3 Technques for Dynamc Power Reducton Dynamc power s comprsed of logc swtchng power and gltch power, and can be expressed by the followng equaton 73]. P dyn 1 = C 2 L V 2 dd A F (2.4) To reduce dynamc power at a specfed operatng frequency F, we can ether reduce the dynamc power consumpton per logc transton whch s determned by loadng capactances C L, and power supply V dd, or reduce the number of logc transtons n the crcut represented by swtchng actvty A Logc Swtchng Power Reducton Dual power supply Reducng the supply voltage, or voltage scalng 15, 23, 27, 29, 107], s the most effectve technque for dynamc power reducton because dynamc power s proportonal to the square of the power supply. Smlar to the dual-v th approach, the dual V dd technque assgns hgh V dd to all the gates on the crtcal paths and low V dd to some of the gates on the non-crtcal paths. When a gate operatng at a lower V dd drectly drves a hgher V dd gate, a level converter s requred to avod the undesrable short crcut power n that hgher V dd gate due to the possble large DC current caused by the low voltage fann. Snce the level converters contrbute addtonal power, mnmzng the number of level converters s also mportant n voltage scalng 9]. 17

33 Level Converters Hgh Vdd Cluster Low Vdd Cluster FFs Combnatonal Logc FFs Fgure 2.6 Scheme of cluster voltage scalng. Clustered voltage scalng (CVS) 94] s an effectve voltage scalng technque. The basc dea s shown n Fgure 2.6 9]. The nstances of low V dd gates drvng hgh V dd gates are not allowed and level converters are only used to convert low voltage sgnals to hgh voltage as nputs to flp-flops (FFs) such that the total number of level converters s mnmzed. In contrast to CVS, extended clustered voltage scalng (ECVS) 95] allows level converson anywhere and the supply voltage assgnment to the gates s much more flexble. Thus greater dynamc power savng can be acheved compared to the CVS. The algorthm of ECVS s more complcated than that of CVS, snce CVS may use a backtrackng algorthm to determne just two clusters: one hgh V dd cluster and the other a low V dd cluster. Fgure 2.7 gves an example crcut whose dynamc power s optmzed by ECVS. The bold lnes represent the crtcal paths. 18

34 Hgh Vdd Gate Low Vdd Gate Level Converter FF Fgure 2.7 Example crcut for llustratng ECVS Gate szng Non-crtcal paths have tmng slack and the delays of some gates on these paths can be ncreased wthout affectng the performance. Snce the lengths of devces (transstors) n a gate are usually mnmal for a hgh speed applcaton, the gate delay can be ncreased by reducng the devce wdth. As a result, the dynamc power s accordngly decreased due to smaller loadng capactance C L, whch s proportonal to the devce sze. Gate szng s a technque that determnes devce wdths for gates. Tradtonal gate szng approaches use Elmore delay models n a polynomal formulaton. Heurstcsbased greedy approaches 23-25, 67, 78, 86, 101] can be used to solve such a polynomal problem. In general, a heurstc algorthm s relatvely fast but cannot guarantee a global optmal. The gate delay wth respect to ts devce sze, used n 23-25, 67, 78, 101], s generally gven by the followng equaton, 19

35 d C out = gd + C (2.5) GS where, d s the delay of the gate, gd s the ntrnsc gate delay of gate, C s a constant, C out s the fanout load of gate and GS s the wdth of the gate. The total loadng capactance C out s determned based on the fanout of the gate and s gven as 78], C out = ( C j FO ( ) wre j + C GS j ) (2.6) where, FO() s the set of gates that form the fan-outs for gate, C wrej s the capactance of the wre connectng gates and j and C s a constant. When gnorng the wrng capactance, Equaton (2.5) can be rewrtten as (2.7). GS j d = gd + k (2.7) GS j FO() where k =C C. A lnear programmng method s proposed 14] n whch a pecewse lnear delay model s adopted to acheve a global optmal soluton. A non-lnear programmng approach 59] gves the most accurate optmal soluton but at a cost of long run tmes Transstor szng The basc dea of transstor szng s exactly the same as that of gate szng except that n gate szng all the transstors n one gate are szed together wth the same factor but n transstor szng each transstor can be szed ndependently. Gate ntrnsc delay actually depends on the current and prevous nput vectors whch determne the nternal IO path (from the gate nputs to gate output). Dfferent nternal IO paths have dfferent on-resstances that cause dstnct path delays (gate ntrnsc delays). 20

36 For a gate on a crtcal path, only part of ts transstors contrbute the largest ntrnsc gate delay, so the remanng transstors stll can be szed to reduce the capactances. In gate szng, gd, the ntrnsc gate delay of gate n Equaton (2.5) and (2.7) s a fxed value whch makes t mpossble to dfferentate among the nternal IO paths. On the contrary, transstor szng 16, 43, 85, 105] explores the maxmum possble optmzaton space by szng transstors ndependently Gltch Power Elmnaton When transtons are appled at nputs of a gate, the output may have multple transtons before reachng a steady state (Fgure 2.9(a)). Among these, at most one s the essental transton, and all others are unnecessary transtons often called gltches or hazards. Because swtchng power consumed by the gate s drectly proportonal to the number of output transtons, gltches reportedly account for 20%-70% dynamc power 20]. Agrawal et al. 8] prove that a combnatonal crcut s mnmum transent energy desgn,.e., there s no gltch at the output of any gate, f the dfference of the sgnal arrval tmes at every gate's nputs remans smaller than the nertal delay of the gate, whch s the tme nterval that elapses after a prmary nput change before the gate can produce a change at ts output. Ths condton s expressed by the followng nequalty: t t 1 < (2.8) n d where we assume t 1 s the earlest arrval tme at nputs, t n s the most delayed arrval tme at another nput, and d s gate s nertal delay, as shown n Fgure 2.8. The nterval t n t 1 s referred to as the gate nput/output tmng wndow 74]. 21

37 Input Tmng Wndow t 1 t 2 t t n t 1 t 2 t n d t d d Output Tmng Wndow t 1 +d t n +d (a) a n-nput NAND gate (b) tmng wndow for the nputs and output of gate n (a) Fgure 2.8 Tmng wndow for an n-nput NAND gate. To satsfy nequalty (2.8), we can ether ncrease the nertal delay d (hazard flterng or gate/transstor szng) or decease the path delay dfference t n t 1 (path balancng). Fgures 2.9(b) and 2.9(c) llustrate these procedures for the gate of Fgure 2.9(a) Hazard flterng In hazard flterng, the nertal gate delay s ncreased to be larger than the tmng wndow by gate/transstor szng 7, 33, 104], so that the gate tself acts as a hazard flter. Fgure 2.9(a) shows that the tmng wndow s 2 unts, whch s larger than the nertal gate delay of 1 unt. Gltches are generated at ths gate s output. In Fgure 2.9(b), the nertal gate delay s ncreased from 1 unt to 3 unts for hazard flterng and gltches are removed. 22

38 2 1 (a) Gltch at the output of one NAND gate (b) Gltch elmnaton by hazard flterng (c) Gltch elmnaton by path delay balancng Fgure 2.9 Gltch elmnaton methods, (a) gltches at the output of a NAND gate, (b) gltch elmnaton by hazard flterng, and (c) gltch elmnaton by path delay balancng. 23

39 In 7], hazard flterng s appled to a full adder crcut and 42% dynamc power s reduced. The gltch-free crcut has gates whose speed s decreased to 20% of ther orgnal value but wth lttle reducton n overall speed of the crcut. Ths s because those gates are manly on non-crtcal paths and do not contrbute much to the crtcal path delay of the crcut Path balancng In path balancng, the tmng wndow, t n t 1, s reduced to be less than the nertal gate delay by nsertng delay elements 8, 46, 74] on the faster nput paths. In Fgure 2.9(c), a 1.5 unt delay s nserted on the faster nput path and reduces the tmng wndow to be 0.5 unts, whch s less than the nertal delay of the gate. Hence gltches are elmnated at the gate output. Snce delay elements contrbute addtonal power, the lowpower delay elements should be selected. Secton 3.3 gves a detaled dscusson of two popular delay elements. In 92], the authors use resstve-feed-through cells to mplement delays. Ths technque can elmnate gltch power but at a cost of huge area overhead whch s contrbuted by the large nserted resstance. Raja, et al. 75, 76] propose a path balancng technque based on a new varable-nput-delay logc or a new desgn style where logc gates have dfferent delays along I/O paths through them. Therefore, a gltch free crcut can be desgned wthout nsertng delay elements. But, the desgn of ths type of gates has technology lmtatons due to the amount of dfferental delay that can be realzed. Hazard flterng or gate/transstor szng, when used alone, can ncrease the overall nput-to-output delay snce some gates on crtcal paths have to ncrease ther nertal 24

40 delays to elmnate gltches. On the other hand, due to the upper bound of the gate delays n a specfc technology, gate delay cannot be ncreased wthout bound, so some of gltches cannot be removed n a crcut that has a large logc depth or large crtcal path delay. Hazard flterng or gate/transstor szng usually cannot guarantee 100% gltch elmnaton. Path balancng does not ncrease the delay, and guarantees to elmnate all gltches, but requres nserton of delay elements that contrbute power and area overheads. A combnaton of the two procedures 8, 46] can gve an optmum desgn Hazard-free crcut desgn In an asynchronous system, some control sgnals should be very clean and wthout any hazard (gltch). Hazard-free crcuts can be adopted to generate such sgnals. The multplexer crcut n Fgure 2.10(a) has a gltch at ts output when A changes from 1 to 0 whle both B and C are 1. By addng a redundant gate (gray shaded gate) n Fgure 2.10(b), ths hazard can be elmnated 18]. B A C B A C stuck-at-0 (a) (b) Fgure 2.10 Usng redundant mplcant to elmnate hazards, (a) a multplexer wth hazards, and (b) a redundant mplementaton of multpler free from certan hazards. Besdes the area and power overhead, an addtonal dsadvantage of ths method s that t ntroduces redundant stuck-at faults, such as the one shown n Fgure 2.10(b). Ths 25

41 fault cannot be tested. On the other hand, f ths fault s present then the crcut loses the hazard-suppresson capablty. Another dsadvantage s that such method cannot guarantee to elmnate all the hazards caused by multple nput-sgnal transtons. In 71], authors present a new method for two-level hazard-free logc mnmzaton of Boolean functons wth multple-nput changes. Gven an ncompletely-specfed Boolean functon, ths method produces a mnmal sum-of-products mplementaton, whch s hazard-free for a gven set of multple-nput changes, f such a soluton exsts. Overhead due to hazard-elmnaton s shown to be neglgble. 2.4 Power Optmzaton wth Process Varaton Leakage Mnmzaton wth Process Varaton Due to the exponental dependency of subthreshold leakage on some key process parameters, the ncreased presence of process parameter varatons n modern desgns has accentuated the need to consder the mpact of statstcal leakage current varatons durng the desgn process. Up to three tmes change n the amount of subthreshold leakage current s observed wth ±10% varaton n the effectve channel lengths of transstors 66, 79]. Statstcal analyss and estmaton of leakage power consderng process varaton are presented n 21, 80, 81]. A lognormal dstrbuton s used to approxmate the leakage current of each gate and the total chp leakage s determned by summng up the lognormals 21]. Varaton of process parameters not only affects the leakage current but also changes the gate delay, degradng ether one or both, power and tmng yelds of an optmzed 26

42 desgn. To mnmze the effect of process varaton, some technques 26, 61, 89] statstcally optmze the leakage power and crcut performance by dual-v th assgnment. Leakage current and delay are treated as random varables. A dynamc programmng approach for leakage optmzaton by dual-v th assgnment has been proposed 26], whch uses two prunng crtera that stochastcally dentfy pareto-optmal solutons and prune the sub-optmal ones. Another approach 61] solves the statstcal leakage mnmzaton problem usng a theoretcally rgorous formulaton for dual-v th assgnment and gate szng. Lu et al. 53] reduce leakage power by dual-v th desgn n a probablstc analyss method. They assume a lower V th, predetermned by the tmng requrements, and an optmal hgher V th s then selected n the presence of varablty. The probablstc model demonstrates that the true average leakage power s three tmes as large as that predcted by a non-probablstc model Gltch Power Optmzaton wth Process Varaton The delay of the gate s modeled as a fxed value n the determnstc methods dscussed n Secton In realty, however, process varatons make the delays to be random varables, generally assumed to have Gaussan dstrbutons. The gltch flterng condton of nequalty (2.8) cannot be guaranteed to be satsfed under process varaton. Especally n path balancng, the perfect satsfacton of nequalty (2.8) could easly be corrupted by a small varance of nertal gate delay. Hence the technque of path delay balancng s not effectve and gltches cannot be completely suppressed under process varaton. 27

43 Statstcal delay modelng s ntroduced n 39] for gate szng by non-lnear programmng. Gate delay s treated as a random varable wth normal dstrbuton. Hu 34-36] proposes a statstcal path balancng approach by lnear programmng. The results show that power varaton due to process varaton can be reduced. 2.5 Summary Ths chapter has ntroduced the feld of low power desgn. Varous technques to reduce power consumpton at the gate level are descrbed. Dual-V th assgnment s a very effcent method to reduce the subthreshold leakage power. Wth process varaton, subthreshold leakage ncreases exponentally, so a statstcal approach s proposed to mnmze the mpact of process varaton on leakage optmzaton. To reduce the unnecessary gltch power, hazard flterng and path balancng are used for gltch elmnaton. Although dynamc power s not senstve to the process varaton, the technque of path balancng becomes neffectve unless a statstcal delay model s adopted to reflect the real condtons. 28

44 CHAPTER 3 DETERMINISTIC MILP FOR LEAKAGE AND GLITCH MINIMIZATION The power dsspaton of a CMOS crcut comprses dynamc power, short crcut power and statc power. Leakage power s becomng a domnant contrbutor to the total power consumpton wth the contnung technology scalng. In the dynamc power, gltches as unnecessary sgnal transtons consume extra power. Compared to the other two power components, short crcut power can be gnored. In ths chapter, we propose a mxed nteger lnear programmng (MILP) formulaton to globally mnmze leakage power by dual-threshold desgn and elmnate gltches by path balancng. 3.1 Leakage and Delay As dscussed n Secton 2.1.2, subthreshold leakage exponentally depends upon the threshold (V th ). Increasng V th sharply reduces the subthreshold current, whch s gven by the followng expresson 42]: I sub W 2 Vgs V 1.8 th V ds = µ 0Cox VT e exp 1 exp (3.1) Leff nvt VT Spce smulaton results on the leakage current of a two-nput NAND gate are gven n Table 3.1 for 70nm BPTM CMOS technology 1] (V dd = 1V, Low V th = 0.20V, Hgh V th = 29

45 0.32V). The leakage current of a hgh V th gate s only about 2% of that of a low V th gate. If all gates n a CMOS crcut could be assgned the hgh threshold voltage, the total leakage power consumed n the actve and standby modes can be reduced by up to 98%, whch s a sgnfcant mprovement. Table 3.1 Leakage currents for low and hgh V th NAND gates. Input I leak (na) vector Low V th Hgh V th Reducton (%) However, accordng to the followng equaton, the gate delay ncreases wth the ncrease of V th. T pd dd (3.2) ( V V ) α dd CV th where α equals 1.3 for short channel devces 82]. Table 3.2 gves the delays of a NAND gate obtaned from Spce smulaton when the output fans out to varyng numbers of nverters. We observe that by ncreasng V th form 0.20V to 0.32V, the gate delay ncreases by 30%-40%. Table 3.2 Delays of low and hgh V th NAND gates. Number of Gate delay (ps) fanouts Low V th Hgh V th % ncrease