Interconnect Optimization for Deep-Submicron and Giga-Hertz ICs

Transcription

1 Interconnect Optmzaton for Deep-Submcron and Gga-Hertz ICs Le He UCLA Computer Scence Department Los Angeles, CA Outlne Background and overvew LR-based STIS optmzaton LR -- local refnement STIS -- smultaneous transstor and nterconnect szng Conclusons and future works

2 Upcomng Desgn Challenges Mcroprocessors for server computers um, 7.5M FETs, 450MHz um, ~100M FETs, >1GHz close to tape-out um, ~200M FETS, ~3.5GHz launch desgn n 2003 begn developng desgn tools n 2001 start research rght now We are movng faster than Moore s Law Crtcal Issue: Interconnect Delay Startng from 0.25um generaton, crcut delay s domnated by nterconnect delay Efforts to control nterconnect delay Processng technology: Cu and low K delectrc Desgn technology: nterconnect-centrc centrc desgn

3 Layout Desgn: Devce-Centrc versus Interconnect-Centrc Floorplanng Tmng Drven Placement Delay Budgetng Floorplanng Interconnect Plannng, and Interconnect Optmzaton Tmng Drven Placement Delay Budgetng Global Routng Global Routng wth Interconnect Optmzaton Detaled Routng Devce-Centrc Detaled Routng wth Varable Wdth and Spacng Interconnect-Centrc Interconnect Optmzaton Devce locatons and constrants: Delay Power Sgnal ntegrty Skew... Topology Szng Spacng Other crtcal optmzatons: buffer nserton, smultaneous devce and nterconnect szng Automatc solutons guded by accurate nterconnect and devce models

4 UCLA TRIO Package Integrated system for nterconnect desgn cadlab.cs.ucla.edu/~tro Effcent polynomal-tme optmal/near-optmal algorthms Interconnect topology optmzaton Optmal buffer nserton Optmal wre szng Wre szng and spacng consderng C Smultaneous devce and nterconnect szng Smultaneous topology generaton wth buffer nserton and wreszng zng Accurate nterconnect models 2-1/2 D capactance model 2-1/2 D nductance model Elmore delay and hgher-order delay models Improve nterconnect performance by up to 7! Used n ndustry, e.g., Intel Contrbutons to UCLA TRIO Package Integrated system for nterconnect desgn cadlab.cs.ucla.edu/~tro Effcent polynomal-tme optmal/near-optmal algorthms Interconnect topology optmzaton Optmal buffer nserton Optmal wre szng [ ICCAD 95, TODAES 96] Wre szng and spacng consderng C [ICCAD 97, TCAD 99] Smultaneous devce and nterconnect szng [ ICCAD 96, ISPD 98,TCAD 99] Smultaneous topology generaton wth buffer nserton and wreszng zng Accurate nterconnect models 2-1/2 D capactance model [DAC 97] (wth Cadence) 2-1/2 D nductance model [CICC 99] (wth HP Labs) Elmore delay and hgher-order delay models Improve nterconnect performance by up to 7! Used n ndustry, e.g., Intel

5 Outlne Background and overvew LR-based STIS optmzaton Motvaton for LR-based optmzaton Conclusons and future works Dscrete Wreszng Optmzaton [Cong-Leung, ICCAD 93] Gven: A set of possble wre wdths { W 1, W 2,, W r } Fnd: An optmal wre wdth assgnment to mnmze weghted sum of snk delays Wreszng Optmzaton

6 Domnance Relaton and Local Refnement W Domnance Relaton For all E, w(e ) w'(e ) W domnates W (.e., W W ) W Local refnement (LR) LR for E 1 to fnd an optmal wdth for E 1,, assumng wdths for other wres are fed wth respect to current wdth assgnment Sngle-varable optmzaton can be solved effcently Domnance Property for Dscrete Wreszng [Cong-Leung, ICCAD 93] If soluton W domnates optmal soluton W* W = local refnement of W Then, W domnates W* If soluton W s domnated by optmal soluton W* W = local refnement of W Then, W s domnated by W* A hghly effcent algorthm to compute tght lower and upper bounds of optmal soluton

7 Bound Computaton based on Domnance Property Lower bound computed startng wth mnmum wdths LR operatons on all wres consttute a pass of bound computaton on LR operatons can be n an arbtrary order New soluton s wder, but s stll domnated by the optmal soluton LR Upper bound s computed smlarly, but begnnng wth mamum wdths We alternate lower and upper bound computatons Total number of passes s lnearly bounded by sze of soluton space s Optmal soluton s often acheved n eperments Other Problems Solved by LR operaton Mult-source dscrete wreszng [Cong-He, ICCAD 95] Bundled-LR s proposed to speed up LR by a factor of 100 Contnuous wreszng [Chen-Wong, ISCAS 96] Lnear convergence s proved [Chu-Wong, TCAD 99] Smultaneous buffer and wre szng [Chen [Chen-Chang-Wong, DAC 96] Lagrangan relaaton s proposed to mnmze ma delay Why does LR operaton work? va a sequence of weghted delay mnmzatons Etended to general gates and multple nets [Chu-Chen Chen-Wong, ICCAD 98]

8 Outlne Background and overvew LR-based STIS optmzaton Motvaton of LR-based optmzaton Smple CH-program and applcaton to STIS problem Conclusons and future works Smple CH-functon [Cong-He, ICCAD 96, TCAD 99] f ( X ) m m = p = 0 q = 0 = 1 = 1, n ) ( b It ncludes the obectve functons for a number of works Dscrete or contnuous wre szng [Cong-Leung, ICCAD 93][Cong n Leung, ICCAD 93][Cong-He, ICCAD 95][Chen-Wong,ISCAS 96] Smultaneous devce and wre szng [Cong-Koh, ICCAD 94][Chen- Chang-Wong, DAC 96][Cong-Koh Koh-Leung, ILPED 96][Chu-Chen Chen-Wong, ICCAD 98] ( a p p s a smple CH-functon Varables and are postve, ether contnuous or dscrete Coeffcents a p and b q are postve constants Eamples: 2 3, ( f = a + b + cy g = a ) q q )

9 Domnance Property for Smple CH-Program Optmzaton problem to mnmze a smple CH- functon s a smple CH-program. The domnance property holds for smple CH-program w.r.t. the LR operaton. If X domnates optmal soluton X* X = local refnement of X Then, X domnates X* If X s domnated by optmal soluton X* X =local refnement of X Then, X s domnated by X* LR operaton can be used for all smple CH-programs Smple CH-functon [Cong-He, ICCAD 96, TCAD 99] f ( X ) m m = p = 0 q = 0 = 1 = 1, n ) ( b It ncludes the obectve functons for a number of works Dscrete or contnuous wre szng [Cong-Leung, ICCAD 93][Cong n Leung, ICCAD 93][Cong-He, ICCAD 95][Chen-Wong,ISCAS 96] Smultaneous devce and wre szng [Cong-Koh, ICCAD 94][Chen- Chang-Wong, DAC 96][Cong-Koh Koh-Leung, ILPED 96][Chu-Chen Chen-Wong, ICCAD 98] ( a p p s a smple CH-functon Varables and are postve Coeffcents a p and b q are postve constants Eamples: 2 3, ( f = a + b cy g a ) + = q Unfed and effcent soluton q )

10 General Formulaton: STIS Smultaneous Transstor and Interconnect Szng Gven: Crcut netlst and ntal layout desgn Determne: Dscrete szes for devces/wres Mnmze: α Delay + β Power + γ Area Ö It s the frst publcaton to consder smultaneous devce and wre szng for comple gates and multple paths STIS Obectve for Delay Mnmzaton R ( ) (, ) 0 ( ) R0 ( ) t X = F C0( ) F(, ) C1( + ),, R ( ) 0 ( ) R0 ( ) + G H ( ) C1( + ) : C 0 R 0 : unt-wdth resstance unt-wdth area capactance C 1 : effectve-frngng frngng capactance X =,,..., }: { 1 2 n Res = R0 R / Cap = C0 C * + (Cf( + C) = C0 C * + C1C dscrete wdths and varables for optmzaton It s a smple CH-functon under smple model assumng R 0, C 0 and C 1 are constants STIS can be solved by computng lower and upper bounds va LR operatons Identcal lower and upper bounds often acheved

11 SPICE-Delay reducton of LR-Based STIS STIS optmzaton versus manual optmzaton for clock net [Chen-et et al.,iscc 94]: 1.2um process, um wre, 154 nverters Two formulatons for LR-based optmzaton sgws smultaneous gate and wre szng sts smultaneous transstor and nterconnect szng manual sgws sts ma delay (ns) (-6.2%) 3.96 (-14.4) power(mw) (-24.3%) 46.3 (-24.2%) clock skew (ps) (-3.6) 40 (-11.7) Runtme (wre segmentng: 10um) LR-based sgws 1.18s, sts 0.88s HSPICE smulaton ~2100s n total STIS Obectve for Delay Mnmzaton R ( ) (, ) 0 ( ) R0 ( ) t X = F C0( ) F(, ) C1( + ),, R ( ) 0 ( ) R0 ( ) + G H ( ) C1( + ) : C 0 { 1 2 n R 0 : unt-wdth resstance unt-wdth area capactance C 1 : frngng capactance X =,,..., }: dscrete wdths and varables for optmzaton Over-smplfed for DSM (Deep Submcron) desgns It s a smple CH-functon under smple model assumng R 0,C 0 and C 1 are constants

12 R 0 s far away from a Constant! effectve-resstance R 0 for unt-wdth n-transstor sze = 100 c l \t t 0.05ns 0.10ns 0.20ns 0.225pf pf pf sze = 400 c l \t t 0.05ns 0.10ns 0.20ns 0.501pf pf pf R 0 depends on sze, nput slope t t and output load c l May dffer by a factor of 2 Usng more accurate model lke the table-based based devce model has the potental of further delay reducton. But easy to be trapped at local optmum, and to be even worse than usng smple model [Fshburn-Dunlop, ICCAD 85] Nether C 0 nor C 1 s a Constant Both depend on wre wdth and spacng Especally C 1 = C f +C s hghly senstve to spacng Effectve-frnge capactance (ff/um) Spacng (nm) C accounts for >50% capactance n DSM Proper spacng may lead to etra delay reducton But no estng algorthm for optmal spacng spacng E 1 E 1

13 STIS-DSM Problem to Consder DSM Effects STIS-DSM STIS-DSM problem Non-constant R0, R, C0C and C1C Fnd: devce szng, and wre szng and spacng soluton optmal w.r.t. accurate devce model and multple nets Easer but less appealng formulaton: sngle-net net STIS-DSM Fnd: devce szng, and wre szng and spacng soluton optmal w.r.t. accurate devce model and a sngle-net net Assume: ts neghborng wres are fed Outlne Background and overvew LR-based STIS optmzaton Motvaton: LR-based wre szng Smple CH-program and applcaton to STIS problem Bounded CH-program and applcaton to STIS-DSM problem Conclusons and future works

14 Go beyond Smple CH-functon f(x) m m n n a p (X) q = ( ) (b (X) ) p q p = 0 q = 0 = 1 = 1 It s a smple CH-functon f a p and b q are postve constants It s a bounded CH-functon f a p and b q are arbtrary functons of X a p and b q are postve and bounded L a a X U a and L p ( ) p Eamples: f (, ) = + 2, > e 1 2 ln p b q b ( X ) b Obectve functon for STIS-DSM problem q U q Etended-LR Operaton Etended-LR (ELR) operaton s a relaed LR operaton Replace a p and b q by ts lower or upper bound durng LR operaton. Make sure that the resultng lower or upper bound s always correct but mght be conservatve. Eample: f ( ) = a( ) + b( ) ELR for a lower bound s ELR for an upper bound s = L ELR = U ELR b L a b U U a L? L ELR * U ELR

15 General Domnance Property Theorem ([Cong( [Cong-He, ISPD 98, TCAD 99]) Domnance property holds for bounded CH-program wth respect to ELR operaton General Domnance Property Theorem ([Cong( [Cong-He, ISPD 98, TCAD 99]) Domnance property holds for bounded CH-program wth respect to ELR operaton m m n n a p (X) To mnmze f(x) = ( ) (b (X) p q p = 0 q = 0 = 1 = 1 If X domnates optmal soluton X* X = Etended-LR of X Then, X domnates X* If X s domnated by optmal soluton X* X = = Etended-LR of X Then, X s domnated by X* q )

16 Soluton to STIS-DSM Problem STIS-DSM can be solved as a bounded CH-program Lower bound computed by ELR startng wth mnmum szes Upper bound computed by ELR startng wth mamum szes Lower- and upper-bound computatons are alternated to shrnk soluton space Up-to to-date lower and upper bounds of R 0, C 0 and C 1 are used Uncertanty of R 0, C 0 and C 1 s reduced when the soluton space s shrunk There ests an optmal soluton to the STIS-DSM problem between fnal lower and upper bounds How large s the gap? Gaps between Lower and Upper Bounds Two nets under 0.18um technology: DCLK and 2cm lne STIS-DSM uses table-based based devce model and ELR operaton STIS uses smple devce model and LR operaton We compare average lower-bound wdth / average gap Transstors Wres DCLK STIS STIS-DSM STIS STIS-DSM sgws 5.39/ / / /0.025 sts 17.2/ / / / cm lne STIS STIS-DSM STIS STIS-DSM sgws 108/ / / /0.106 sts 126/ / / /0.091 Gap s almost neglgble About 1% of lower-bound wdth n most cases

17 Delay Reducton by Accurate Devce Model STIS-DSM versus STIS STIS-DSM uses table-based based devce model and ELR operaton STIS uses smple devce model and LR operaton DCLK STIS STIS-DSM sgws 1.16 (0.0%) 1.08 (-6.8%) sts 1.13 (0.0%) 0.96 (-15.1%) 2cm lne STIS STIS-DSM sgws 0.82 (0.0%) 0.81 (-0.4%) sts 0.75 (0.0%) 0.69 (-7.6%) STIS-DSM acheves up to 15% etra reducton Runtme s stll mpressve Total optmzaton tme ~10 seconds Delay Reducton by Wre Spacng Mult-net STIS-DSM versus sngle-net net STIS-DSM Test case: 16-bt bus each bt s 10mm-long wth 500um per segment ptch-spacng delay runtme sngle-net mult-net mult-net 1.10um (-39%) 2.0s 1.65um (-27%) 2.4s 2.20um (-8.7%) 2.3s 2.75um (-5.3%) 4.9s 3.30um (-8.6%) 7.7s Mult-net STIS-DSM acheves up to 39% delay reducton Sngle-net net STIS-DSM has a sgnfcant delay reducton f we compare t wth prevous wre szng formulatons

18 Conclusons Interconnect-centrc centrc desgn s the key to DSM and GHz IC desgns Interconnect optmzaton s able to effectvely control nterconnect delay Vald for general problems Problem formulatons should consder DSM effects e.g., LR-based optmzaton for STIS-DSM problem More s needed to close the loop of nterconnect- centrc desgn Interconnect plannng Interconnect optmzaton for nductance and nose Interconnect verfcaton, especally for pattern- dependent nose and delay...