Lecture 4: Adders. Computer Systems Laboratory Stanford University

Transcription

1 Lecture 4: Adders Computer Systems Laboratory Stanford Unversty Copyrght 2004 by Mark Horowtz (w/ Fgures from Hgh-Performance Mcroprocessor Desgn IEEE And Fgures from Bora Nkolc 1 Overvew Readng HP Adder paper EE271 Adder notes f you have not seen them before Chandrakasen -- Frst part of Chapter 10 Introducton Fast adders generally use a tree structure to take advantage of parallelsm to make the adder go faster. We wll talk about a couple of dfferent tree adders n ths lecture, and go over n more detal one of the adders. The adder descrbed n the paper s even more complex than the one n the notes, and at the end we wll talk a lttle about what t does These notes wll number the lsb as bt zero, whch s the conventon that I have used over the past 3 years. 2

2 Adders N-bt adder sums two N-bt quanttes (A & B plus perhaps Cn Sum= A xor B xor C Fundamental problem s rapdly calculatng carry n to bt (C All carres are dependent on all prevous nputs Therefore, least sgnfcant nput has fanout of N, mn delay log 4 N FO4 delays even f there were no logc. Most adders use Generate and Propagate logc to compute C G = A AND B (C out forced to be true P = A + B (C out = C n Also could use P = A XOR B, but OR s faster than XOR Can combne G and P nto larger blocks G 20 = G 1 + G 0 P 1 P 20 = P 1 P 0 3 Adder Cell Desgn Lots of XORs whch makes t nterestng desgn problem On of few places where pass-gate logc s an attractve Strange way to draw two nv 4

3 Pass-Gate Logc But even here t s stll not great 5 Lnear Solutons (see EE271 notes Smplest adder: rpple carry, faster adders: carry look-ahead, carry bypass... All of these work out carry several bts at a tme Best desgns have around 11 FO4 delays for 64 bts Useful for small adders (up to 16 bts and moderate performance longer adders Carry Bypass 6

4 Fgure s Not Qute Rght Need to get group carry outputs nto the global chan AND gate for group s really (Pg*Cn + Gg Groups need to calculate Pg and Gg Output of OR gate s the true nput to the next group 7 Carry Bypass or Carry Skp Adders Generally form mult-level carry chans Break bts nto group Rpple carry n all groups n parallel Rpple global carry Lots of trcks n choosng the number of bts for each group Equalze the crtcal path For the least sgnfcant ½ of the bts Want group to generate carry out, when C of the global chan wll arrve For the most sgnfcant ½ of the bts Also want for the last carry rpple n each group to occur at the same tme Means the groups should not be the same sze 8

5 Carry Select Calculate both answers for a group Select correct one Elmnates fnal carry rpple Setup P,G "0" "0" Carry Propagaton "1" "1" Carry Propagaton C o,k-1 Multplexer Co,k+3 Carry Vector Sum Generaton 9 Many Papers on These Adders But no one bulds them any more Why? They are all clever ways of buldng faster adders Whle usng lttle addton hardware Bypass logc requres few gates We have too many transstors Don t need to be frugal wth transstors Just buld the faster adder Interestng queston As power becomes a larger concern Wll these smpler adders reappear? 10

6 Logarthmc Solutons It would seem that to know C, we need C -1, So delay s lnear wth N A clever trck called prefx computaton lets us turn ths knd of problem nto logarthmc delay snce G and P are assocatve. Notaton s always an ssue I wll try to use the followng strategy A# means the sgnal A for group sze # n the th poston P = propagate (A+B G = generate (AB C = CarryIn to ths bt/group poston 11 Tree Logc For Logarthm Tme Adders Compute sngle bt values: (0 <= < N G = A B, P = A + B Compute two bt groups: (0 <= < N/2 G2 = G G 2 P 2+1 ; P 2 = P 2+1 P 2 Compute four bt groups: G4 = G G2 2 P2 2+1 P4 = P2 2+1 P2 2 (0 <= < N/4...(contnue up bnary tree to fnd all generates & propagates...(work down tree to fnd carry ns C4 2+1 = G4 2 + C8 P4 2 C4 2 = C8 C2 2+1 = G2 2 + C4P2 2 C2 2 = C4 C 2+1 = G 2 + C2 P 2 C 2 = C2 12

7 Many Types of Tree Adders Two basc parameters Radx Densty Radx Prevous secton showed a bnary tree, radx 2 Can buld other sze trees, but generally t s 2 or 4 But not always! Not always the same radx at each level Tree densty Prevous slde actually needed two trees One to generate PG nformaton One to dstrbute ths nformaton to all the consumers Needed second tree snce t dd not compute all PGs t could 13 Radx 4 PG and Carry Trees 14

8 CLA Adder Folded Tree 15 Dynamc Logc for 4 Bt CLA Block 16

9 8 Bt Bnary Tree Adder B 6 A 6 P 6 G 6 Sum =A XOR B XOR C C 7 B 5 A 5 P 5 G 5 P2 2 G2 2 C2 3 C 6 B 4 A 4 P 4 G 4 C 5 B 3 A 3 P 3 G 3 P2 1 G2 1 P4 0 C4 G4 1 C2 2 0 C4 = G4 + P4C8 0 C 4 B 2 A 2 P 0 G 2 C 3 B 1 A 1 P 1 G 1 P2 0 G2 0 G2 = G 1 + G 0 P 1; P2 = P 0 P 1 C2 1 C 2 B 0 A 0 C n P 0 G 0 G = AB; P = A+B C 1 C 0 17 Tree Adder 18

10 Tree Depth and Densty In addton to changng the radx of the adder Whch we have seen n our examples The other man varable s depth and densty of the trees The dfference between n and ln n s small for small numbers Often the bottom of the Carry trees are chopped Replaced wth lnear structures Can compute more PG results gong up the tree Forest of trees Don t need a very large (or any C tree In choppng trees Many adders use carry select at the fnal stage Compute two results, and use C4 or C8 to select rght result Group sze n the select s small for fanout reasons 19 Bnary Tree Adder Can elmnate the carry out tree by computng a group for each bt poston: P +7, G +7 P +6, G +6 P +5, G +5 P +4, G +4 P +3, G +3 P +2, G +2 P +1, G +1 P, G Each crcle has two gates, one that computes P for the group and one that computes G. Ths adder has a large number of wres, but can be very fast. In fact t provdes a way to estmate what the mn delay of an adder would be. 20

11 64 Bt Adder Delay Assume: The output load s equal to the load on each nput. Usng statc gates (nverter s the fastest gate Fnd delay from the effectve fanout: Smple approxmaton: Must compute A xor B xor C Cn (or LSB must fanout to all bts (FO 64 Total effectve fanout 64 * 2 ( for some logc n chan (3.5 FO4 delays More complex Look at effectve fanout of the path through adder P gates drve 3 gates, G gates drve 2. Effectve fanout s about 3.5/stage 1.5 (frst NAND/NOR 3.5^6 * 1sh (fnal Mux for Sum optmze for late select 5.7 FO4 (not really accountng for parastc delay correctly 21 Tree Adders: Radx 2 (A 0, B 0 (A 1, B 1 (A 2, B 2 (A 3, B 3 (A 4, B 4 (A 5, B 5 (A 6, B 6 (A 7, B 7 (A 8, B 8 (A 9, B 9 (A 10, B 10 (A 11, B 11 (A 12, B 12 (A 13, B 13 (A 14, B 14 (A 15, B 15 S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 S bt radx-2 Kogge-Stone Tree From Bora Nkolc 22

12 Tree Adders: Radx 4 (a 0, b 0 (a 1, b 1 (a 2, b 2 (a 3, b 3 (a 4, b 4 (a 5, b 5 (a 6, b 6 (a 7, b 7 (a 8, b 8 (a 9, b 9 (a 10, b 10 (a 11, b 11 (a 12, b 12 (a 13, b 13 (a 14, b 14 (a 15, b 15 S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 S bt radx-4 Kogge-Stone Tree From Bora Nkolc 23 Sparse Trees (a 0, b 0 (a 1, b 1 (a 2, b 2 (a 3, b 3 (a 4, b 4 (a 5, b 5 (a 6, b 6 (a 7, b 7 (a 8, b 8 (a 9, b 9 (a 10, b 10 (a 11, b 11 (a 12, b 12 (a 13, b 13 (a 14, b 14 (a 15, b 15 S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 S 15 From Bora Nkolc 16-bt radx-2 sparse tree wth sparseness of 2 (Han-Carlson 24

13 Full vs. Sparse Trees Sparse trees have less transstors, wres Less power Less nput loadng Recoverng mssng carres Rpple (extra gate delay Precompute (extra fanout Complex precompute can get nto the crtcal path Total Transstor Wdth [unt wdth/bt] Radx-4 Kogge-Stone Radx-4 2-Sparse Radx-4 4-Sparse -23.3% Adder Delay [FO4] From Bora Nkolc 25 Tree Adder wth Growng Fanout Ladner-Fscher (A 0, B 0 (A 1, B 1 (A 2, B 2 (A 3, B 3 (A 4, B 4 (A 5, B 5 (A 6, B 6 (A 7, B 7 (A 8, B 8 (A 9, B 9 (A 10, B 10 (A 11, B 11 (A 12, B 12 (A 13, B 13 (A 14, B 14 (A 15, B 15 S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 S 15 From Bora Nkolc 26

14 Other Sparse Trees Mathew, VLSI 02 From Bora Nkolc 27 Lng Adder Varaton of CLA p g = a = a b b Lng s equatons t = a + b g = a b G S = g + p G 1 = p G 1 H S = g + t 1 H 1 = t H + gt 1H 1 Lng, IBM J. Res. Dev, 5/81 From Bora Nkolc 28

15 Lng Adder Conventonal CLA: G Also: = g + p G 1 Lng s equaton shfts the ndex of pseudo carry G H = g + t 1 G 1 = g + t G 1 Propagates nformaton on two bts Doran, Trans on Comp 9/88 From Bora Nkolc 29 Lng Adder Conventonal radx-4 G + 3 = g3 + t3g2 + t3t2g1 t3t2t1g 0 Lng radx-4 H = 3 g = 3 g 3 + g + t t g 2 2 g + t 1 + t t 2 1 t g g + t 0 t t Reduces the stack heght (or wdth Reduces nput loadng g 0 From Bora Nkolc 30

16 Lng vs. CLA Energy [pj] R2 Lng R2 CLA R4 Lng R4 CLA Delay [FO4] From Bora Nkolc 31 R. Zlatanovc, ESSCIRC 03 Statc vs. Dynamc Compound Domno R2 Domno R2 Domno R4 Statc R2 Energy [pj] Delay [FO4] From Bora Nkolc 32

17 Example Look at a real desgn of a 64-bt adder (by Davd Harrs Dual-level carry-select adder, radx 4 (knd of Fully dual-ral domno Performs only addton (nput nverted n bypass network for subtract Delay (smulated = 6.4 FO4 delays Desgn Issues Adder archtecture Gate szng 33 Archtecture Logarthmc adder must generate up tree, then send carry down tree Carry Select adder cuts delay by only fndng carry nto block of 16 Meanwhle, sums must be computed for block assumng C n = 0, 1 Ths also requres a very fast 16 bt adder Reuse the same trck: buld a 16 bt carry select adder 16 bt adder can share generate and propagate logc wth man adder A,B PG2 PG4 PG16 C16 2-bt C4 C2 4-bt 16-bt Buffer A,B Sum R 64-bt 34

18 2-Bt Logc 2-bt Propagates & Generates P2 = P 0 P 1 = G2 = G 1 +G 0 P 1 = Speculatve Sums to bt b assumng carry n c: sumc b sum0 0 = sum1 0 = sum0 1 = sum1 1 = Fnal Result R 0 = R 1 = 35 4-bt Logc Carry n to 2 bt block b assumng cn to 16 bt block s c: cn2c b cn20 0 = cn21 0 = cn20 1 = cn11 1 = 4-bt Propagates and Generates g4 = p4 = 36

19 16-bt Logc Carry n to 4 bt block b assumng cn to 16 bt block s c: cn4c b cn40 0 = cn41 0 = cn40 1 = cn41 1 = cn40 2 = cn41 2 = cn40 3 = cn41 3 = 16-bt Propagates and Generates g16 = p16 = bt Logc Carry n to 16 bt block b assumng cn to 16 bt block s c: cn16 b 1 cn16 0 = cn16 1 = cn16 2 = cn16 3 = 1. Assumes no carry n to 64 bt adder. Ths mght be relaxed to handle subtracton at the expense of one more seres transstor n the crtcal path. 38

20 Domno Implementaton Notce that all the P, G, and C terms are monotonc! Only the sum select mux needs complementary nputs Opton 1: Generate sngle ral C, use statc mux to select sum Requres statc mux plus nverter for C, C_b mux select Good for area Delay = FO4 delays Opton 2: Generate dual ral P, G, C, use domno mux to select sum Requres twce as much hardware Good for speed Can produce dual-ral output n domno form for later crcuts Delay = 6.4 FO4 delays 39 Domno Trcks A bunch of domno trcks were used for maxmum speed Full utlzaton of statc as well as domno gates No clocked pulldowns on some domno gates Needs delayed precharge clocks, so make sure t s worth t Precharge necessary nternal nodes Predscharge other nternal nodes when all transstors are off Another speed hack that mght not be worth t No keepers Lvng dangerously, probably not a good dea Skewed for fast eval at cost of slow precharge Some of these conflct wth robust desgn prncples 40

21 Namng Conventons Very mportant to name all gates and nodes Node names necessary when debuggng nternal sgnals Gates needed for same reason Gate types: D1 = Domno wth evaluaton transstor D2 = Domno wth no evaluaton transstor H = Hgh skew CMOS L = Low skew CMOS Clocks: clk: normal clock dlclk: delayed low (fallng clock (for D2 delayed precharge ddlclk: doubly delayed low clock 41 2 Bt Adder Block 42

22 4 Bt Adder Block Bt Adder Block 44

23 64 Bt Adder Block 45 2-Bt Logc 2-bt Propagates & Generates P2 = P 0 P 1 = (A 0 +B 0 (A 1 +B 1 G2 = G 1 +G 0 P 1 = A 1 B 1 + A 0 B 0 (A 1 +B 1 Speculatve Sums to bt b assumng carry n c: sumc b sum0 0 = A 0 xor B 0 sum1 0 = ~(A 0 xor B 0 sum0 1 = A 1 xor B 1 xor (A 0 B 0 sum1 1 = A 1 xor B 1 xor (A 0 + B 0 Fnal Result R 0 = cn16? (cn21? sum1 0 : sum0 0 : (cn20? sum1 0 : sum0 0 R 1 = cn16? (cn21? sum1 1 : sum0 1 : (cn20? sum1 1 : sum0 1 46

24 4-bt Logc Carry n to 2 bt block b assumng cn to 16 bt block s c: cn2c b cn20 0 = cn40 cn21 0 = cn41 cn20 1 = g2 0 + p2 0 cn40 cn11 1 = g2 0 + p2 0 cn41 4-bt Propagates and Generates g4 = g2 1 + p2 1 g2 0 p4 = p2 0 p bt Logc Carry n to 4 bt block b assumng cn to 16 bt block s c: cn4c b cn40 0 = 0 cn41 0 = 1 cn40 1 = g4 0 cn41 1 = g4 0 + p4 0 cn40 2 = g4 1 + p4 1 (g4 0 cn41 2 = g4 1 + p4 1 (g4 0 + p4 0 cn40 3 = g4 2 + p4 2 (g4 1 + p4 1 (g4 0 cn41 3 = g4 2 + p4 2 (g4 1 + p4 1 (g4 0 + p bt Propagates and Generates g16 = g4 3 + p4 3 (g4 2 + p4 2 (g4 1 + p4 1 g4 0 p16 = p2 0 p2 1 p2 2 p2 3 48

25 64-bt Logc Carry n to 16 bt block b assumng cn to 16 bt block s c: cn16 b cn16 0 = 0 cn16 1 = g16 0 cn16 2 = g p16 1 (g16 0 cn16 3 = g p16 2 (g p16 1 (g