Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning

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1 Asa and South Pacfc Desgn Automaton Conference 2008 Varablty-Drven Module Selecton wth Jont Desgn Tme Optmzaton and Post-Slcon Tunng Feng Wang, Xaoxa Wu, Yuan Xe The Pennsylvana State Unversty Department of Computer Scence & Engneerng

2 Outlne Introducton Process Varaton and ts mpact on HLS Related work Varablty-Drven Module Selecton Performance/Power yeld Desgn Tme Approach Post-slcon Tunng Approach The combned approach Expermental Results Concluson

3 What s the problem? Process varaton has become a promnent concern as technology scales Devce and nterconnect process varatons ncrease wth shrnkng feature szes Intra-de 2,ntra σ VT Normalzed Frequency Inter-de % 0.18 mcron ~ X samples Normalzed Leakage (Isb) 2,nter σ VT (Source: K. Roy DAC05) (Source: Intel)

4 Impact on Hgh-Level Synthess HLS schedules operatons at dfference clock cycle and maps them to functon unts (FU). Tradtonally, each FU has a fxed latency value. However, under process varaton. CC1 CC2 CC3 CC Normalzed Delay Varablty (Sgma/Mean) MANCHESTER STATIC MANCHESTER DYNAMIC CARRY SELECT STATIC CARRY SELECT PASSGATE CARRY SELECT DYNAMIC KOGGE STONE RADIX 2 STATIC KOGGE STONE RADIX 4 STATIC KOGGE STONE R2 PASSGATE KOGGE STONE R2 DYNAMIC HAN CARLSON BRENT KUNG (Source: K. Bernsten, IBM)

5 Old Solutons Worst-case analyss: -- much larger varaton -- very pessmstc Source: IBM Requre a shft n the desgn paradgm, from today s determnstc to probablstc desgn

6 Probablstc Desgn Paradgm A holstc desgn paradgm shft to statstcal desgn ARCHITECTURE Varaton-aware archtecture V n V out MODULE GATE CIRCUIT Varaton-aware hgh level synthess? Statstcal tmng analyss Statstcal gate level optmzaton Statstcal technology mappng S n G DEVICE D n Process varaton modelng

7 Related work Hgh-level synthess s a well-studed problem Low power: T. Km TVLSI03, J. Cong ASPDAC08 Thermal: Seda ICCAD 06 Physcal nformaton can also be ntegrated nto HLS H. Zhou DAC05 Industry success story: HLS tool Catapult (Mentor Graphcs) BlueSpec nc. AutoESL Varaton-aware HLS W. Huang ICCAD06, T. Km ICCAD07, S. P. Mohanty VLSID 07 varaton-aware hgh level synthess s stll n ts nfancy

8 Outlne Introducton Process Varaton and ts mpact on HLS Related work Varablty-Drven Module Selecton Performance/Power yeld Desgn Tme Approach Post-slcon Tunng Approach The combned approach Expermental Results Concluson

9 Performance Analyss/Yeld Performance yeld: The probablty that the synthess hardware can work at a partcular clock rate A functonal unt: T = a0 a1 V a2 l a3 V th SB Syntheszed DFG: Sum operaton and Max operaton Performance Yeld of the DFG: Yeld delay (DFG) = Pr ob(tmax T _clock constra nt s) Yeld Yeld delay delay = = M = 1 M = 1, j Yeld Yeld delay delay ( b ) ( b ) Yeld delay( b ) j

10 Power Analyss/Yeld Power yeld: The probablty that the total power less than the power lmt A functonal unt: P = exp( b0 b1 V b2 l b3 V th SB ) Syntheszed DFG: Sum of the random varables Power Yeld of the DFG: Yeld power (DFG) = Pr ob(p tot P t arget constra nt s) P = P P new DFG old DFG old opt k P new opt k Yeld = Yeld( P new DFG ) Yeld( P old DFG )

11 Desgn Tme Approach- example CC1 CC2 CC3 CC4 PDF Clock Cycle Tme Clock Cycle Tme Adder 2 Yeld Adder 1 Delay = T p( t) dt 0 0 T1 T2 T3 t Worst case analyss: Adder2 s faster CCT=T1: Adder 1 s better CCT=T2: Adder 2 s better CCT=T3: Both Adders have the same yeld (100%)

12 Desgn Tme Approach- algorthm Input: ntal scheduled DFG, constrants, module lbrary Output: a syntheszed DFG wth optmzed power and satsfed performance constrants Meet constrant and Yeld ε Generate_multple_moves to_move_lst: fnd k moves to maxmze the total gan Gk If (Gk>0) Apply the moves, evaluate the power and performance yeld Evaluate the gan of each possble move, nsert the move wth hghest gan to to_move_lst 2 teratve steps: Performance yeld maxmzaton and power yeld mprovement under performance yeld constrant

13 Post Slcon Tunng Tunng chps after manufacturng, body basng technques by controllng threshold voltage Reverse body basng (RBB) reduces leakage power at the expense of slowng down crcuts Forward body basng (FBB) mproves performance at the expense of hgher leakage power Adaptve body basng (ABB) can tghten dstrbuton of the performance and power, mnmzng the yeld loss due to process varaton PDF Delay Dstrbuton Before ABB After ABB 0 t Delay

14 Post Slcon tunng Approach Decde the optmal body basng for a module selecton decson such that the power yeld s maxmzed under the performance constrants. mnmze: subject to: P sttot P( T max T constrant s) α clock second order conc program mnmze: subject to: ( a1 b a2) b c T T s s φ T ( n 1 T 1/ 2 ( α)( s s) s s ) ε T lmt vector s s to be determned, then Vsb

15 Jont optmzaton Approach The ntal body bas s zero Maxmze the power yeld under performance yeld constrants Iterates untl no mprovement can be obtaned Output a syntheszed DFG wth optmal body bas

16 Outlne Introducton Process Varaton and ts mpact on HLS Related work Varablty-Drven Module Selecton Performance/Power yeld Desgn Tme Approach Post-slcon Tunng Approach The combned approach Expermental Results Concluson

17 Experment set up Algorthms n C 90nm technology Sx hgh level synthess benchmarks: A 16-pont symmetrc FIR flter (FF) A 16-pont ellptc wave flter (EWF) An autoregressve lattce flter (ARF) An algorthm for computng dscrete cosne transform (DCT) A dfferental equaton solver (DES) An IIR flter (IIR)

18 Power Yeld Gan Desgn Tme Approach vs. worst case 90% performance yeld constrant 34% power yeld mprovement

19 Power Yeld Results Jont Approach vs. Desgn tme only 99% performance yeld constrant 38% power yeld 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% AR DCT DES EWF FF IIR Average mprovement DT JTS

20 Concluson As technology scales, process varaton has ncreasng mpact on performance and power varatons Tradtonal synthess technques belong to desgn tme approaches We propose a yeld drven module selecton wth jont desgn tme optmzaton and post-slcon tunng

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22 Compare wth Prevous Works Only consder tmng varablty Every step s stll determnstc Desgn tme approach