VLSI Design I; A. Milenkovic 1
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1 ourse dmnstraton PE/EE 47, PE 57 VLI esgn I L8: Pass Transstor Logc epartment of Electrcal and omputer Engneerng Unversty of labama n Huntsvlle leksandar Mlenkovc ( www. ece.uah.edu/~mlenka ) www. ece.uah.edu/~mlenka/cpe57- [dapted from Rabaey s gtal Integrated rcuts,, J. Rabaey et al. and Mary Jane Irwn ( www. cse. psu.edu/~m ) ] Instructor: leksandar Mlenkovc mlenka@ece.uah.edu Offce Hrs: MW 7:-8:, E7-L T: athma Tareen Offce Hrs: rday : : M, E46 URL: Text: gtal Integrated rcuts, nd Edton Rabaey et. al., (October) Lab: eptember 5 (posted), ue: October Hw: eptember 5 (posted), ue eptember 9 Proect: efault proect # posted! 9// VLI esgn I;. Mlenkovc ombnatonal Logc ells (cont d) OI The OI famly of cells wth ndex numbers or less = {OI, OI, O, O}; a,b,c={,} Vdd ell Type a a ab ab abc Total ells,,,,,,,,, Number of Unque ells 4 4 E E Z 9// VLI esgn I;. Mlenkovc 9// VLI esgn I;. Mlenkovc 4 tandard ell Layout Methodology OI Logc Graph Routng channel PUN sgnals =!( ( + )) What logc functon s ths? PN 9// VLI esgn I;. Mlenkovc 5 9// VLI esgn I;. Mlenkovc 6 VLI esgn I;. Mlenkovc
2 Two tck Layouts of!( ( + )) onsstent Euler Path n unnterrupted dffuson strp s possble only f there exsts a Euler path n the logc graph Euler path: a path through all nodes n the graph such that each edge s vsted once and only once. unnterrupted dffuson strp 9// VLI esgn I;. Mlenkovc 7 or a sngle poly strp for every nput sgnal, the Euler paths n the PUN and PN must be consstent (the same) 9// VLI esgn I;. Mlenkovc 8 onsstent Euler Path OI Logc Graph n unnterrupted dffuson strp s possble only f there exsts a Euler path n the logc graph Euler path: a path through all nodes n the graph such that each edge s vsted once and only once. =!((+) (+)) PUN or a sngle poly strp for every nput sgnal, the Euler paths n the PUN and PN must be consstent (the same) PN 9// VLI esgn I;. Mlenkovc 9 9// VLI esgn I;. Mlenkovc OI Layout VT s ata-ependent M M 4.5µ/.5 µ NMO.75 µ /.5 µ PMO ome functons have no consstent Euler path lke x =!(a + bc + de) (but x =!(bc + a + de) does!) 9// VLI esgn I;. Mlenkovc,: -> = =, : -> weaker =, :-> M PUN V G = V V nt M V G = V The threshold voltage of M s hgher than M due to the body effect (γ) V Tn = V Tn V Tn = V Tn + γ( ( φ + V nt ) - φ ) snce V of M s not zero (when V = ) due to the presence of nt 9// VLI esgn I;. Mlenkovc VLI esgn I;. Mlenkovc
3 tatc MO ull dder rcut! out =! n & (!!) (! &!) tatc MO ull dder rcut!um= out & (!!! n ) (! &! &! n ) n n n! out n!um n n! out n!um n n n out = n & ( ) ( & ) um=! out & ( n ) ( & & n ) 9// VLI esgn I;. Mlenkovc 9// VLI esgn I;. Mlenkovc 4 NMO Transstors n eres/parallel Prmary nputs drve both gate and source/dran termnals NMO swtch closes when the gate nput s hgh Y = Y f and PMO Transstors n eres/parallel Prmary nputs drve both gate and source/dran termnals PMO swtch closes when the gate nput s low Y = Y f and = + Y = Y f or Y = Y f or = Remember NMO transstors pass a strong but a weak Remember PMO transstors pass a strong but a weak 9// VLI esgn I;. Mlenkovc 5 9// VLI esgn I;. Mlenkovc 6 Pass Transstor (PT) Logc = Gate s statc a low-mpedance path exsts to both supply rals under all crcumstances N transstors nstead of N No statc power consumpton Ratoless drectonal (versus undrectonal) 9// VLI esgn I;. Mlenkovc 7 =.5/.5.5/.5.5/.5.5/.5 VT of PT N Gate = V out, V =, = V n, V =, = == Pure PT logc s not regeneratve- the sgnal gradually degrades after passng through a number of PTs (can fx wth statc MO nverter nserton) 9// VLI esgn I;. Mlenkovc 8 VLI esgn I;. Mlenkovc
4 fferental PT Logc (PL) PL Propertes N/NN = = PT Network Inverse PT Network OR/NOR =+ =+ = = OR/NOR fferental so complementary data nputs and outputs are always avalable (so don t need extra nverters) tll statc, snce the output defnng nodes are always ted to or through a low resstance path esgn s modular; all gates use the same topology, only the nputs are permuted. mple OR makes t attractve for structures lke adders ast (assumng number of transstors n seres s small) ddtonal routng overhead for complementary sgnals tll have statc power dsspaton problems 9// VLI esgn I;. Mlenkovc 9 9// VLI esgn I;. Mlenkovc PL ull dder PL ull dder n n n n!um!um um um n n n n! out! out n n out out n n 9// VLI esgn I;. Mlenkovc 9// VLI esgn I;. Mlenkovc NMO Only PT rvng an Inverter In = V V x = G = -V Tn V x does not pull up to, but V Tn Threshold voltage drop causes statc power consumpton (M may be weakly conductng formng a path from to ) Notce V Tn ncreases of pass transstor due to body effect (V ) 9// VLI esgn I;. Mlenkovc M M Voltage wng of PT rvng an Inverter In =.5/.5 x.5/.5.5/.5 ody effect large V at x - when pullng hgh ( s ted to and charged up close to ) o the voltage drop s even worse V x = - (V Tn + γ( ( φ f + V x ) - φ f )) Voltage, V 9// VLI esgn I;. Mlenkovc 4 In x =.8V.5.5 Tme, ns VLI esgn I;. Mlenkovc 4
5 ascaded NMO Only PTs oluton : Level Restorer = = G M = x = - V Tn G y M = = = x y M M Level Restorer on M r off = M x = = = M n = M wng on y = - V Tn - V Tn wng on y = - V Tn Pass transstor gates should never be cascaded as on the left Logc on the rght suffers from statc power dsspaton and reduced nose margns 9// VLI esgn I;. Mlenkovc 5 ull swng on x (due to Level Restorer) so no statc power consumpton by nverter No statc backward current path through Level Restorer and PT snce Restorer s only actve when s hgh or correct operaton M r must be szed correctly (ratoed) 9// VLI esgn I;. Mlenkovc 6 Voltage, V Transent Level Restorer rcut Response W/L =.5/.5 W/L n =.5/.5 W/L =.5/.5 W/L r =.75/.5 W/L r =.5/.5 W/L r =.5/.5 W/L r =./ Tme, ps node x never goes below V M of nverter so output never swtches Restorer has speed and power mpacts: ncreases the capactance at x, slowng down the gate; ncreases t r (but decreases t f ) 9// VLI esgn I;. Mlenkovc 7 oluton : Multple V T Transstors Technology soluton: Use (near) zero V T devces for the NMO PTs to elmnate most of the threshold drop (body effect stll n force preventng full swng to ) In = V In =.5V =.5V on sneak path off but leakng = V low V T transstors Impacts statc power consumpton due to subthreshold currents flowng through the PTs (even f V G s below V T ) 9// VLI esgn I;. Mlenkovc 8 oluton : Transmsson Gates (TGs ) Most wdely used soluton oluton : Transmsson Gates (TGs ) Most wdely used soluton = = = = = = = = = = ull swng bdrectonal swtch controlled by the gate sgnal, = f = 9// VLI esgn I;. Mlenkovc 9 = = ull swng bdrectonal swtch controlled by the gate sgnal, = f = 9// VLI esgn I;. Mlenkovc VLI esgn I;. Mlenkovc 5
6 Resstance of TG TG Multplexer 5 W/L p =.5/.5 V R n R p.5v V out In Resstance, kω 5 5 R p R n.5v R eq W/L n =.5/.5 In V out, V =!(In + In ) In In 9// VLI esgn I;. Mlenkovc 9// VLI esgn I;. Mlenkovc Transmsson Gate OR Transmsson Gate OR weak f! off on off on!! weak f an nverter 9// VLI esgn I;. Mlenkovc 9// VLI esgn I;. Mlenkovc 4 TG ull dder fferental TG Logc (PL) n = = um = = out N/NN OR/NOR 9// VLI esgn I;. Mlenkovc 5 9// VLI esgn I;. Mlenkovc 6 VLI esgn I;. Mlenkovc 6
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