FPGA Implementation of Pipelined CORDIC Sine Cosine Digital Wave Generator

Transcription

1 FPGA Implementaton of Ppelned CORDIC Sne Cosne Dgtal Wave Generator Navdeep Prashar 1 and Balwnder Sngh 1- Acadmc and Consultancy Servces Dvson, Centre for Development of Advanced Computng(C-DAC, Mohal, Inda nav.prashar@gmal.com, balwnder_cdacmohal@yahoo.com ABSTRACT The coordnate rotaton dgtal computer (CORDIC algorthm s well known teratve algorthm for performng rotatons n dgtal sgnal processng applcatons. Hardware mplementaton of CORDIC results ncrease n Crtcal path delay. Ppelned archtecture s used n CORDIC to ncrease the clock speed and to reduce the Crtcal path delay. In ths paper a hardware effcent Dgtal sne and cosne wave generator s desgned and mplemented usng Ppelned CORDIC archtecture. FPGA based archtecture s presented and desgn has been mplemented usng Xln 1.3 devce. KEYWORDS CORDIC, FPGA, Ppelned archtecture, Mcro -rotatons. 1. INTRODUCTION CORDIC stands for Coordnate Rotaton Dgtal Computer s a shft and add algorthm used to compute trgonometrc, hyperbolc, lnear and logarthmc functons. The CORDIC algorthm s frst ntroduced by Jack.E Volder n year 1959[1] and further etended by Walther []. The CORDIC algorthm has found ts varous applcatons such as pocket calculator, numercal coprocessor, and mage processng applcatons, drect dgtal synthess and analog dgtal modulaton. CORDIC operates manly n two modes for computaton of dfferent functons. These modes are known as rotaton mode and vector mode. In rotaton mode, the co-ordnate components of a vector and an angle of rotaton s gven and the co-ordnate component of orgnal vector, after rotaton through gven angle are computed. In vector mode, the coordnate component of a gven vector s gven and the magntude and angular argument of orgnal vector are computed. The CORDIC technque uses a one bt at a tme approach to make computaton to an arbtrary precson [3]. Typcally, these tables only one to two entres per bt of precson. CORDIC algorthms also use only rght shfts and addtons, mnmzng the computaton tme. It s hardware effcent algorthm because no multplers are presentng n CORDIC, to save gate requred mplementng on FPGA. If multpler s present, then cost and number of gates ncreases. The CORDIC algorthm has become a wdely used approach to elementary functon evaluaton where the slcon area s a prmary constrant. Ppelned CORDIC archtecture s mplemented n order to reduce teratve cycle and to ncrease the clock speed. Davd C. Wyld, et al. (Eds: CCSEA, SEA, CLOUD, DKMP, CS & IT 05, pp , 01. CS & IT-CSCP 01 DOI : /cst.01.43

2 436 Computer Scence & Informaton Technology (CS & IT Ths paper s organzed as follows. Secton : Introduces CORDIC Algorthm. Secton 3: Descrbes the Ppelned archtecture. Secton 4: Dscuss the smulaton and result Secton 5: Concluson.. CORDIC ALGORITHM The basc dea of CORDIC s to rotate the vector over gven angle. Each basc rotaton s realzed by usng shft and add operatons. A vector s rotated through fed number of steps called as teratons. If a vector v havng co-ordnates ( and y s rotated through an angle φ then obtanng a new vector wth co-ordnates where and y can be obtaned usng followng method. X = r cos θ, Y = r sn θ ' V ' cosφ y sn φ = = ' y y cosφ + sn φ Mcro rotaton φ s performed by vector at each teraton, so new vector s gven by y =.cosφ y. sn φ + 1 (3 = y.cosφ +. sn φ + 1 (4 Factorzng cos terms vector components gven as = cosφ ( y.tan φ +1 y = cosφ (y +.tanφ +1 As cosne s an even functon, so cos (α = cos (-α.then equaton (5 and (6 becomes + 1 = k ( y+ 1 = k (y + y d d (8 Where s the number of teraton requred by vector to reach the requred angle, k factor s gven as n 1 = k k = 0 Where k s CORDIC gan. Reducng orgnal gven rotaton to add shft algorthm gven as y + 1 = d y + 1 = y + d A new varable known as accumulator s gven as z = z d φ (5 (6 (7 (9 (1 ( (10 ( (1 d = ±1 ( d s the drecton of angle of rotaton Where φ = tan 1 s pre-computed and stored n table for dfferent value of.

3 Computer Scence & Informaton Technology (CS & IT PIPELINED ARCHITECTURE Dependng upon the applcaton, CORDIC Processor s mplemented n number of ways. The smple archtecture s seral archtecture consst of three adder/subtractor and two shfter wth a rom contanng lookup table. Seral archtecture perform one mcro rotaton for every clock cycle. Output s obtaned after n clock cycle. Snce seral archtecture uses n clock cycle for every rotaton hence t s very slow. Fgure 1 shows the seral archtecture. Fgure.1. Shows Seral archtecture Ppelned archtecture converts teratons n to ppelne phrases. It conssts of n cascaded blocks. The frst output of n stage CORDIC s obtaned after n clock cycle. Thereafter output s obtaned after every clock cycle. Ppelned archtecture havng shft regster that perform fed number of shfts every tme. Regsters are used to store the angle for a partcular mcro rotaton. Fgure shows the ppelned archtecture. Fgure. Shows Ppelned archtecture

4 438 Computer Scence & Informaton Technology (CS & IT Ppelned archtecture s much teraton at each stage. In ths paper a s stage ppelne sne cosne dgtal wave generator s developed performng specfc mcro-rotatons. Ths archtecture s fast than seral archtecture snce t doesn t requre any lookup table. It operates n crcular rotaton mode.sne and Cosne terms are gven by Xn = cosθ (13 Yn= snθ (14 The RTL vew of Ppelned CORDIC s shown n Fgure 3. faster than seral archtecture. Sgn z gves the drecton of Fgure 3. RTL vew of Ppelned CORDIC For any angle as an nput three outputs are generated sne functon, cosne functonn and eps.eps gves the error promty to requred angle. 4. SIMULATION AND RESULTS The code of dgtal wave generator s wrtten n VHDL and smulated usng ModelSm SE 6.3 f. The dgtal wave generator mplemented on XILINX SPARTAN 3 c3s00-5ft56 FPGA devce, usng XILINX 1.3. Area and tmng reports are gven for partcular target devce. Table 1 shows the devce utlzaton summary of dgtal wave generator usng CORDIC algorthm. Table1: Hardware Devce Utlzaton Summary S.N O 1 Logc Utlzaton Number of Slce Flp Used 166 Avalable 3840 Flops 3 Number of Slces Number of 4 nput LUTs 4 Number of bonded IOBs 5 Number of 1 8 BUFGMUXs

5 Computer Scence & Informaton Technology (CS & IT 439 Tmng reports nclude total tme delay for output to appear after gvng nput. At speed grade of - 5, desgn operates at mamum frequency of ns.The mnmum perod requre s 5.356ns. 4.1 Comparson of present Ppelned CORDIC Sne and Cosne wave generator wth prevous work. Present work s mplemented on XILINX SPARTAN c3s05ft56 FPGA devce. Thus, fnally comparson of present work wth prevous work s done as shown n Table. Table : Comparson of Present work wth prevous Reference paper Parameters Present work Reference Paper[4] No. of Slces Flp Flops No. of Slces No. of 4 nput LUTs No. of bonded IOBs Mamum Frequency MHz From Table, t s cleared that present desgn shows an mprovement n speed wth reducton n used resources on target devce. 5. CONCLUSION In ths paper, ppelnng technque s mplemented on CORDIC dgtal wave generator whch shows the better results n terms of speed and area utlzaton. The desgn operates on mamum frequency of MHz.A Consderable ncrease n speed made the desgn sutable for many wreless applcatons lke SDR and GSM. In ths work CORDIC has been mplemented n ppelne n order to avod teratve cycle that s output obtaned at every clock cycle. REFERENCES [1] J.E Volder. The CORDIC Trgonometrc Computng Technque, IRETrans.Electronc Computers, EC-8: , September [] J.S Walther. A Unfed Algorthm for Elementary Functons, AIFS Sprng Jont Computer Conference, pp ,1971. [3] P. K. Meher, J. Valls, T. B. Juang, K.Srdhan and K. Maharatna, 50 Years of CORDIC: Algorthms, Archtectures, and Applcatons, IEEE Transactons on Crcuts and Systems, Vol. 56, No.9, pp , 009. [4] Rajesh Mehra, Bndya kamboj FPGA Based Desgn of Dgtal Wave Generator Usng CORDIC: Algorthms,Int.J.Comp.Tech.Appl,Vol1 ( [5] Dobbs, M. Pascale, Usng CORDIC methods for Computatons n mcro-controllers, No. 9, 000. [6] R. Andraka, A survey of CORDIC algorthm for FPGA based computers, 6th Internatonal Symposum on Feld Programmable Gate Arrays, No., pp , 1998

6 440 Computer Scence & Informaton Technology (CS & IT [7] J. Duprat and J. M. Muller, The CORDIC Algorthm: New Results for Fast VLSI Implementaton, IEEE Transactons on Computers, Vol. 4, No., pp , [8] M. Ercegovac and L. Tomas, Redundant and On-Lne CORDIC: Applcaton to Matr Trangularzaton and SVD, IEEE Transactons on Computers, Vol. 39, No.6, pp , [9] HerberDawd, Henrch Meyr. VLSI Implementaton of the CORDIC algorthm usng redundant arthmetc, IEEE Internatonal symposum on crcuts and systems, 199. ISCAS 9. Proceedngs [10] B.Das, S.Banerjee. Unfed CORDIC based chp to realze DFT/DHT/DCT/DST, IEE Proc-Comput. Dgt. Tech., Vol. 149, No. 4, July 00. [11] J. G. Proaks and D. G. Manolaks,.Dgtal sgnal processng prncples, algorthms and applcatons, Delh: Prentce Hall, ed. nd, 008. [1] J. A. Lee, T. Lang, SVD by constant factor Redundant CORDIC,10th IEEE Symposum on Computer Arthmetc, No. 6, pp.64-71, Authors Bography Balwnder Sngh has obtaned hs Bachelor of Technology degree from Natonal Insttute of Technology, Jalandhar and Master of Technology degree from Unversty Centre for Inst. & Mcroelectroncs (UCIM, Punjab Unversty, Chandgah n 00 and 004 respectvely. He s currently servng as Senor Engneer n Centre for Development of Advanced Computng (CDAC, Mohal and s a part of the teachng faculty and also pursung Phd from GNDU Amrtsar. He has 7+ years of teachng eperence to both undergraduate and postgraduate students. Sngh has publshed three books and many papers n the Internatonal & Natonal Journal and Conferences. Hs current nterest ncludes Genetc algorthms, Low Power technques, VLSI Desgn & Testng, and System on Chp. Navdeep Prashar receved the B.Tech. (Electroncs and Communcaton Engneerng degree from the CT Insttute of Engneerng, Management and Technology, Jalandhar afflated to Punjab Techncal Unversty, Jalandhar n 010, and presently he s dong M.Tech. (VLSI desgn degree from Centre for Development of Advanced Computng (CDAC, Mohal and workng on hs thess work. Hs area of nterest s Embedded Systems, VLSI Desgn and Dgtal Sgnal Processng etc.