A Fast FPGA based Architecture for Determining the Sine and Cosine Value

Transcription

1 Proc. of Int. Conf. on Advances n Communcaton, Network, and Computng, CNC A Fast FPGA based Archtecture for Determnng the Sne and Cosne Value Atanu Dey, Tanma Bhattacharyya, Abul Hasnat and Santanu Halder Department of Computer Scence & Engneerng Government College of Engneerng & Tetle Technology, Berhampore, West Bengal, Inda Emal: atanud0@gmal.com, tanma.bhattacharyya0@gmal.com, abulhasnat.@gmal.com Department of Computer Scence & Engneerng Government College of Engneerng & Leather Technology, Kolkata, Inda Emal: sant.halder@gmal.com Abstract Ths paper ams to desgn a fast FPGA based archtecture for determnng the sne and cosne values usng Taylor s Seres. In ths work, a ppelned archtecture has been proposed for desgnng a fleble and scalable dgtal sne and cosne wave generator. An FPGA Based archtecture s mplemented n VHDL, syntheszed on Xln Spartan cs-ft6 FPGA kt smulated on ModelSm 6.c. The proposed archtecture gves accuracy of the computed sne and cosne values up to st bts n all cases and up to or bts for some cases n s clock cycles only whereas CORDIC archtecture needs clocks for bt accuracy. Trgonometrc waves s used n countless applcatons.e. Software Defned Rado (SDR). The proposed system s able to operate at the frequency of. MHz. Inde Terms FPGA, SDR, CORDIC, Sne, Cosne. I. INTRODUCTION There are plenty of applcatons whch requre dgtal wave generators. Wreless and moble systems are among the fastest growng applcaton areas; n partcular, Software Defned Rado (SDR) s currently a focus of research and development. An SDR allows performng many functons based on a sngle hardware platform, thus hghly reconfgurable resources for sgnal processng are needed, manly for modulaton and demodulaton of dgtal sgnals. Felds of development are ncreasng every day wth applcatons such as cell phones or mltary communcaton. There s a wdely used method, CORDIC [-4] whch s mplemented n most of the applcaton to generate dgtal sne and cosne waves. Although CORDIC algorthm computes trgonometrc angle values n a smple and faster way but t needs n number of clock cycles to get accuracy up to n th bt [-4]. So there s a need to develop a system whch would gve the better accuracy n less number of clock cycles. The proposed archtecture offers an alternatve, whch takes bts nput (for sngle precson format) and generates Sne and Cosne values n s clock cycles only and gves accuracy up to bts n all the cases (and for some cases bts or bts accuracy acheved) where as CORDIC needs clock cycle to compute the same Elsever, 4

2 accuracy. In the present work, The Taylor seres [-] s mplemented n VHDL based ppelned archtecture s proposed whch s syntheszed n Xln Spartan XCS0-PQ08 FPGA, smulated on the Modelsm 6.c from Mentor Graphcs Corporaton. Ths paper s organzed as follows: Secton II descrbes the estng CORDIC algorthm brefly. Secton III brefly eplans the Taylor seres [-]. Secton IV presents the top level desgn of proposed hardware. Secton V depcts the proposed system archtecture. Secton VI shows the epermental results and fnally secton VII concludes and remarks about some of the aspects analyzed n ths paper. II. EXISTING METHODOLOGY Coordnate Rotaton Dgtal Computer (CORDIC) s a well known algorthm used to appromate teratvely some transcendental functon [-4]. Let the startng vector s defned as v, ) and after n teratons, v0 moves to vn n antclockwse drecton by 0 as shown n fgure. 0 ( 0 y0 Fgure. Antclockwse rotaton of a vector v 0 to v n by θ 0 So, the vector v, y ) can be represented by Eq. and Eq.. n ( n n n y n 0 cos y0 sn () y 0 cos 0 sn () In each teraton, the vector perform a mcro-rotaton by, so the new vector s calculated wth a smlar functon cos y sn () y y cos sn (4) When the term cos s factorzed, components n the vector are descrbed by cos ( y tan ) () y sn ( y tan ) (6) tan s restrcted to, so multplcaton s converted n an arthmetc rght shft. It s also useful to use the dentty cos cos(arctan ) to defne the net varables. K cos(arctan ) / ( ) () d (8) Cosne s an even functon, therefore cos( ) cos( ). So () and (6) can be transformed nto y K ( y d ) () K ( y d ) () 6

3 Multplcaton by K s avoded by consderng t as a gan factor for all teratons. If n number of teratons are performed, then K s defned as the multplcaton of every K. K K I / ( ) () As the vector s ntalzed wth constant K, the vector components of each the teraton are smplfed to ( y d ) () y ( y d ) () On each teraton t s necessary to decde whether d or d. In order to make that decson, the dfference between the desred angle and the current angle s used. So a new varable know as accumulator s defned as: z z d arctan (4) The value of z 0 s the angle for whch sne and cosne are to be calculated. To know whether d should be postve or negatve, the followng rule s used: d sn z 0 d sn z 0 () The well known CORDIC by Volder [], s a classcal technque to compute both sne and cosne usng such decomposton nto mcro-rotatons. These rotatons are chosen n such a way that the value can be computed usng one adder or one subtractor and two shfters for each clock cycle. In vectorng mode, coordnates (, y 0 0 ) are rotated untl y 0 converges to zero. In rotaton mode, ntal vector (, y 0 0 ) starts algned wth the -as and s rotated by an angle of every cycle, so after n cycles, s obtaned angle. Fgure shows the CORDIC ppelne archtecture gven by Esbetan O. Garca et al[]. Fgure. Ppelned CORDIC Archtecture

4 Lke CORDIC, proposed mplementaton does not need to have Cosne values stored n memory, nstead t appromates the results, on each step of the teratve process. The proposed archtecture may be etended for a specfc resoluton wthout a consderable ncrease n the number of components used. III. PROPOSED METHODOLOGY Taylor seres [-] s a representaton of a functon as an nfnte sum of terms that are calculated from the values of the functon's dervatves at a sngle pont. Sne and Cosne value s calculated usng Eq. 6 and Eq. respectvely cos( ).. (6)! 4! 6! 8!!! sn( ).. ()!!!!!! Where As the present work takes nto consderaton tenth and eleventh power of for cosne and sne values respectvely, the Taylor seres reduces to Eq. 8 and Eq cos( ) (8)! 4! 6! 8!! sn( ) ()!!!!! As /(!), /(4!), /(6!), /(8! ) and /(! ) are constant so these values are stored n a look up table. The net secton descrbes VHDL mplementaton of Eq. 8 and Eq.. IV. TOP LEVEL DESIGN The top level desgn of proposed archtecture s shown n Fgure. The proposed archtecture takes one - bt value as nput. Then the system calculates the Sne and Cosne value usng the gven nput. Fnally, the system generates two -bt values Sne and Cosne respectvely. Fg. shows the top level desgn of the proposed archtecture. Fgure. The top level desgn of Proposed archtecture In the present work, f the nput angle s less than. degree results to less than n radan. Thus for any angle θ whch s less than. degree s drectly converted nto radan value and ts bt bnary representaton s used as nput and as output Y, Z s consdered as sn( ), cos( ) values respectvely. But f the nput angle s greater than. degree, then smply ( 0 ) s used as nput angle and ts bt bnary representaton of the angle n radan s used as nput to the system. Second nput s set to one to ndcate to alternate the output.e. Y, Z s consdered as cos( ), sn( ) respectvely because sn( 0 ) cos( ) or vce versa. Ths s done smply to avod normalzaton of nput and output values further.e. f the nput angle s less than. degree then ts correspondng radan value les n the range 0. Assumng decmal pont on left sde, correspondng bnary value s gven as nput and output s also taken as the gven bnary strng assumng decmal pont les n the left sde. Thus no normalzaton s needed. 8

5 V. SYSTEM ARCHITECTURE The proposed system archtecture s shown n Fgure 4 whch has a ppelned archtecture, consstng two adder, three subtractor and fve multpler for sne and cosne angle calculaton to get -bt accuracy all the tmes and to accuracy n some cases. The varous blocks of ths archtecture are descrbed net. All the nputs n each and every block are taken n bts and also all blocks forwards output n bts. Multpler : Fgure 4. Proposed system archtecture Multpler unt takes angle as nput (n radan) and calculates,, value as nput to all other multplers. It also forwards and as nputs to Subtractor.!! Multpler : Multpler takes and as nputs and calculates! and. Multpler forwards! value as nput to Multpler and also forwards 4 4,, and. Multpler forwards 4!! 4 and

6 values nput to Multpler and also forwards Multpler : Multpler takes 4 and 4 4! as nputs and calculates values nput to Multpler 4 and also forwards Multpler 4: Multpler 4 takes 6 and 6 6! as nputs and calculates values nput to Multpler and also forwards Multpler : Multpler takes 8 and 8 8! as nputs and calculates values nput to Multpler and also forwards Subtractor : and as nputs to Adder.! ,, and. Multpler forwards 6!! and as nputs to Subtractor.! 8 8,, and. Multpler4 forwards 8!! and as nputs to Adder.!!,, and. Multpler forwards!! It takes angle as drect nput (n radan) and also two more nputs follows And forwards the outputs f and f and as nputs to Subtractor.! (8)! f ()! f as nput to Adder. Adder : It takes two nputs f, f and calculates f and f as follows And forwards the outputs f and 4 f f (0)! 4 f4 f () 4! f as nput to Subtractor. Subtractor : It take two nputs f and f4 and calculates f and f6 as follows f f ()! f6 f 4 () 6! And forwards the outputs f and f6 as nput to Adder. Adder : It takes two nputs f, f6 and calculates f and f8 as follows 6 f f (4)!! 6 and 8 and and and and calculates f and f as!

7 f8 f6 () 8! And forwards the outputs f and f8 as nput to Subtractor. Subtractor : It take two nputs f and f 8 and calculates f and f as follows f 8 f (6)! f f8 ()! And fnally the output f s the calculated value of sn() and f as calculated value of cos( ) f nput angle n degree s less than. else f s the calculated value of cos( ) and f as calculated value of sn( ). The system archtecture shown n Fg. 4 s a ppelne archtecture whch computes sne and cosne values n only 6 clock cycle resultng faster computaton. VI. EXPERIMENTAL RESULTS The system for Sne Cosne value calculaton s mplemented usng VHDL, syntheszed for a Xln Spartan cs-ft6 wth smulaton on the Modelsm 6.c from Mentor Graphcs Corporaton. Eperment has been conducted on dfferent value n the range [0, ]. The proposed archtecture s capable to operate at the clock frequency of. MHz and takes only 6 clock cycles to get the result n bts. The devce utlzaton summary for the proposed archtecture for sne and cosne value computaton s gven n Table I. For comparson study of the proposed archtecture wth the standard CORDIC archtecture, the devce utlzaton summary of CORDIC archtecture smulated on a Xln Spartan cs-ft6 usng Xln ISE. s also gven n Table I. TABLE I. COMPARISON DEVICE UTILIZATION SUMMARY OF THE PROPOSED ARCHITECTURE AND CORDIC Proposed Method CORDIC Parameter Used % Used % Number of Slces Number of Flp Flops Number of 4 nput LUTs Number of bonded IOBs Number of GCLKs Mamum Frequency. MHz 4.6MHz Devce utlzaton summary s gven n Table I, t shows that the proposed archtecture takes (-46) number of Slces, 6 (-4) number of 4 nput LUTs less compared to that of CORDIC archtecture. But the proposed archtecture computes sne and cosne values up to st bt accuracy n only 6 clock cycle whereas CORDIC archtecture wll requre clock cycles to compute the same [-]. The FPGA based proposed system operates as fast as. MHz. The proposed archtecture has been tested usng Modelsm 6.c smulator and computaton accuracy acheved up to th bts or more. Table II shows the computed sne and cosne values usng the proposed archtecture whch clearly shows the accuracy up to th bts n only 6 clock cycles whereas to get accuracy up to th bts CORDIC archtecture needs clock cycles. Table II shows the computed sne and cosne values calculated usng proposed method. The Fgure (a) and (b) shows bt, bt and bt accuraces gven by the proposed system for sne and cosne values. For calculaton of sne(), the proposed system produces bt, bt and bt accuracy for.%, 8.66% and 0% cases respectvely and for cosne(), t produces bt, bt and bt accuracy for.%, 80%, and 0% cases respectvely. Fgure 6 shows the snapshot of sample output whch s smulated on ModelSm SE 6.c where nput angle (n radan) and output values are shown n red and yellow marked rectangles respectvely. 6

8 TABLE II. EXPERIMENTAL RESULTS FOR BOTH SINE AND COSINE VALUES Sl Angle (Degre e) Angle n Radan (-bt)* Sne()* Sne() (Decmal) Cosne()* Cosne() (Decmal)

9 *Decmal pont ests n the very left of the bnary strng VII. CONCLUSION The present work focuses manly to reduce the number of clock cycles requred to calculate the value of sne and cosne. The proposed system computes the sne and cosne values correctly up to bts for all the nputs or more n only 6 clock cycles where as CORDIC archtecture wll requre clock cycles for the same. But the system resource utlzaton by the proposed methodology s more or less same compared to that of the 6

10 (a) (b) Fgure. Shows accuracy acheved, and bts a) Sne values b) Cosne values Fgure 6. Snapshot of the ModelSm Smulaton CORDIC archtecture. Ths work may be etended to desgn a complete module havng memory unt for storng the data and a control unt to nterface the computaton unt and the memory unt. ACKNOWLEDGMENT Authors are thankful to the Government College of Engneerng and Tetle Technology, Berhampore, West Bengal for provdng nfrastructural facltes durng progress of the work. Dr. Santanu Halder s thankful to Government College of Engneerng and Leather Technology, Kolkata for kndly permttng hm to carry on the research work. REFERENCES [] J.E Volder, The CORDIC Trgonometrc Computng Technque, IRE Transactons on Electronc Computers, EC8:0-4, September. [] Esteban O. Garca, Rene Cumpldo, Mguel Aras, Ppelned CORDIC Desgn on FPGA for a Dgtal Sne and Cosne Waves Generator, rd Internatonal Conference on Electrcal and Electroncs Engneerng (ICEEE), 6. 64

11 [] P. K. Meher, J. Valls, T. B. Juang, K.Srdhan and K. Maharatna, 0 Years of CORDIC: Algorthms, Archtectures, and Applcatons, IEEE Transactons on Crcuts and Systems, Vol. 6, No., pp.8-0,. [4] Javer Valls, Martn Kuhlmann, and Keshar K. Parh, Evaluaton of CORDIC algorthms for FPGA desgn, Journal of VLSI sgnal Processng. Vol., no., pp. 0-,. [] Shenk Al, Calculus and Analytc Geometry Scott Foresman & Co; 4 th edton, July. [6] Mlton Abramowtz and Irene A. Stegun, Handbook of Mathematcal Functons Dover Publcatons Inc., New York, 6. [] Frank W.J. Olver, Danel W. Lozer, Ronald F. Bosvert and Charles W. Clark, The NIST Handbook of Mathematcal Functons, Cambrdge Unversty Press, Cambrdge, UK, 0. 6