A Novel, Low-Power Array Multiplier Architecture

Transcription

1 A Noel, Low-Power Array Multpler Archtecture by Ronak Bajaj, Saransh Chhabra, Sreehar Veeramachanen, MB Srnas n 9th Internatonal Symposum on Communcaton and Informaton Technology 29 (ISCIT 29) Songdo - FEZ ConensA, Icheon, Korea Report No: IIIT/TR/29/234 Centre for VLSI and Embeded Systems Technology Internatonal Insttute of Informaton Technology Hyderabad , INDIA September 29

2 A Noel, Low-Power Array Multpler Archtecture Ronak Bajaj, Saransh Chhabra, Sreehar Veeramachanen Internatonal Insttute of Informaton Technology- Hyderabad, Gachbowl, Hyderabad, 532, Inda E-mal :{ M B Srnas Department Electroncs and Communcaton Engg, Brla Insttute of Technology and Scences (BITS) Plan, Hyderabad Campus, Hyderabad, 578, Inda E-mal: srnas@bts-hyderabadacn Abstract Low power parallel array multpler s proposed for both unsgned and two s complement sgned multplcaton Modfed Baugh-Wooley multpler s further modfed and f nput numbers are not n two s complement form, proposed method makes the calculaton of two s complement of the number redundant, thus reducng delay Also power consumpton has been found to be less than that of modfed Baugh-Wooley multpler Y Y2 Y P P I INTRODUCTION Multplers are one of the most mportant arthmetc unts n mcroprocessors and DSPs and also a major source of power dsspaton Reducng the power dsspaton of multplers s key to satsfyng the oerall power budget of arous dgtal crcuts and systems Power consumed by multplers can be lowered at arous leels of the desgn herarchy, from algorthms to archtectures to crcuts, and deces Varous algorthms and multpler schemes hae been proposed tll date ncludng Hoffman et al [], Burton and Noaks [2], De Mor [3], and Gult [4] for poste numbers, and Baugh and Wooley [5] and Hwang [6] for numbers n two s complement form References [7-9] ge a good nsght nto the problem and desgn optmzatons at all the herarchy leels In ths paper, we focus on power reducton for both unsgned and sgned multplers For Sgned multpler, the modfed Baugh-Wooley algorthm (Fg (b) and 2) s extended to obtan a power effcent multpler Inputs are the nerted bts of two's complement representaton II UNSIGNED PARALLEL ARRAY MULTIPLIER The basc process of bnary array multplcaton noles the AND operaton of multplcand and multpler bts and subsequent addton as shown n Fg (a) for a 5 5 multpler NOR gates are used nstead of AND n accordance wth the DeMorgan s Law: AB = (A + B ) () From (), t s clear that f NOR gates are used, the nputs hae to be complmented Whle t takes 6 transstors to buld AND/OR gate, only 4 transstors are used for NOR/NAND gate Also, AND gate has an extra delay of T compared to NOR gate P2 Y3 P3 Y4 P4 P5 P9 P8 P7 P6 Fgure (a) Conentonal Unsgned Array Multpler Y Y P P Y2 P2 Y3 P3 Y4 P4 P5 P9 P8 P7 P6 Fgure (b) Modfed Baugh-Wooley two s complement sgned multpler [7] /9/$25 29 IEEE 9 ISCIT 29 Authorzed lcensed use lmted to: INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY Downloaded on March 25,2 at 5:3:4 EDT from IEEE Xplore Restrctons apply

3 x n- y m- P m+n- P m+n-2 (x n- y m-2 ) (x n-2 y m- ) P m+n-3 x n-2 y m-2 (x n- y m-3 ) (x n-3 y m- ) (x y m- ) P m+n-4 x 2 y m-2 P m- y m- x n- x y m-2 x y m-2 x 2 y 4 x y 4 x 2 y 3 x n-2 y 2 x n-2 y (x n- y 2 ) (x n- y ) (x n-y ) P n+ P n P n- y 4 y 3 y 2 y y x y 4 x y 3 x 2 y 2 x n-2 y x 3 x 2 x x y 3 x y 2 x 2 y P 3 x y 2 x y x 2 y P 2 x y x y P x x y P Fgure 2 Tabular form for modfed Baugh-Wooley two s complement sgned multpler Thus, for a m n multpler, the proposed method ntroduces m + n extra nerters along wth changng m n AND gates to m n NOR gates, effectely sang ( m n ( m + n) ) nerters or 2 *( m n ( m + n) ) transstors (Fg 2) ' ' ' ' P 9 ' ' ' ' ' P 8 ' ' ' ' ' P 7 ' ' ' ' ' P 6 ' ' ' ' Fgure 3 Proposed unsgned array multpler III PARALLEL TWO S COMPLEMENT SIGNED MULTIPLIER For m n parallel two s complment sgned multplcaton, m-bt multpler Y s represented as: Y = y m 2 m m 2 + y 2 = and n-bt multplcand X s represented as: ' Y' Y2' Y3' Y4' Y' P P 2 P 3 P 4 P 5 P X = x n 2 n n 2 + x 2 = Each of multpler bts s ANDed to eery multplcand bt to produce partal products and then summed to form the product P, m n m n m+ n 2 + p 2 = P = p = Y X m 2 n 2 m n = y m 2 + y 2 xn 2 + x 2 = = = + n 2 m 2 m n 2 m n 2 + j n + m + x n ym 2 x yj2 xn y 2 ym x 2 = j= = = Modfed Baugh-Wooley multpler uses AND and NAND gates to generate partal products The tabular form of modfed Baugh-Wooley multpler s shown n Fg 2 Its archtecture s shown n Fg (b) Now we see, out of m n partal products, majorty of the bts ( m n ( m + n 2)) are generated as a result of AND operaton whle only a few ( m + n 2) are a result of NAND operaton between multpler and multplcand bts In the proposed multpler, all the AND gates are replaced wth NOR gates Accordng to DeMorgan s Law, AB = (A +B ) (2) Ths makes t necessary to use nerted nputs (addton of ( m + n) nerters) and conert the remanng NAND gates to OR gates, as (AB) = (A +B ) These changes reduce ( m n 2*( m + n 2) ( m + n)) nerters n the proposed multpler (As an example, for a 6x6 multpler, 64 nerters are reduced) Thus, n comparson to the modfed Baugh-Wooley multpler (Fg (b)), area s reduced The probablty of 2 Authorzed lcensed use lmted to: INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY Downloaded on March 25,2 at 5:3:4 EDT from IEEE Xplore Restrctons apply

4 gettng a n both NOR and AND gate s same (e /4) and that for NAND and OR s also same (e 3/4) Thus the swtchng actty n the proposed multpler remans the same Snce less number of transstors are used, power dsspaton n the proposed multpler s bound to decrease Howeer due to the extra nerters added to obtan complemented nputs, there s extra T delay Howeer, f the nputs are not n two s complement form, further modfcatons can be done to produce the complemented nputs as explaned below Generaton of Inerted Bts If the nputs are not n two s complement form, for modfed Baugh-Wooley multpler, they hae to be ntally conerted nto two s complement form For ths, frst, sgn extenson to the modulus of the nput s done rrespecte of the sgn of the nput Ths s done by appendng s to the most sgnfcant sde of the number Then, f the number s poste, all the bts reman the same If the number s negate, all the bts are complemented and s added to the resultng number The process s llustrated n example below and shown n Fg 4(a) Example: Consder two nteger numbers 5 and -3 We shall use a 6 bt word length for llustraton Three bt bnary representaton of the modulus of gen ntegers s Multpler, 5 = Multplcand, 3 = Sgn Extenson done to 6 bts, Multplcand, 5 = Multpler, 3 = Multpler s poste so t would reman same e Multplcand s negate, so the bts are frst nerted, and then s added to ge the two s complement form for -3 e Instead of generatng nerted bts smply by complementng two s complement form of nput, a new way descrbed below s proposed whch makes the calculaton of two s complement of a negate number redundant Frst, sgn extenson s done to the modulus of the nput rrespecte of the sgn of the nput Ths s done by appendng s to the most sgnfcant sde of the number Now f the nput number s poste, bts are complemented If t s negate, the complement of ts two s complment form s obtaned by addng (2 m - ) to the number (Consderng sgn extenson s done to m bts, proof gen below) The process s shown n Fg 4(b) and llustrated n example gen below The tabular form representaton shown n Fg 2, now looks lke as shown n Fg 6 The block dagram s shown n Fg 5 Example: Consder two nteger numbers 5 and -3 We shall use a 6 bt word length for llustraton 3 bt bnary equalent of the modulus of gen ntegers s Multpler, 5= Multplcand, 3 = Sgn Extenson s done to 6 bts, Multplcand, 5 = Sgn extenson to m bts Addton of n= e Input n m nerters m bt Adder n=+e Requred nput Fgure 4(a) Conentonal method of generatng two s complement form ' ' ' ' S P9 Sgn extenson to m bts Addton of (2 m ) n= e Input n m bt Adder Requred nput n=+e m nerters Inerson of bts Fgure 4(b) Generaton of nput of proposed method ' ' ' ' ' P8 ' ' ' ' ' P7 X 2' ' ' ' ' P6 X ' ' ' ' ' Fgure 5 Proposed two s complement sgned array multpler X ' Y' Y2' Y3' Y4' Y ' P P P2 P3 P4 P5 2 Authorzed lcensed use lmted to: INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY Downloaded on March 25,2 at 5:3:4 EDT from IEEE Xplore Restrctons apply

5 (x n- +y m- ) (x n-2 +y m-2 ) (x 2 +y m-2 ) y m- x n- (y m-) (x +y m-2 ) y 4 y 3 y 2 y y x 3 x 2 x Inerson of bts by process descrbed n Fg 5 (y 4) (y 3) (y 2) (y ) x (y ) (x n-) (x 3) (x 2) (x ) (x ) (x +y m-2 ) (x 2 +y 3 ) (x n-2 +y ) (x +y 3 ) (x 2 +y 2 ) (x n-2 +y ) x n- +y m-2 x n- +y m-3 x n- +y x n- +y x n-2 +y m- x n-3 +y m- x +y m- P m+n- P m+n-2 P m+n-3 P m+n-4 P m- P n P n- (x +y 3 ) (x +y 2 ) (x 2 +y ) P 3 x 4 (x +y 2 ) (x +y ) (x 2 +y ) Fgure 6 Tabular form for proposed two s complement sgned array multpler P 2 (x +y ) (x +y ) P (x +y ) P Multpler, 3 = Multpler s poste so the bts are nerted to ge Multplcand s negate, so (2 6 - ) s added to to ge the complement of two s complement form for -3 e Proof for addton of (2 m -): As mentoned earler, requred nput for proposed multpler s complement of two s complement form of nput Steps noled n obtanng two s complement form of a number (sgn extended to m bts) are: ) Complement the number 2) Addton of As we know that, takng two s complement of a number twce ges the same number Let A s the gen m-bt sgn extended number and B s ts two s complement representaton B s requred number, then A A (A +) = B B B (B +) = A B = A = A + (2 m ) Thus for a negate number, calculaton of ts two s complement form and ts complement are taken care of smultaneously aodng the need to calculate ts two s complement form Ths not only mproes tme delay but also power dsspaton s reduced IV SIMULATION DETAILS AND RESULTS The analyss has been carred out on the proposed multplers by performng smulatons on HSpce and compared wth the exstng multplers Smulatons are performed for 6x6 bt multplers at 2V and at a frequency of 5 MHz Results shown n the Table I are for the partcular nputs x Smlar results can also be obtaned for other nputs TABLE I Power and Delay comparson of conentonal and proposed multplers Unsgned array multpler Conentonal Proposed Proposed/Conentonal Power (n Watt) 7277E E-4 92 Delay (n ns) Two s complement sgned array multpler Modfed Proposed/Modfed Proposed Baugh Wooley Baugh Wooley Power (n Watt) 56533E E Delay (n ns) V CONCLUSION In ths paper, a new approach for the desgn of parallel array multplers has been suggested AND gates n the exstng desgns hae been replaced wth NOR gates Where the numbers are not n two s complement form then they are nerted and gen as nput Results of the smulaton clearly show that the proposed multpler archtecture performs better than the exstng modfed Baugh-Wooley multpler REFERENCES [] J Hoffman, G Lacaze, and P Csllag, Iterate Logcal Network for Parallel Multplcaton, Electroncs Letters, ol 4, p 78, 968 [2] P Burton and DR Noaks, Hgh-Speed Iterate Multpler, Electroncs Letters, ol 4, p 262, 968 [3] R De Mor, Suggeston for an IC Fast Parallel Multpler, Electroncs Letters, ol 5, pp 5-5, Feb 969 [4] H Gult, Fully Iterate Fast Array for Bnary Multplcaton, Electroncs Letters, ol 5, p 263, 969 [5] R Baugh and BA Wooley, A Two s Complement Parallel Array Multplcaton Algorthm, IEEE Trans Computers, ol 22, no 2, pp,45-,59, Dec Authorzed lcensed use lmted to: INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY Downloaded on March 25,2 at 5:3:4 EDT from IEEE Xplore Restrctons apply

6 [6] K Hwang, Global and Modular Two s Complement Array Multplers, IEEE Trans Computers, ol 28, no 4, pp 3-36, Apr 979 [7] Wayne Wolf, (22) Modern VLSI Desgn: System-On-Chp Desgn 3 rd Edton, Prentce Hall, Upper Saddle Rer, NJ [8] MSElrabaa, IS Abu-Khater, MI Elmasry, Adanced Low- PowerDgtal Crcuts Technques, Kluwer Academc Publ, 997 [9] JMRabaey, AChandrakasan, and BNcolc, Dgtal Integrated Crcuts, (2 nd Edton) Prentce Hall, Authorzed lcensed use lmted to: INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY Downloaded on March 25,2 at 5:3:4 EDT from IEEE Xplore Restrctons apply