Power Efficient Design and Implementation of a Novel Constant Correction Truncated Multiplier

Transcription

1 APSIPA ASC 11 X an Power Effcent Desgn and Implementaton of a Novel Constant Correcton Truncated Multpler Yu Ren, Dong Wang, Lebo Lu, Shouy Yn and Shaojun We Tsnghua Unversty, Bejng E-mal: reneereny@gmal.com Tel: E-mal: doonny11@gmal.com Tel: Abstract Multplers are the fundamental arthmetc unts n most hgh speed sgnal and multmeda processng SoCs. In most cases, the fnal products of the multplcatons can be rounded wth lower precsons to avod the contnuous growth of word length whle the computaton carres on. A class of modfed multplers whch s called truncated multplers could sgnfcantly reduce the hardware cost and energy consumpton of the fnal mplementaton. Ths paper proposes an optmzed desgn of truncated multplers based on comprehensve analyss of statstcal propertes of the nput operands. The proposed desgn archtectures are modeled n Matlab codes usng Fxedpont toolbox and n RTL usng Verlog. The synthess results on FPGA show that the proposed multpler archtectures could acheve almost 37% reducton on logc resource and consume about 33% less dynamc power over the full-sze multplers. The average error can be reduced by 3% to 5% compared to the tradtonal constant correcton truncated multplers. Ths paper also explores the effcency of the proposed desgn n actual systems. Smulaton results show that the proposed desgn has obvous advantages on power effcency n applcatons aganst tradtonal truncated multplers. I. INTRODUCTION Multplcaton has been pervasvely used n Dgtal Sgnal Processng (DSP) applcatons lke flterng, convoluton and compresson [1]. For most DSP systems, the exact result wth full precson word length s not always reured and modfed desgn of standard multplers could reduce power dsspaton and ncrease throughput []. Snce a full-precson n n multpler computes the n output, roundng the result to n bts could avod the contnuous growth of word length whle the computaton carres on. Several approaches have been proposed n the lterature [-13] to reduce the area and mprove the latency on the crtcal path for the mplementaton of truncated multplers. The basc dea of these technues s to remove the least sgnfcant bts of the partal products and ntroduces adjustng crcut to compensate for the errors ntroduced. It was shown that by savng correspondng hardware n the multplers reducton array and fnal carry propagaton chan, the dynamc power dsspaton can also be proportonally reduced. However, the tradtonal schemes usually ntroduce a non-zero DC (Drect Current) component on the fnal product for all data nputs [7], whch would cause obvous mstakes when one of the multplcand s zero. To address ths ssue, ths paper proposes a new algorthm and correspondng hardware desgn of the truncated multpler based on tradtonal CCT (Constant Correcton Truncated) multpler algorthm [4], whch could further mprove the area and power effcency whle mnmzng the average and maxmum error by 3% to 5% compared to CCT multpler. The proposed scheme can be appled to both sgned and unsgned multplers [14],[15]. We also verfy the new scheme n desgnng power effcency multplers n several real applcatons, whch could reduce the logc resource by 36.9% than a 16-bt standard multpler and 9.3% than a 16-bt tradtonal CCT multpler. As to power dsspaton, the proposed scheme consumes 33.% less power than a standard multpler and 3.% less a tradtonal CCT multpler. II. OVERVIEW OF THE CONSTANT CORRECTION TRUNCATED MULTIPLIERS The CCT multpler s frst ntroduced n [4]. Assumng multplcaton of two n-bt numbers A and B results n a n-bt product P, whch are of the form n 1 n 1 n n+ n+ = B = 1 P = a = b p = A = Where a and b denote each bt of A and B, p denotes each bt of P. The relatonshp between the partal product bt π j =a j b and the fnal products p n the multplcaton matrx s shown as follows: Fg. 1 n n Multplcaton Matrx The n partal products π j are summed to compute the nbt product P, whch s usually then rounded to n bts n most applcatons to avod contnuous growth of the word-length of the results. Truncaton could also be conducted to reduce the area and power consumpton by omttng the least sgnfcant columns of the multplcaton matrx and summng only the (n+k) most sgnfcant columns,.e. column (n-k) to column Ths paper s supported by Chna Postdoctoral Scence Foundaton NO

2 (n-1) n Fg. 1. However, both the roundng and truncaton would ntroduce errors to the fnal products. To calculate the expected value of reducton error, t s assumed that each bt of the nput operand a or b has an eual probablty of beng 1 or, whch means each partal product btπ j has an expected value of 1/4, and the postonal weght s -n++j. The reducton error, whch s the sum of all partal products n columns to (n-k-1), s calculated as 1 1 E reduct = ( + 1) 4 (1) = Roundng error occurs because the (n+k)-bt product s rounded to n bts. To estmate the expected value of roundng error, t s assumed the probablty of each product bt, p n-1 to p n-k, beng one s.5, and the expected value of roundng error s 1 n 1 n 1 k E round = = (1 ) () = The expected value of the total error s the sum of reducton error E reduct and roundng error E round, and correcton constant s selected to be the nverse value of the total error wth (n+k) bts precson, whch s gven as below: n k round( + Etotal ) C = (3) n+ k where round(x) ndcates x s rounded to the nearest nteger. The expected value of the average error s gven as E avg = C + E total (4) Two assumptons are made n prevous conducton of (3) and (4). However, n prevous studes, we have found these assumptons were not reasonable. By smulatng A and B from to N -1 usng Fxed-Pont Toolbox n Matlab R9a and comparng the average error wth theoretcal results, we get an 8-bt multpler s shown n Fg. 3, and t s clearly that the output bt s not unformly dstrbuted. Probablty Bt Number Fg. 3 Probablty of an 8-bt Multpler Product Bt Beng One When t comes to the expected value of reducton error, t s also assumed that the probablty of each nput bt beng one s.5. Whle n fact, nput data s not dstrbuted unformly, ether. Takng the nput statstcal characterstc nto consderaton wll contrbute to more accurate estmaton of total error and mprovement n precson by selectng correcton constant wsely. Therefore, by followng ths dea, ths paper proposes a novel method to estmate the error and select correcton constant to solve the problems above. III. INPUT-STATISTICALLY-BASED (ISB) CCT MULTIPLIER A. Theoretcal Analyss The multplcaton matrx of Fg. 1 can be rearranged as the multplcaton array [] shown n Fg. 4, where we take n=8 for nstance. Fg. Average Error Comparson of 8-bt Multpler between Smulaton and Theoretcal result From Fg., we could see that there s bg devaton between theoretcal and true value for some values of k. The reason for the nconsstence s that the assumpton made to calculate the reducton and roundng error s unwarranted. In the tradtonal scheme [4], to calculate the expected value of roundng error, t s assumed that the probablty of each output bt beng one s.5, whle n fact, p s the sum of partal products n column and the partal products are relevant to multplcands. Smulaton result of p beng one n Fg. 4 An 8 8 Multpler Array

3 Where A represents AND gate, FA represents full adder, HA represents half adder n the pcture above. Let p(a ) and p(b j ) be the probabltes of nput bt beng one, p( be the probablty of partal product at column and row j beng one. Thus p(a ) p(b j ). Let p s ( denote the probablty that the sum bt of the adder at the th column and jth row s one and, p c ( the carry bt beng one. (=1-p( For N-, j=1, we have p c ( p( + 1, (5) p s ( ( + 1, + ( p( + 1, (6) For N-, j N-1 p c ( ( + 1, ( ( + 1, c ( s ( + 1, ( + ( ( + 1, ( (7) p s ( ( + 1, ( s ( + 1, c ( + ( s ( + 1, ( + ( p ( + 1, ( (8) s c As has been analyzed n Secton, the reducton error s the sum of the partal products n to (n-k-1) dagonals, whch gves a formula of the expected value of E reduct = 1 = j= p( j, The expected value of roundng error s the sum of product p n-1 to p n-k. n 1 s = Eround = p (, ) (1) And new form of correcton constant s calculated as n k round( + Etotal ) C = n+ k (11) B. Mathematcal Models of the ISB-CCT-Multpler Fg.5 llustrates the mathematcal model of the proposed truncated multpler. M and N are the nput length. L s the output length. K s number of addtonal partal product columns. Frst of all, analyze the M-bt and N-bt nput database and obtan the probablty of each nput bt beng one, P A and P B. Calculate output bt dstrbuton P C accordng to formula (5)-(8), and total error and correcton constant usng (9)-(11). Summng up the (L+k) most sgnfcant columns of multplcaton matrx and (L+k) bt correcton constant, and the fnal result s rounded to L bts. (9) C. Smulaton Results Smulate two multplcands from to N -1 (N=8) and compare the dfference between the true value and theoretcal value of total error usng tradtonal and proposed method. We can get Fg. 6 Dfference of Total Error between True Value and Theoretcal Value of an 8-bt Multpler Fg.6 shows that compared to tradtonal CCT, the proposed desgn estmates the error more accurately, and the dfference could be reduced by 3%-5%. IV. IMPLEMENTATION OF THE ISB-CCT MULTIPLIER Fg. 5 Model of nput-statstcally-based truncated multpler Fg. 7 A constant correcton truncated 8 8 multpler

4 Fg. 7 shows the archtecture of a constant correcton truncated 8 8 multpler wth k=. We have mplemented t n Verlog HDL and syntheszed usng Altera Quartus II 8. Web Edton wth EPS15F484C3 devce n Stratrx II famly. The synthess results show that 8-bt standard multpler (whch s not truncated, as shown n Fg. 4) needs 11 ALUTs and 48.35mW, and 16-bt standard multpler needs 51 ALUTs and 7.7mW. The detaled results for tradtonal CCT and proposed scheme are shown n Table I, where the hardware cost s measured n the number of LUTs (Look-Up- Tables) used ncludng both combnatonal and regster elements. The power consumpton s reported n the value of dynamc power dsspaton snce the statc power s the same wth dentcal FPGA devces. TABLE I LOGIC RESOURCE AND POWER COMPARISON BETWEEN TRADITIONAL CCT AND ISB-CCT MULTIPLIERS n=8 Logc Resource Dynamc Power (LUTs) (mw) k CCT ISB CCT ISB n=16 Logc Resource Dynamc Power (LUTs) (mw) k CCT ISB CCT ISB Compared to standard multpler, 8-bt ISB-CCT consumes 9.1% less logc resource, and 16-bt 36.9%. Besdes, the proposed scheme consumes 7.9% less logc resource for 8-bt and 9.3% less for 16-bt than tradtonal CCT multpler. As to power dsspaton, compared to standard multpler, ISB-CCT consumes 33.% lower power for 8-bt and 31.95% for 16-bt. As the proposed scheme occupes less logc resource, the power dsspaton s lower than tradtonal CCT wth 8-bt 17.4% less and 16-bt 3.%. V. APPLICATION OF THE TRUNCATED MULTIPLIER IN DSP SYSTEMS In ths secton, we apply the proposed truncated multplers to mplement the JPEG baselne seuental codec [16] and weghted flter to demonstrate the valdty of the proposed scheme. A. DCT/IDCT Smulaton Test mages are dvded nto 8 8 blocks for processng. - D DCT could be mplemented by performng 1-D DCT on each row, then performng t agan on each column, whch could be depcted as C=DPD T, where C s the matrx after transformaton, P s the mage for processng, and D s the DCT operator matrx. For IDCT, t s gven as P=D T CD. For comparson, performng DCT/IDCT usng the methods gven as below: 1) Matlab dct/dct functon; ) double precson operaton; 3) fxed-pont operaton usng standard multpler; 4) fxed-pont operaton usng Non-Correcton Truncated (NCT) multpler; 5) fxed-pont operaton usng tradtonal CCT multpler; 6) fxed-pont operaton usng ISB-CCT multpler. The PSNR (Peak Sgnal-to-Nose Rato) of the transformed pcture s shown n Table II. TABLE II PSNR USING DIFFERENT METHODS FOR DCT/IDCT(DB) Matlab func k 1 3 Double Precson NCT Standard Mul CCT ISB The data shows that n DCT/IDCT, the proposed archtecture has the same result as tradtonal CCT. The reason s that the novel scheme s based on the probablty dstrbuton of the nput operands, and t takes four multplcatons before obtanng the fnal results n DCT/IDCT. In fact, the ntermedate results has an unnformed dstrbuton for each bt, whch concdes wth the assumpton n tradtonal CCT. B. Weghted Flter Implementaton Now mplement the truncated multpler nto another applcaton n DSP, weghted flter, whch could remove nose n real mages. The flterng template s gven as 1/ 3 1/ 3 1/ 3 1/ 3 3/ 4 1/ 3 1/ 3 1/ 3 1/ 3 Takng double-precson operaton, standard multpler, non-correcton truncated multpler, tradtonal CCT multpler and ISB-CCT multpler to flter the nose n mages, and the PSNR s shown n Table III. TABLE III PSNR USING DIFFERENT METHODS FOR FILTERING(DB) Orgnal Nose.156 k 1 3 Double Precson.3445 NCT Standard Mul.3445 CCT ISB The flterng results show that the PSNR of the ISB-CCT s better than that acheved wth standard multplers and tradtonal CCT multplers, whch s due to the nonunformed dstrbuton of the nput operand bt n flterng

5 matrx. The novel algorthm takes the dstrbuton of nput bt nto consderaton, thus t estmates the error more accurately. The use of truncated multpler n the mplementaton of JPEG compresson usng DCT/IDCT and weghted flter has been examned and t s found that the proposed desgn has obvous advantages aganst tradtonal truncated multplers n applcatons based on non-unformed nput dstrbuton, whle the advantages are not as obvous n unformly dstrbuted nput cases. Under the same precson, the ISB-CCT multpler has a hgher PSNR than tradtonal CCT multpler. On the other hand, wthn a certan precson, the ISB-CCT multpler consumes less power than the tradtonal one. VI. CONCLUSIONS Ths paper proposes an optmzed desgn of truncated multplers based on comprehensve analyss of statstcal propertes of the nput operands. By gvng detaled error analyss on both reducton error and roundng error, we have revealed that the basc assumpton of the eualzed dstrbuton of the probablty of the bt n the partal products and the nput operands are not reasonable. Therefore, a new statstc scheme s ntroduced and an optmzed correcton algorthm s generalzed. We also propose the hardware mplementaton of the archtecture, verfy and synthesze the desgn on FPGA. At last, two applcatons n DSP are gven. In summary, our proposed multpler acheves lower error, less area, lower power dsspaton than tradtonal CCT multpler, and t could be used for the mplementaton of dgtal flter, DCT and IDCT hardware accelerators and so on. [9] C. Lemonds and S. S. Shett A low power 16 by 16 multpler usng transton reducton crcutry, n Proceedngs of the Internatonal Workshop on Low Power Desgn, pp ,1994. [1] E. de Angel and E. E. Swartzlander, Jr., Low power parallel multplers, n VLSI Sgnal Processng, IX., pp ,1997. [11] S.-R. Kuang and J.-P. Wang, Desgn of power-effcent confgurable Booth multpler, n IEEE Transactons on Crcuts and Systems I: Regular Papers, vol. 57, no. 3, pp , March 1 [1] Y. Lm, Sngle precson multpler wth reduced crcut complexty for sgnal processng applcatons, n IEEE Transactons on Computers, vol. 41, no. 1, pp , 199. [13] A. D. Booth, A sgned bnary multplcaton technue, Q. J. Mech. Appl. Math., vol. 4, pp. 36-4,1951. [14] C. R. Baugh and B. A. Wooley, A two s complement parallel array multplcaton algorthm, n IEEE Transactons on Computers, vol. C-, pp , 1973 [15] E. G. Walters III, M. G. Arnold, and M. J. Schulte, Usng truncated multplers n DCT and IDCT hardware accelerators, Proc. SPIE 55, 573(3). REFERENCES [1] U. M. Baese, Dgtal Sgnal Processng Wth Feld Programmable Gate Arrays. Berln, Germany: Sprnger,4. [] S. S. Kdamb F. El-Gubaly, A. Antonon, Area-effcent multplers for dgtal sgnal processng applcatons, n IEEE Transactons on Crcuts and Systems II: Analog and Dgtal Sgnal Processng, vol. 43, no., pp. 9-5, Feb [3] J. E. Stne and O. M. Duverne, Varatons on truncated multplcaton, n Proc. Euro. Symp. Dgtal Syst. Desgn, pp Sept [4] E. E. Swartzlander, Jr. Truncated multplcatons wth approxmate roundng, Conference Record of the Thrty-Thrd Aslomar Conference on Sgnals, Systems, and Computers, vol., pp , 1999 [5] C-H. Chand and R. K. Satzoda, A low error and hgh performance multpler-based truncated multpler, IEEE Transactons on VLSI Systems, vol. 18, no. 1, pp , Dec. 1 [6] M. J. Schulte and E. E. Swartzlander, Jr., Truncated multplcaton wth correcton constant, n VLSI Sgnal Processng, VI, Oct. 1993, pp [7] E. J. Kng and E. E. Swartzlander, Jr., Data-dependent truncaton scheme for parallel multplers, n Proc. 31 st Aslomar Conf. Sgnals, Syst. Comput., Nov. 1997, vol., pp [8] K. Brcherstaff, M. J. Schulte, and E. E. Swartzlander, Jr., Parallel reduced area multplers, n Journal of VLSI sgnal processng, vol. 9, pp , 1995.