FEATURES DESCRIPTIO APPLICATIO S. LTC V Software-Selectable Multiprotocol Transceiver TYPICAL APPLICATIO

Transcription

1 .V Software-Selectable Multiprotocol ransceiver FERES Software-Selectable ransceiver Supports: RS, RS, EI0, EI0-, V., V., X.21 Operates from Single.V Supply with V Rheinland of North merica Inc. Certified NE1, NE2 and B Compliant, Report No.: B/001/02 Complete DE or DCE Port with 2-Lead SSOP Surface Mount Package PPLICIO S Data Networking CS and DS Data Routers DESCRIPIO he LC 2 is a -driver/-receiver multiprotocol transceiver. he and form the core of a complete software-selectable DE or DCE interface port that supports the RS, RS, EI0, EI0-, V., V. or X.21 protocols. he operates from a.v supply and supplies provided by the. he part is available in a 2-lead SSOP surface mount package., LC and L are registered trademarks of Linear echnology Corporation. YPICL PPLICIO DE or DCE Multiprotocol Serial Interface with DB-2 Connector LL CS DSR DCD DR RS RXD RXC XC SCE XD D XD () XD B SCE () SCE B XC () XC B RXC (1) RXC B RXD () RXD B SG (2) SHIELD (1) RS () RS B DR () DR B DCD () DCD B DSR () DSR B CS () CS B LL (1) DB-2 CONNECOR

2 BSOLE XI RI GS W W W (Note 1) Supply Voltage... 0.V to.v V IN... 0.V to.v V EE... V to 0.V V DD... 0.V to V Input Voltage ransmitters... 0.V to ( + 0.V) Receivers... 1V to 1V Logic Pins... 0.V to ( + 0.V) Output Voltage ransmitters... (V EE 0.V) to (V DD + 0.V) Receivers... 0.V to (V IN + 0.V) Short-Circuit Duration ransmitter Output... Indefinite Receiver Output... Indefinite V EE... 0 sec Operating emperature Range CG... 0 C to 0 C IG... 0 C to C Storage emperature Range... C to 0 C Lead emperature (Soldering, sec) C W PCKGE/ORDER I FOR IO 1 V DD 2 D 1 DCE/DE OP VIEW D G PCKGE 2-LED PLSIC SSOP 2 V EE 2 GND 2 2 B 2 B / 21 / B 1 B 1 1 B 1 D/ V IN JMX = C, θ J = 0 C/ W, θ JC = C/ W ORDER PR NMBER CG IG Consult LC Marketing for parts specified with wider operating temperature ranges. ELECRICL CHRCERISICS he denotes specifications which apply over the full operating temperature range, otherwise specifications are at = 2 C. = V, V IN =.V, V DD = V, V EE = V for V.2,.V for V., V. (Notes 2, ) SYMBOL PRMEER CONDIIONS MIN YP MX NIS Supplies I CC Supply Current (DCE Mode, RS0, RS0-, X.21 Modes, No Load 2. m ll Digital Pins = GND or V IN ) RS0, RS0-, X.21 Modes, Full Load 0 m V.2 Mode, No Load 1 2 m V.2 Mode, Full Load 1 2 m No-Cable Mode µ I EE V EE Supply Current (DCE Mode nless RS0, RS0-, X.21 Modes, No Load 1. m Otherwise Noted, ll Digital Pins = GND or V IN ) RS0, X.21 Modes, Full Load (DE Mode) m RS0-, Full Load (DE Mode) 2 m V.2 Mode, No Load 1 m V.2 Mode, Full Load. m No-Cable Mode µ I DD V DD Supply Current (DCE Mode, RS0, RS0-, X.21 Modes, No Load 0.2 m ll Digital Pins = GND or V IN ) RS0, RS0-, X.21 Modes, Full Load 0.2 m V.2 Mode, No Load 1 m V.2 Mode, Full Load m No-Cable Mode µ I VIN V IN Supply Current (DCE Mode, ll Modes Except No-Cable Mode 0 µ ll Digital Pins = GND or V IN ) 2

3 ELECRICL CHRCERISICS he denotes specifications which apply over the full operating temperature range, otherwise specifications are at = 2 C. = V, V IN =.V, V DD = V, V EE = V for V.2,.V for V., V. (Notes 2, ) SYMBOL PRMEER CONDIIONS MIN YP MX NIS P D Internal Power Dissipation (DCE Mode, RS0, RS0-, X.21 Modes, Full Load 2 mw ll Digital Pins = GND or V IN ) V.2 Mode, Full Load mw Logic Inputs and Outputs V IH Logic Input High Voltage 2 V V IL Logic Input Low Voltage 0. V I IN Logic Input Current,,, D ± µ,,, DCE = GND 0 0 µ,,, DCE = V IN ± µ V OH Output High Voltage I O = m 2. V V OL Output Low Voltage I O = 1.m V I OSR Output Short-Circuit Current 0V V O V IN ±0 m I OZR hree-state Output Current = = = V IN, V O = 0V 0 10 µ = = = V IN, V O = V IN ± µ V. Driver V ODO Open Circuit Differential Output Voltage R L = 1.k (Figure 1) ± V V ODL Loaded Differential Output Voltage R L = 0Ω (Figure 1) 0.V ODO 0.V ODO V ±2 V V OD Change in Magnitude of Differential R L = 0Ω (Figure 1) 0.2 V Output Voltage V OC Common Mode Output Voltage R L = 0Ω (Figure 1) V V OC Change in Magnitude of Common Mode R L = 0Ω (Figure 1) 0.2 V Output Voltage I SS Short-Circuit Current V O = GND ±0 m I OZ Output Leakage Current 0.2V V O 0.2V, Power Off or ±1 ±0 µ No-Cable Mode or Driver Disabled t r, t f Rise or Fall ime C (Figures 2, ) 2 2 ns I (Figures 2, ) 2 ns t PLH Input to Output C (Figures 2, ) 0 ns 1 (Figures 2, ) 0 ns t PHL Input to Output C (Figures 2, ) 0 ns I (Figures 2, ) 0 ns t Input to Output Difference, t PLH t PHL C (Figures 2, ) 0 ns I (Figures 2, ) 0 1 ns t SKEW Output to Output Skew (Figures 2, ) ns V. Receiver V H Input hreshold Voltage V V CM V V V H Input Hysteresis V V CM V 0 mv I IN Input Current (, B) V V,B V ±0. m R IN Input Impedance V V,B V 0 kω t r, t f Rise or Fall ime (Figures 2, ) ns t PLH Input to Output C C L = 0pF (Figures 2, ) 0 0 ns I C L = 0pF (Figures 2, ) 0 0 ns

4 ELECRICL CHRCERISICS he denotes specifications which apply over the full operating temperature range, otherwise specifications are at = 2 C. = V, V IN =.V, V DD = V, V EE = V for V.2,.V for V., V. (Notes 2, ) SYMBOL PRMEER CONDIIONS MIN YP MX NIS t PHL Input to Output C C L = 0pF (Figures 2, ) 0 0 ns I C L = 0pF (Figures 2, ) 0 0 ns t Input to Output Difference, t PLH t PHL C C L = 0pF (Figures 2, ) 0 1 ns I C L = 0pF (Figures 2, ) 0 21 ns V. Driver V O Output Voltage Open Circuit, R L =.k ± ± V V Output Voltage R L = 0Ω (Figure ) ±. V R L = 0Ω (Figure ) 0.V O I SS Short-Circuit Current V O = GND ±0 m I OZ Output Leakage Current 0.2V V O 0.2V, Power Off or ±0.1 ±0 µ No-Cable Mode or Driver Disabled t r, t f Rise or Fall ime R L = 0Ω, C L = 0pF (Figures, ) 2 µs t PLH Input to Output R L = 0Ω, C L = 0pF (Figures, ) 1 µs t PHL Input to Output R L = 0Ω, C L = 0pF (Figures, ) 1 µs V. Receiver V H Receiver Input hreshold Voltage V V H Receiver Input Hysteresis 2 0 mv I IN Receiver Input Current V V V ±0. m R IN Receiver Input Impedance V V V 0 kω t r, t f Rise or Fall ime C L = 0pF (Figures, ) ns t PLH Input to Output C L = 0pF (Figures, ) ns t PHL Input to Output C L = 0pF (Figures, ) ns t Input to Output Difference, t PLH t PHL C L = 0pF (Figures, ) 0 ns V.2 Driver V O Output Voltage Open Circuit ± V R L = k (Figure ) ± ±. V I SS Short-Circuit Current V O = GND ±0 m I OZ Output Leakage Current 0.2V V O 0.2V, Power Off or ±1 ±0 µ No-Cable Mode or Driver Disabled SR Slew Rate R L = k, C L = 200pF (Figures, ) 0 V/µs t PLH Input to Output R L = k, C L = 200pF (Figures, ) µs t PHL Input to Output R L = k, C L = 200pF (Figures, ) µs V.2 Receiver V HL Input Low hreshold Voltage 0. V V LH Input High hreshold Voltage 2 V V H Receiver Input Hysterisis V R IN Receiver Input Impedance V V V kω t r, t f Rise or Fall ime C L = 0pF (Figures, ) ns t PLH Input to Output C L = 0pF (Figures, ) 0 0 ns t PHL Input to Output C L = 0pF (Figures, ) 0 00 ns

5 ELECRICL CHRCERISICS Note 1: bsolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: ll currents into device pins are positive; all currents out of device are negative. ll voltages are referenced to device ground unless otherwise specified. Note : ll typicals are given for = V, V IN =.V, V DD = V, V EE = V for V.2,.V for V., V. and = 2 C. YPICL PERFOR CE CHRCERISICS W 0 RS0, X.21 in DCE Mode (hree V. Drivers with Full Load) I CC vs Data Rate 2 = 2 C = 2 C = 2 C RS0- in DE Mode (wo V. Drivers with Full Load) I EE vs Data Rate V.2 in DCE Mode (hree V.2 Drivers with Full Load) I DD vs Data Rate I CC (m) 1 0 I EE (m) I DD (m) D RE (kbd) 2 G D RE (kbd) D RE (kbd) 2 G02 2 G0 I CC (m) 0 0 RS0, X.21 in DCE Mode (hree V. Drivers with Full Load) I CC vs emperature 0 0 I EE (m) RS0- in DE Mode (wo V. Drivers with Full Load) I EE vs emperature EMPERRE ( C) EMPERRE ( C) EMPERRE ( C) I DD (m) V.2 in DCE Mode (hree V.2 Drivers with Full Load) I DD vs emperature 2 G0 2 G0 2 G0

6 PI F CIO S (Pin 1): Positive Supply for the ransceivers. Connect to Pin on or to V supply. Connect a capacitor to ground. V DD (Pin 2): Positive Supply Voltage for V.2. Connect to V DD Pin on or V supply. Connect a capacitor to ground. (Pin ): L Level Driver 1 Input. (Pin ): L Level Driver 2 Input. (Pin ): L Level Driver Input. (Pin ): CMOS Level Receiver 1 Output. Receiver outputs have a weak pull up to V IN when high impedance. (Pin ): CMOS Level Receiver 2 Output. (Pin ): CMOS Level Receiver Output. D (Pin ): L Level Driver Input. (Pin ): CMOS Level Receiver Output. (Pin ): L Level Mode Select Input 0. Mode select inputs pull up to V IN. (Pin ): L Level Mode Select Input 1. (Pin 1): L Level Mode Select Input 2. DCE/DE (Pin ): L Level Mode Select Input. V IN (Pin ): Positive Supply for the Receiver Outputs. V V IN.V. Connect a capacitor to ground. D/ (Pin 1): Receiver Inverting Input and Driver Inverting Output. B (Pin 1): Receiver Noninverting Input. (Pin 1): Receiver Inverting Input. B (Pin 1): Receiver 2 Noninverting Input. (Pin ): Receiver 2 Inverting Input. / B (Pin 21): Receiver 1 Noninverting Input and Driver Noninverting Output. / (Pin ): Receiver 1 Inverting Input and Driver Inverting Output. B (Pin 2): Driver 2 Noninverting Output. (Pin ): Driver 2 Inverting Output. B (Pin 2): Driver 1 Noninverting Output. (Pin 2): Driver 1 Inverting Output. GND (Pin 2): Ground. V EE (Pin 2): Negative Supply Voltage. Connect to V EE Pin 1 on or to V supply. Connect a capacitor to ground.

7 BLOCK DIGR W ES CIRCIS 1 2 V EE V DD 2 2 GND R L 2 V OD 2 B R L V OC B 2 F01 2 B Figure 1. V. Driver est Circuit 2 / k k k k k S 21 / B B R L 0Ω C L 0pF C L 0pF B R C L 2 F02 k k Figure 2. V. Driver/Receiver C est Circuit k S k k 1 B D C L R L k k k S 1 2 F0 Figure. V./V.2 Driver est Circuit k k 1 B D D 1 D/ D R k k k S C L 2 F0 1 MODE SELECION LOGIC Figure. V./V.2 Receiver est Circuit DCE/DE V IN 2 BD

8 W ODE SELECIO (Note 1) (Note 1) (Note 1) MODE NME DCE D D /DE B B B Not sed (Default V.) L X L V. V. V. V. Z Z V. RS L X L V. V. V. Z Z Z V. RS L X L V. V. V. V. Z Z V. X L X L V. V. V. V. Z Z V. V L X L V.2 Z V.2 Z Z Z V.2 RS/V L X L V. V. V. V. Z Z V. V.2/RS L X L V.2 Z V.2 Z Z Z V.2 No Cable X X X Z Z Z Z Z Z Z Not sed (Default V.) L L X V. V. V. V. V. V. Z RS L L X V. V. V. Z V. V. Z RS L L X V. V. V. V. V. V. Z X L L X V. V. V. V. V. V. Z V L L X V.2 Z V.2 Z V.2 Z Z RS/V L L X V. V. V. V. V. V. Z V.2/RS L L X V.2 Z V.2 Z V.2 Z Z No Cable X X X Z Z Z Z Z Z Z Note 1: Driver inputs are L level compatible. MODE NME DCE /DE Not sed (Default V.) RS RS X V RS/V V.2/RS No Cable Not sed (Default V.) RS RS X V RS/V V.2/RS No Cable Note 2: nused receiver inputs are terminated with 0k to ground. Note : Receiver outputs are CMOS level compatible and have a weak pull-up to V IN when Z. (Note 2) (Note 2) (Note 2) (Note 2) (Note ) (Note ) (Note ) B B B V. V. V. V. V. V. 0k CMOS CMOS Z V. V. V. 0k V. V. 0k CMOS CMOS Z V. V. V. V. V. V. 0k CMOS CMOS Z V. V. V. V. V. V. 0k CMOS CMOS Z V.2 0k V.2 0k V.2 0k 0k CMOS CMOS Z V. V. V. V. V. V. 0k CMOS CMOS Z V.2 0k V.2 0k V.2 0k 0k CMOS CMOS Z 0k 0k 0k 0k 0k 0k 0k Z Z Z 0k 0k V. V. V. V. V. Z CMOS CMOS 0k 0k V. 0k V. V. V. Z CMOS CMOS 0k 0k V. V. V. V. V. Z CMOS CMOS 0k 0k V. V. V. V. V. Z CMOS CMOS 0k 0k V.2 0k V.2 0k V.2 Z CMOS CMOS 0k 0k V. V. V. V. V. Z CMOS CMOS 0k 0k V.2 0k V.2 0k V.2 Z CMOS CMOS 0k 0k 0k 0k 0k 0k 0k Z Z Z

9 W W SWICHI G I E WVEFOR S V D 0V 1.V f = 1MHz : t r ns : t f ns 1.V t PLH t PHL V O B V O 0% t r 0% % 1/2 V O V DIFF = V() V(B) 0% t f 0% % B V O t SKEW t SKEW 2 F0 Figure. V., V. Driver Propagation Delays V O B 0V V O t PLH f = 1MHz : t r ns : t f ns INP 0V t PHL V OH R V OL 1.V OP 1.V 2 F0 Figure. V., V. Receiver Propagation Delays V D 0V V O V O 1.V t PHL V t f 0V V 1.V t PLH 0V V t r V 2 F0 Figure. V., V.2 Driver Propagation Delays V IH RECEIVER HRESHOLD RECEIVER HRESHOLD V IL V OH R t PHL 1.V t PLH 1.V 2 F0 V OL Figure. V., V.2 Receiver Propagation Delays

10 PPLICIONS INFORMION W Overview he / form the core of a complete software-selectable DE or DCE interface port that supports the RS, RS, EI0, EI0-, V., V. or X.21 protocols. complete DCE-to-DE interface operating in EI0 mode is shown in Figure. he of each port is used to generate the clock and data signals. he is used to generate the control signals along with LL (local loop-back). Cable termination is used only for the clock and data signals. he control signals do not need any external resistors. DE DCE SERIL CONROLLER SERIL CONROLLER XD XD Ω XD SCE SCE Ω SCE XC Ω XC XC RXC Ω RXC RXC RXD Ω RXD RXD RS RS RS DR DR DR DCD DCD DCD DSR DSR DSR CS CS CS LL D LL LL D 2 F0 Figure. Complete Multiprotocol Interface in EI0 Mode

11 PPLICIONS INFORMION W Mode Selection he interface protocol is selected using the mode select pins, and (see the Mode Selection table). For example, if the port is configured as a V. interface, the mode selection pins should be = 1, = 0, = 0. For the control signals, the drivers and receivers will operate in V.2 (RS) electrical mode. For the clock and data signals, the drivers and receivers will operate in V. electrical mode. he DCE/DE pin will configure the port for DCE mode when high, and DE when low. he interface protocol may be selected simply by plugging the appropriate interface cable into the connector. he mode pins are routed to the connector and are left unconnected (1) or wired to ground (0) in the cable as shown in Figure. he internal pull-up current sources will ensure a binary 1 when a pin is left unconnected and that the / enter the no-cable mode when the cable is removed. In the no-cable mode the / supply current drops to less than 00µ and all driver outputs are forced into a high impedance state. he mode selection may also be accomplished by using jumpers to connect the mode pins to ground or V IN. (D) CONNECOR 1 DCE/DE 1 1 NC NC CBLE DCE/DE 1 (D) 2 F Figure. Single Port DCE V. Mode Selection in the Cable

12 PPLICIONS INFORMION W Cable ermination raditional implementations have included switching resistors with expensive relays, or required the user to change termination modules every time the interface standard has changed. Custom cables have been used with the termination in the cable head or separate terminations are built on the board and a custom cable routes the signals to the appropriate termination. Switching the termination with FEs is difficult because the FEs must remain off even though the signal voltage is beyond the supply voltage for the FE drivers or the power is off. sing the / solves the cable termination switching problem. Via software control, appropriate termination for the V. (RS2), V. (RS), V.2 (RS) and V. electrical protocols is chosen. he V. receiver configuration in the is shown in Figure 1. In V. mode switch S inside the is turned off.he noninverting input is disconnected inside the receiver and connected to ground. he cable termination is then the 0k input impedance to ground of the V. receiver. V V I Z V V.2m V Z V. (RS2) Interface typical V. unbalanced interface is shown in Figure. V. single-ended generator output with ground C is connected to a differential receiver with inputs ' connected to, and input C' connected to the signal return ground C. sually, no cable termination is required for V. interfaces, but the receiver inputs must be compliant with the impedance curve shown in Figure..2m Figure. V. Receiver Input Impedance 2 F GENEROR BLNCED INERCONNECING CBLE CBLE ERMINION LOD RECEIVER ' R k S R k R k RECEIVER ' B' k R k C C' 2 F C' GND 2 F1 Figure. ypical V. Interface Figure 1. V. Receiver Configuration

13 PPLICIONS INFORMION V. (RS) Interface typical V. balanced interface is shown in Figure. V. differential generator with outputs and B with ground C is connected to a differential receiver with ground C', inputs ' connected to, B' connected to B. he V. interface has a differential termination at the receiver end that has a minimum value of 0Ω. he termination resistor is optional in the V. specification, but for the high speed clock and data lines, the termination is required to prevent reflections from corrupting the data. he receiver inputs must also be compliant with the impedance curve shown in Figure. In V. mode, all switches are off except S1 of the s receivers which connects a Ω differential termination impedance to the cable as shown in Figure 1. he only handles control signals, so no termination other than its V. receivers 0k input impedance is necessary. GENEROR B W BLNCED INERCONNECING CBLE CBLE ERMINION ' B' 0Ω MIN LOD RECEIVER V.2 (RS) Interface typical V.2 unbalanced interface is shown in Figure 1. V.2 single-ended generator output with ground C is connected to a single-ended receiver with input ' connected to, ground C' connected via the signal return ground C. In V.2 mode all switches are off except S inside the / which connects a k (R) impedance to ground in parallel with k (R) plus k (R) for a combined impedance of k as shown in Figure 1. he noninverting input is disconnected inside the / receiver and connected to a L level reference voltage for a 1.V receiver trip point. ' B' 1.Ω S1 S2 1.Ω Ω R k S R k k R k R k RECEIVER C C' 2 F C' GND 2 F Figure. ypical V. Interface Figure. V. Receiver Configuration GENEROR BLNCED INERCONNECING CBLE CBLE ERMINION LOD RECEIVER ' R k S R k R k RECEIVER ' B' k R k C C' 2 F1 C' GND 2 F1 Figure 1. ypical V.2 Interface Figure 1. V.2 Receiver Configuration 1 ctually, there is no switch S1 in receivers and. However, for simplicity, all termination networks on the can be treated identically if it is assumed that an S1 switch exists and is always closed on the and receivers. 1

14 PPLICIONS INFORMION W V. Interface typical V. balanced interface is shown in Figure 1. V. differential generator with outputs and B with ground C is connected to a differential receiver with ground C', inputs ' connected to, B' connected to B. he V. interface requires a or delta network termination at the receiver end and the generator end. he receiver differential impedance measured at the connector must be 0Ω ±Ω, and the impedance between shorted terminals (' and B') and ground C' must be 0Ω ±Ω. In V. mode, both switches S1 and S2 inside the are on, connecting the network impedance as shown in Figure 1. he 0k input impedance of the receiver is placed in parallel with the network termination, but does not affect the overall input impedance significantly. he generator differential impedance must be 0Ω to 0Ω and the impedance between shorted terminals ( and B) and ground C must be 0Ω ±Ω. For the generator termination, switches S1 and S2 are both on as shown in Figure. No-Cable Mode he no-cable mode ( = = = 1) is intended for the case when the cable is disconnected from the connector. he bias circuitry, drivers and receivers are turned off, the driver outputs are forced into a high impedance state, and the supply current drops to less than 00µ. Supplies he uses an internal capacitive charge pump to generate V DD and V EE as shown in Figure 21. voltage doubler generates about V on V DD and a voltage inverter generates about.v for V EE. hree surface mounted tantalum or ceramic capacitors are required for C1, C2 and C. he V EE capacitor C should be a minimum of.µf. ll capacitors are 1V and should be placed as close as possible to the to reduce EMI. he has an internal boost switching regulator which generates a V output from the.v supply as shown in Figure. he V supplies its internal charge pump and transceivers as well as its companion chip. GENEROR 0Ω Ω 0Ω B BLNCED INERCONNECING CBLE ' B' LOD CBLE ERMINION Ω 0Ω 0Ω RECEIVER ' B' 1.Ω S1 S2 1.Ω Ω R k S R k k R k R k RECEIVER C C' C' GND 2 F1 2 F1 Figure 1. ypical V. Interface Figure 1. V. Receiver Configuration V. DRIVER Ω S2 1.Ω S1 1.Ω B V C C1 C µf V DD C1 + C1 C2 + C2 V EE GND C2 C.µF C 2 F21 Figure. V. Driver 2 F Figure 21. Charge Pump

15 PPLICIONS INFORMION V IN.V C µf SHDN W L1.µH V IN SW BOOS SWICHING REGLOR SHDN FB GND 2, Figure. Boost Switching Regulator 2 F Receiver Fail-Safe ll / receivers feature fail-safe operation in all modes. If the receiver inputs are left floating or shorted together by a termination resistor, the receiver output will always be forced to a logic high. DE vs DCE Operation he DCE/DE pin acts as an enable for Driver /Receiver 1 in the, and Driver /Receiver 1 and Receiver / Driver in the. he / can be configured for either DE or DCE operation in one of two ways: a dedicated DE or DCE port with a connector of appropriate gender or a port with one connector that can be configured for DE or DCE operation by rerouting the signals to the / using a dedicated DE cable or dedicated DCE cable. dedicated DE port using a DB-2 male connector is shown in Figure 2. he interface mode is selected by logic outputs from the controller or from jumpers to either V IN or GND on the mode select pins. port with one DB-2 connector, but can be configured for either DE or DCE operation is shown in Figure. he configuration requires separate cables for proper signal routing in DE or DCE operation. For example, in DE C1,C2: IYO YDEN XR JMK1BJML : ON SEMICONDCOR MBR0 L1: SMID C-R 1k.k V 0m C µf mode, the XD signal is routed to Pins 2 and via Driver 1 in the. In DCE mode, Driver 1 now routes the RXD signal to Pins 2 and. Multiprotocol Interface with RL, LL, M and a DB-2 Connector If the RL, LL and M signals are implemented, there are not enough drivers and receivers available in the /. In Figure 2, the required control signals are handled by the LC2. he LC2 has an additional single-ended driver/receiver pair that can handle two more optional control signals such as M and LL. Cable-Selectable Multiprotocol Interface cable-selectable multiprotocol DE/DCE interface is shown in Figure 2. he select lines, and DCE/DE are brought out to the connector. he mode is selected by the cable by wiring (connector Pin 1) and (connector Pin 21) and DCE/DE (connector Pin 2) to ground (connector Pin ) or letting them float. If, or DCE/ DE is floating, internal pull-up current sources will pull the signals to V IN. he select bit is floating and therefore, internally pulled high. When the cable is pulled out, the interface will go into the no-cable mode. Compliance esting he / chipset has been tested by V Rheinland of North merica Inc. and passed the NE1, NE2 and B requirements. Copies of the test report are available from LC or V Rheinland of North merica Inc. he title of the report is est Report No. B/001/02 he address of V Rheinland of North merica Inc. is: V Rheinland of North merica Inc. 1, Old Highway NW, Suite St. Paul, MN 1 el. (1) -0 Fax (1) -0

16 YPICL PPLICIO S V IN.V C µf V C C1 SHDN L1.µH BOOS SWICHING REGLOR CHRGE PMP MBR0 + C2 C.µF 1k.k C µf V XD SCE XC RXC RXD DCE/DE VIN.V XD () XD B SCE () SCE B XC () XC B RXC (1) RXC B RXD () RXD B SG SHIELD C RS DR C 1 2 V DD V EE GND C 1 2 DB-2 MLE CONNECOR RS () RS B DR () DR B DCD DSR CS DCD () DCD B DSR () DSR B CS () CS B LL 1 1 LL (1) 1 D DCE/DE V V IN IN C.V 2 F2 1 Figure 2. Controller-Selectable Multiprotocol DE Port with DB-2 Connector

17 YPICL PPLICIO S V IN.V C µf V C C1 SHDN L1.µH BOOS SWICHING REGLOR CHRGE PMP MBR0 + C2 C.µF 1k.k C µf V DE_XD/DCE_RXD DE_SCE/DCE_RXC DE_XC/DCE_XC DE_RXC/DCE_SCE DE_RXD/DCE_XD C DE_RS/DCE_CS DE_DR/DCE_DSR C DCE/DE V DD V EE GND VIN.V C DE XD XD B SCE SCE B XC XC B RXC RXC B RXD RXD B SG SHIELD RS RS B DR DR B DCE RXD RXD B RXC RXC B XC XC B SCE SCE B XD XD B DB-2 CONNECOR CS CS B DSR DSR B DE_DCD/DCE_DCD DE_DSR/DCE_DR DE_CS/DCE_RS DCD DCD B DSR DSR B CS CS B DCD DCD B DR DR B RS RS B DE_LL/DCE_LL 1 1 LL LL DCE/DE 1 D DCE/DE V V IN IN C.V 2 F2 Figure. Controller-Selectable Multiprotocol DE/DCE Port with DB-2 Connector 1

18 YPICL PPLICIO S V IN.V C µf V C C1 SHDN L1.µH BOOS SWICHING REGLOR CHRGE PMP MBR0 + C2 C.µF 1k.k C µf V DE_XD/DCE_RXD DE_SCE/DCE_RXC DE_XC/DCE_XC DE_RXC/DCE_SCE DE_RXD/DCE_XD DCE/DE VIN.V DE XD XD B SCE SCE B XC XC B RXC RXC B RXD RXD B SG SHIELD DCE RXD RXD B RXC RXC B XC XC B SCE SCE B XD XD B C DE_RS/DCE_CS DE_DR/DCE_DSR C 1, 1 2 V DD V EE GND 2 1 C 1 2 DB-2 CONNECOR RS RS B DR DR B CS CS B DSR DSR B DE_DCD/DCE_DCD DE_DSR/DCE_DR DE_CS/DCE_RS DE_LL/DCE_RI DE_RI/DCE_LL LC2 D * DCD DCD B DSR DSR B CS CS B LL RI DCD DCD B DR DR B RS RS B RI LL DCE/DE DE_M/DCE_RL DE_RL/DCE_M 1 R 1 21 D 1 DCE/DE V IN DENB EN 1 NC C V IN.V 2 M 21 RL *OPIONL RL M 2 F2 1 Figure 2. Controller-Selectable Multiprotocol DE/DCE Port with RL, LL, M and DB-2 Connector

19 YPICL PPLICIO S V IN.V C µf V C C1 SHDN L1.µH BOOS SWICHING REGLOR CHRGE PMP MBR0 + C2 C.µF 1k.k C µf V DE_XD/DCE_RXD DE_SCE/DCE_RXC DE_XC/DCE_XC DE_RXC/DCE_SCE DE_RXD/DCE_XD NC DCE/DE VIN.V DE XD XD B SCE SCE B XC XC B RXC RXC B RXD RXD B SG SHIELD DCE RXD RXD B RXC RXC B XC XC B SCE SCE B XD XD B DB-2 CONNECOR C DE_RS/DCE_CS DE_DR/DCE_DSR C 1 2 V DD V EE GND C 2 DCE/DE 21 1 RS 1 RS B DR 2 DR B CS CS B DSR DSR B DE_DCD/DCE_DCD DE_DSR/DCE_DR DE_CS/DCE_RS NC 1 D DCE/DE V V IN IN C.V CBLE WIRING FOR MODE SELECION MODE V. RS, V. RS PIN 1 PIN NC PIN CBLE WIRING FOR DE/DCE SELECION MODE PIN 2 DE PIN DCE NC PIN 21 PIN PIN NC 1 DCD DCD B DSR DSR B CS CS B DCD DCD B DR DR B RS RS B 2 F2 Figure 2. Cable-Selectable Multiprotocol DE/DCE Port with DB-2 Connector Information furnished by Linear echnology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear echnology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1

20 PCKGE DESCRIPIO G Package 2-Lead Plastic SSOP (.mm) (Reference LC DWG # ) 1.2 ± * (.0.1) (.21.2) 0.2 ± BSC RECOMMENDED SOLDER PD LYO ** (.1.1) 2.0 (.0) (.00.0) (.0.0) NOE: 1. CONROLLING DIMENSION: MILLIMEERS MILLIMEERS 2. DIMENSIONS RE IN (INCHES). DRWING NO O SCLE * DIMENSIONS DO NO INCLDE MOLD FLSH. MOLD FLSH SHLL NO EXCEED.2mm (.00") PER SIDE ** DIMENSIONS DO NO INCLDE INERLED FLSH. INERLED FLSH SHLL NO EXCEED.2mm (.0") PER SIDE 0. (.02) BSC (.00.0) 0.0 (.002) G2 SSOP 002 RELED PRS PR NMBER DESCRIPION COMMENS LC1 Dual RS/RS ransceiver wo RS Driver/Receiver Pairs or wo RS Driver/Receiver Pairs LC Single V RS/RS Multiprotocol ransceiver wo RS Driver/Receiver or Four RS Driver/Receiver Pairs LC Software-Selectable Multiprotocol ransceiver -Driver/-Receiver for Data and Clock Signals LC Software-Selectable Cable erminator Perfect for erminating the LC (Not Needed with LC) LC Single Supply V. ransceiver -Driver/-Receiver for Data and Clock Signals LC Dual Supply V. ransceiver -Driver/-Receiver for Data and Clock Signals LC Software-Selectable Multiprotocol ransceiver erminated with LC for Data and Clock Signals, Companion to LC or LC for Control Signals LC Software-Selectable Multiprotocol ransceiver Companion to LC or LC for Control Signals Including LL LC Software-Selectable Multiprotocol ransceiver -Driver/-Receiver Companion to LC or LC for Control Signals Including LL, M and RL LC Software-Selectable Multiprotocol ransceiver -Driver/-Receiver with ermination for Data and Clock Signals LC2.V Software-Selectable Multiprotocol ransceiver.v Supply, -Driver/-Receiver Companion to for Control Signals Including LL, M and RL.V Software-Selectable Multiprotocol ransceiver.v Supply, -Driver/-Receiver with ermination for Data and Clock Signals, Generates the Required V and ±V Supplies for and Companion Parts Linear echnology Corporation 10 McCarthy Blvd., Milpitas, C 0-1 (0) 2-0 FX: (0) L/P 00 1K PRINED IN S LINER ECHNOLOGY CORPORION 02