EECS 150 Homework 8 Solutions Fall Problem 1: CLD2 Problem 8.2, showing BOTH methods (row matching and implication chart).

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1 Problem 1: CLD2 Problem 8.2, showing BOTH methods (row matching and implication chart). Row matching: The state transition table (with one row per state) is: There are no two rows where the next states and outputs are identical, so the row matching method will not help us simplify this FSM. Implication chart: The initial implication chart shows which states are implied as equivalent, and has an X in any box where the corresponding states have different outputs. On the first pass, we eliminate boxes whose implied state pairs are already crossed off. Those boxes are highlighted in blue in the table below. Cross these boxes out. Page 1 of 7

2 In the second pass, highlight any boxes that contain implied state pairs that have now been crossed off. Continue in this manner until you can t cross off any more boxes. The ones that are left are equivalent states: So the following pairs of states are equivalent: A & B, E & F, E & G, and F & G. We can create a new state A that replaces A & B, and a new state E that replaces E, F, & G. The final state diagram looks like this: Page 2 of 7

3 Problem 2: CLD2 problem 8.14 To partition the FSM, introduce two idle states, SA and SB. Any transition from left FSM to the right FSM must go to state SA and leave from SB and vice versa. Interactions between states within each half of the FSM are unchanged. The partitioned state diagram is shown below: The partitioned solution does take a bit more logic to implement, since you have to implement the self loops on SA and SB. You have NOT introduced any delay, because the transition to SA and leaving SB happens on the same clock edge. If you and your partner implement the two halves of the partitioned state machine separately, you need to make sure that all the signals that are shared between the two halves (S0, S1, S3, S4, S6, and the input) are available to both FSMs. Problem 3: CLD2 problems 8.6 and Start by making the state transition table. Page 3 of 7

4 From the state transition table we can make the implication chart, using the same method as we did in Problem 1. Continue crossing off boxes when you find that the implied state pairs in that box are not equivalent. The final implication chart is: Page 4 of 7

5 We see from the chart that several states can be combined: 0 & 6 are equivalent 0 1, 2, 4 & 5 are all equivalent 1 We are left with just three states: 0, 1, and 3. The state diagram is: 8.7 (a) Minimum bit change heuristic Rationale for state map assignments: S0 = 000 because it is the reset state, and this simplifies the reset logic. S1 & S2 should be adjacent to S0 because these are the next states of S0. (Note: wrapping edges is allowed, and still adjacent just like K maps.) S3 & S4 should ideally both be adjacent to S1 and S2, but that isn t possible so we ll have to make a tradeoff. S5 & S6 should be adjacent to S0, and also near S3 and S4. We get the following State Map and State Assignment: (b) State assignment guidelines Priority #1: S1 & S2 adjacent because both go to S3 when In=1 and S4 when In=0. S5 & S6 both go to S0 for all inputs, so they should be adjacent S3 & S4 should be adjacent because both go to S6 when In=1. Page 5 of 7

6 EECS 150 Homework 8 Solutions Fall 2008 Priority #2: S1 & S2 adjacent because they are both next states of S0 S3 & S4 adjacent because they are both next states of S1 and S2 S5 & S6 adjacent because they are both next states of S3 This rationale leads to the following state map and state assignment: (a) An implementation both FSMs using the same ROM is shown below: i. No, this implementation is NOT efficient. In fact, HALF of the ROM is wasted space! The input bits for the first FSM aren t used with the output bits of the second FSM, and vice versa. The figure below illustrates this; the wasted space in the ROM is shown with diagonal lines. Page 6 of 7

7 ii. 2 7 x 6 bits = (128)*(6) = 768 ROM bits = 768 square microns 1 square micron = 10 6 square millimeter (786 x 10 6 mm 2 )*($0.20/mm 2 ) = $ = cents! (b) The size of a ROM scales exponentially with the number of inputs, but only linearly with the number of outputs. In other words, adding inputs is MUCH more costly than adding outputs. If we had to implement many of these FSMs on a single ROM, the size would scale roughly with 2^(FSM1IN + FSM2IN), where FSM1IN and FSM2IN are the total number of input bits to the ROM from FSM1 and FSM2, respectively. (c) If we implement many of these FSMs using separate ROMs, we get a much more efficient solution. The size of the ROM scales roughly with (2^FSM1IN)+(2^FSM2IN) which is MUCH smaller. For example, let FSM1IN = 4 and FSM2IN = 5: Single ROM: 2 (4+5) = 512 word lines Separate ROMs: = 48 word lines Problem 4 One micron spacing between wires means there are 10 4 wires/cm per layer. Since the chip is 1cm square, there are 10 4 wires per layer that are each 1cm in length. (10 4 wires/layer)*(10 2 m/wire)*(10 layers/chip) = 1000m/chip = 1km!! Problem 5 Speed of light: c = 3 x 10 8 m/s Time between rising edges of a 4 GHz clock: t = 1/(4x10 9 ) = 2.5x10 10 seconds (3 x 10 8 m/s)*( 2.5x10 10 sec) = 0.75m Problem 6 ( m m /s ) = sec = 0.09 ns = 94.3 ps Page 7 of 7