Review: Single-Cycle Processor. Limits on cycle time
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1 Review: Single-Cycle Processor Jump 3:26 5: MemtoReg Control Unit LUControl 2: Op Funct LUSrc RegDst PCJump PC 4 uction + PCPlus4 25:2 2:6 2:6 5: 5: 2 3 WriteReg 4: Src Src LU Zero LUResult Write + PC Read Result 27: 3:28 25: Limits on cycle time Jump MemtoReg Control Unit LUControl 2: 3:26 Op LUSrc 5: Funct RegDst PC uction 25:2 2:6 2 3 Src Src LU Zero LUResult Write Result Read PCJump 2:6 5: + PCPlus4 WriteReg 4: 4 5: + PC 27: 3:28 Next address logic uction fetch access LU operation access time. 25: 2
2 Multicycle Processor path uilding locks PC Read uction PC
3 Read Source Operand (rs( rs) PC 25: Sign-Extend the Immediate PC 25: : 6 3
4 dd ase ddress to the Offset LUControl 2: PC 25:2 2 3 Src Src LU LUResult LUOut 5: 7 Load from LUControl 2: PC dr 25:2 2 3 Src Src LU LUResult LUOut 5: 8 4
5 Write ack to LUControl 2: PC dr 25:2 2:6 2 3 Src Src LU LUResult LUOut 5: 9 Increment PC y 4 LUSrc LUSrc : LUControl 2: PC dr 25:2 2: Src Src LU LUResult LUOut 5: 5
6 Enhanced path for sw LUSrc LUSrc : LUControl 2: PC dr 25:2 2:6 2: Src Src LU LUResult LUOut 5: Enhanced path for R-Type RegDst MemtoReg LUSrc LUSrc : LUControl 2: PC dr 25:2 2:6 2:6 5: Src Src LU LUResult LUOut 5: 2 6
7 Enhanced path for eq RegDst MemtoReg LUSrc LUSrc : LUControl 2: PC dr 25:2 2:6 2:6 5: 2 3 Src Zero LUResult LUOut 4 Src LU 5: 3 Multicycle Processor path RegDst MemtoReg LUSrc LUSrc : LUControl 2: PC dr 25:2 2:6 2:6 5: 2 3 Src Zero LUResult LUOut 4 Src LU 5: ImmExt 4 7
8 Multicycle Processor Control Control Unit 3:26 Op 5: Funct LUControl 2: LUSrc : LUSrc PC dr 25:2 2:6 RegDst 2:6 5: MemtoReg 2 3 Src Zero LUResult LUOut 4 Src LU 5: 5 Control Unit? Control Unit Opcode 5: Main Controller (FSM) MemtoReg RegDst LUSrc : LUSrc Multiplexer Selects Enales LUOp : Funct 5: LU Decoder LUControl 2: 6 8
9 The Fetch S: Fetch = Reset lusrc = LUSrc = LUOp = = Control Unit 3:26 Op 5: Funct LUControl 2: LUSrc : LUSrc RegDst 25:2 PC dr 2:6 X 2:6 5: MemtoReg X 2 3 Src Zero LUResult LUOut 4 Src LU 5: 7 The Decode S: Fetch S: Decode = Reset lusrc = LUSrc = LUOp = = Control Unit 3:26 Op 5: Funct LUControl 2: LUSrc : LUSrc RegDst X 25:2 PC dr 2:6 X 2:6 5: MemtoReg X 2 3 X Src XXX Zero X XX LUResult LUOut 4 Src LU 5: 8 9
10 LW and SW - ddress Calc S: Fetch = Reset lusrc = LUSrc = LUOp = = S: Decode S2: Memdr LUSrc = LUSrc = LUOp = or Control Unit LUControl 2: LUSrc : 3:26 Op 5: Funct LUSrc X PC dr RegDst 25:2 2:6 X 2:6 5: MemtoReg X 2 3 Src Zero LUResult LUOut 4 Src LU X 5: 9 ddress Calc S: Fetch = Reset lusrc = LUSrc = LUOp = = S: Decode S2: Memdr or LUSrc = LUSrc = LUOp = S3: MemRead = S4: Mem RegDst = MemtoReg = 2
11 SW - no writeack S: Fetch = Reset lusrc = LUSrc = LUOp = = S: Decode S2: Memdr or LUSrc = LUSrc = LUOp = S3: MemRead S5: = = S4: Mem RegDst = MemtoReg = 2 R Type S: Fetch = Reset lusrc = LUSrc = LUOp = = S: Decode S2: Memdr or Op = R-type S6: Execute LUSrc = LUSrc = LUOp = LUSrc = LUSrc = LUOp = S3: MemRead S5: S7: LU = = RegDst = MemtoReg = S4: Mem RegDst = MemtoReg = 22
12 EQ S2: Memdr S: Fetch = Reset lusrc = LUSrc = LUOp = = LUSrc = LUSrc = LUOp = S3: MemRead or S: Decode S5: LUSrc = LUSrc = LUOp = Op = R-type S6: Execute S7: LU LUSrc = LUSrc = LUOp = Op = EQ S8: LUSrc = LUSrc = LUOp = = = = RegDst = MemtoReg = S4: Mem RegDst = MemtoReg = 23 Control Unit S2: Memdr S: Fetch = Reset lusrc = LUSrc = LUOp = = LUSrc = LUSrc = LUOp = S3: MemRead or S: Decode S5: LUSrc = LUSrc = LUOp = Op = R-type S6: Execute S7: LU LUSrc = LUSrc = LUOp = Op = EQ S8: LUSrc = LUSrc = LUOp = = = = RegDst = MemtoReg = S4: Mem RegDst = MemtoReg = 24 2
13 J RegDst MemtoReg LUSrc LUSrc : LUControl 2: : PC dr 25:2 2:6 2:6 5: 2 3 3:28 4 Src Src LU Zero LUResult LUOut PCJump 27: 5: 25: (jump) 25 Jump S2: Memdr S: Fetch = Reset lusrc = LUSrc = LUOp = = LUSrc = LUSrc = LUOp = S3: MemRead or S: Decode S5: LUSrc = LUSrc = LUOp = Op = R-type S6: Execute S7: LU LUSrc = LUSrc = LUOp = Op = EQ Op = J Op = DDI S8: LUSrc = LUSrc = LUOp = = S: Jump S9: DDI Execute S: DDI = LUSrc = LUSrc = LUOp = = = RegDst = MemtoReg = RegDst = MemtoReg = S4: Mem RegDst = MemtoReg = 26 3
14 Multicycle Performance uctions take different numer of cycles: 3 cycles: eq, j 4 cycles: R-Type, sw, addi 5 cycles: lw CPI is weighted average SPECINT2 enchmark: 25% loads % stores % ranches 2% jumps 52% R-type verage CPI = (. +.2)(3) + (.52 +.)(4) + (.25)(5) = Critical Path T c = t pcq_pc + t mux + max(t LU + t mux, t mem ) + t setup Control Unit 3:26 Op 5: Funct LUControl 2: LUSrc : LUSrc PC dr 25:2 2:6 RegDst 2:6 5: MemtoReg 2 3 Src Zero LUResult LUOut 4 Src LU 5: 28 4
15 Multicycle Performance Multicycle critical path: T c = t pcq_pc + t mux + max(t LU + t mux, t mem ) + t setup Control Unit 3:26 Op 5: Funct LUControl 2: LUSrc : LUSrc PC dr 25:2 2:6 RegDst 2:6 5: MemtoReg 2 3 Src Zero LUResult LUOut 4 Src LU 5: 29 Multicycle Performance Example Element clock-to-q setup Multiplexer LU read file read file setup Parameter t pcq_pc t setup t mux t LU t mem t RFread t RFsetup Delay (ps) T c = t pcq_pc + t mux + max(t LU + t mux, t mem ) + t setup = t pcq_pc + t mux + t mem + t setup = [ ] ps = 325 ps 3 5
16 Multicycle Performance Example For a program with illion instructions executing on a multicycle MIPS processor, CPI = 4.2 T c = 325 ps Execution Time = (# instructions) CPI T c = ( 9 )(4.2)(325-2 ) = 33.9 seconds This is slower than the single-cycle processor (95 seconds). Why? Not all steps the same length Sequencing overhead for each step (t pcq + t setup = 5 ps) 3 Simple questions How many cycles to execute this code? What is going on during the 8th cycle of execution? In what cycle does the actual addition of $t2 and $t3 take place? lw $t2, ($t3) lw $t3, 4($t3) eq $t2, $t3, Lael add $t5, $t2, $t3 sw $t5, 8($t3) Lael: 32 6
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