CSc 256 Midterm 2 Fall 2010
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1 CSc 256 Midterm 2 Fall 2010 NAME: 1a)YouaregivenaMIPSbranchinstruction: x:beq$12,$0,y Theaddressofthelabel"y"is0x40013c.Thememorylocationat"x"contains: addresscontents 0x ????????????????...whichrepresentsthebeqinstruction;the????...????arethe 16 bitconstant.findthe16 bitconstant (12points) ANS:BTA=&beq+4+offset 0x40013c=0x offset offset=0x40013c 0x400208=0x40013c+0xffbffdf4=0xffffff30 = constant= b)YouaregiventhisMIPSinstruction: lb $8,x Thelabelxisatmemoryaddress0x TranslatethisMIPSinstructiontoanefficientsequenceofmachine languageinstructions.youonlyhavetoshowthetextformofthe machinelanguageinstructions;don'ttranslateintobinary. (5points) ANS: lui$1,0x1001 lb$8,0x408($1)
2 1c)ThisisamemorylocationthatcontainsaMIPSinstruction: addresscontents [0x ] 0xad74000c TranslateitintotheMIPSassemblylanguageinstruction(showthe operation,operands,etc): (13points) ANS: 0xad74000c= opcode=101011sw rsis11,rtis20,constantis12 sw$20,12($11)
3 Problem2: Considerthisdigitallogiccircuit:
4 a)filloutanequivalenttruthtableforthecircuit.(14points) X3 X2 X1 X0 y b)writeanequivalentlogicexpressionforoutputy,insumofproductsform.(6 points) y=~x3x2x1x0+x3~x2x1x0+x3x2x1x0
5 Problem3: Refer to the MIPS single-cycle datapath in the sheets provided. Show the control signals for the MIPS instructions, in the table below. Note that some of the control signals have new names. (30 points) Hint: ALUOp control bits are 00 (force ALU to add), 01 (force ALU to subtract), 10 (follow operation specified by bits 5-0 of instruction word) [SelA is branch, SelB is ALUSrc, SelC is RegDst, SelD is MemToReg] a) R-type ALUOp1 ALUOp0 RegWrite MemRead MemWrite SelA SelB SelC SelD x b) sw ALUOp1 ALUOp0 RegWrite MemRead MemWrite SelA SelB SelC SelD x x x
6 Problem 4 For the MIPS single-cycle datapath given, suppose we build a new implementation using slower technology. These are the latencies through the main components: Register Read Register Write ALU operation Memory Read Memory Write 15 ns 15 ns 25 ns 20 ns 20 ns a) Estimate the time taken for each type of instruction to complete (14 points): lw 20 (IF) + 15 (RegR) + 25 (ALU) + 20 (MemR) + 15 (RegW) = 95 ns sw 20 (IF) + 15 (RegR) + 25 (ALU) + 20 (MemW) = 80 ns R-type 20 (IF) + 15 (RegR) + 25 (ALU) + 15 (RegW) = 75 ns Beq 20 (IF) + 15 (RegR) + 25 (ALU) = 60 ns b) What is the cycle time for this implementation? What is the clock rate in MHz? (Hint: 1 ns = 10^-9 seconds, 1 MHz = 10^6 Hz.) You can show an expression that evaluates to the clock rate, but make sure the unit is in MHz. (6 points) ANS: Cycle time = 95 ns Clock rate = 1 / (95 * 10^-9) Hz = 10^9 / 95 Hz = 1000/95 MHz
7 MIPSinstructions op1,op2areregisters,op3isregisterorconstant cont[op1]meanscontentsofop1 moveop1,op2 cont[op1]=cont[op2] addop1,op2,op3 cont[op1]=cont[op2]+cont[op3] subop1,op2,op3 cont[op1]=cont[op2] cont[op3] mulop1,op2,op3 cont[op1]=cont[op2]*cont[op3] divop1,op2,op3 cont[op1]=cont[op2]/cont[op3] remop1,op2,op3 cont[op1]=cont[op2]%cont[op3] notop1,op2 cont[op1]=notcont[op2](bitwise) andop1,op2,op3 cont[op1]=cont[op2]andcont[op3](bitwise) orop1,op2,op3 cont[op1]=cont[op2]orcont[op3](bitwise) nandop1,op2,op3 cont[op1]=cont[op2]nandcont[op3](bitwise) norop1,op2,op3 cont[op1]=cont[op2]norcont[op3](bitwise) xorop1,op2,op3 cont[op1]=cont[op2]xorcont[op3](bitwise) sllop1,op2,amt cont[op1]=cont[op2]shiftleftlogical byamtbits srlop1,op2,amt cont[op1]=cont[op2]shiftrightlogical byamtbits sraop1,op2,amt cont[op1]=cont[op2]shiftrightarithmetic byamtbits rolop1,op2,amt cont[op1]=cont[op2]rotateleftbyamtbits rorop1,op2,amt cont[op1]=cont[op2]rotaterightbyamtbits blabel gotolabel jlabel gotolabel beqop1,op2,label if(cont[op1]==cont[op2])gotolabel bneop1,op2,label if(cont[op1]!=cont[op2])gotolabel bgtop1,op2,label if(cont[op1]>cont[op2])gotolabel bgeop1,op2,label if(cont[op1]>=cont[op2])gotolabel bltop1,op2,label if(cont[op1]<cont[op2])gotolabel bleop1,op2,label if(cont[op1]<=cont[op2])gotolabel beqzop1,label if(cont[op1]==0)gotolabel bnezop1,label if(cont[op1]!=0)gotolabel bgtzop1,label if(cont[op1]>0)gotolabel bgezop1,label if(cont[op1]>=0)gotolabel bltzop1,label if(cont[op1]<0)gotolabel blezop1,label if(cont[op1]<=0)gotolabel lar,label cont[r]=addressoflabel lir,constant cont[r]=constant lwr,?? cont[r]=m[addr]
8 lbr,?? cont[r]=m[addr],sign extended lbur,?? cont[r]=m[addr],zero extended swr,?? M[ADDR]=cont[R] sbr,?? m[addr]=low8 bitsofcont[r] if??isalabel,addr=addressoflabel if??is(r),addr=cont[r] if??isconstant(r),addr=cont[r]+constant if??islabel(r),addr=cont[r]+addressoflabel mtc0op1,op2 contentsofcoprocessor0registerop1= contentsofmipsregisterop2 mfc0op1,op2 contentsofmipsregisterop1= contentsofcoprocessor0registerop2 Syscallusage: printanint $v0=1,$a0=inttobeprinted printastring $v0=4,$a0=addressofstringtobeprinted readanint $v0=5,inputintappearsin$v0 exit $v0=10 MIPSregisternames: $0 $1 $2,$3 $v0,$v1 $4 $7 $a0 $a3 $8 $15 $t0 $t7 $16 $23 $s0 $s7 $24 $25 $t8 $t9 $26 $27 $k0 $k1 $28 $gp $29 $sp $30 $s8 $31 $ra
9 ss ssst tttt dddd d add rd,rs,rt ss ssst tttt dddd d sub rd,rs,rt ss ssst tttt mult rs,rt ss ssst tttt div rs,rt ss ssst tttt dddd d addu rd,rs,rt ss ssst tttt dddd d subu rd,rs,rt ss ssst tttt multu rs,rt ss ssst tttt divu rs,rt dddd d mfhi rd ss sss mthi rs dddd d mflo rd ss sss mtlo rs ss ssst tttt dddd d and rd,rs,rt ss ssst tttt dddd d nor rd,rs,rt ss ssst tttt dddd d or rd,rs,rt ss ssst tttt dddd d xor rd,rs,rt ss ssst tttt dddd d sllv rd,rt,rs ss ssst tttt dddd d srlv rd,rt,rs ss ssst tttt dddd d srav rd,rt,rs ss ssst tttt iiii iiii iiii iiii addi rt,rs,i ss ssst tttt iiii iiii iiii iiii addiu rt,rs,i ss ssst tttt iiii iiii iiii iiii andi rt,rs,i t tttt iiii iiii iiii iiii lui rt,i ss ssst tttt iiii iiii iiii iii ori rt,rs,i ss ssst tttt iiii iiii iiii iiii xori rt,rs,i t tttt dddd diii ii sll rd,rt,i t tttt dddd diii ii srl rd,rt,i t tttt dddd diii ii sra rd,rt,i bb bbbt tttt iiii iiii iiii iiii lw rt,i(rb) bb bbbt tttt iiii iiii iiii iiii lb rt,i(rb) bb bbbt tttt iiii iiii iiii iiii lbu rt,i(rb) bb bbbt tttt iiii iiii iiii iiii sw rt,i(rb) bb bbbt tttt iiii iiii iiii iiii sb rt,i(rb) ss sss iiii iiii iiii iiii bltz rs,i ss sss iiii iiii iiii iiii bgez rs,i ss sss iiii iiii iiii iiii blez rs,i ss sss iiii iiii iiii iiii bgtz rs,i ss ssst tttt iiii iiii iiii iiii beq rs,rt,i
10 ss ssst tttt iiii iiii iiii iiii bne rs,rt,i ss ssst tttt dddd d slt rd,rs,rt ss ssst tttt iiii iiii iiii iiii slti rt,rs,i ii iiii iiii iiii iiii iiii iiii j I ss sss jr rs ii iiii iiii iiii iiii iiii iiii jal I ss sss dddd d jalr rd,rs syscall
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