New Method to Separate Failure Modes by Transient Thermal Analysis of High Power LEDs

Transcription

1 2017 IEEE 67th Electronic Components and Technology Conference New Method to Separate Failure Modes by Transient Thermal Analysis of High Power LEDs Alexander Hanss 1*, E Liu 1, Maximilian Schmid 1, Dominik Müller 1, Udo Karbowski 2, Robert Derix 2, Gordon Elger 1 1 Technische Hochschule Ingolstadt, Esplanade 10, Ingolstadt, Germany 2 Lumileds Germany GmbH, Philipsstrasse 8, Aachen, Germany *alexander.hanss@thi.de Abstract A high reliability of light emitting diode (LED) light sources is essential for general and automotive lighting applications, where exchange of LED components is expensive. Thermal management of modern high power LEDs is crucial for their lifetime. An important aspect is the thermal path for heat conduction. Many different defects can have an influence on this path of an electronic system: on the one hand process failures during production, e.g. voids inside the solder joint, on the other hand typical failures induced by thermo-mechanical stress during their lifetime, like cracks in the solder joint or delamination in the package. The transient thermal analysis (TTA) is a powerful tool to detect changes in the thermal path. Due to improvements in the TTA method during the last years, not only cracks can be detected but also failure modes can be separated, and the root cause can be analyzed by support of transient finite element analysis. In this paper, transient thermal testing is applied and further developed, to monitor the structural integrity of new wafer level LED packages during thermal stress testing. Failure modes are defined and separated. For failure analysis the different defects are simulated by transient finite element analysis and correlated to the TTA results. The simulation results, that solder cracks increase the peak height of the derivative of the transient thermal curves (b(z)). A delamination of an inner layer of the LED package creates additionally to the increase of the peak height also a separation of the b(z) curves between 1 μs and 5 μs. Therefore a transient thermal measurement equipment with a dead time < 10 μs is necessary, which currently is in development. For correlation of these results LED modules soldered with different solder alloys were produced. After initial and 500 thermal shock cycles to the LEDs, the TTA was performed again. No significant change of the peak height of B(z) was detectable Only some samples soldered with AuSn and SnAgCuBiSb show a difference in the early time area, which is an indication of a delamination. A new combined accelerated test is introduced using In-Situ TTA measurements: the LEDs are driven by nominal current during temperature cycle test and the structural integrity is measured at different temperatures. This combination is especially useful, because the TTA is done during thermo-mechanical stress under hot and cold conditions. Additional information can be obtained. Keywords: LED, Reliability, Transient Thermal Testing I. INTRODUCTION During the last four decades, technical progress in the field of light-emitting diodes (LEDs) has been breathtaking. Stateof-the art LEDs are small, rugged, reliable, bright, and efficient [1]. Flip-chip LEDs (FC-LEDs) were first introduced at the end of the 90s [2]. FC-LEDs compared to conventional wire bonded LEDs have a higher light extraction efficiency and a very good heat extraction [2]. For FC-LED the GaN epitaxial layer is grown on patterned sapphire substrates. The LED is assembled p-side down to the PCB. A silver layer under the p-layer increases current spreading and light reflection. To support the mechanical stability, the sapphire is not removed [3]. For automotive headlamps the blue GaN FC-LED is coated with a phosphor containing ceramic, usually a fine crystalline Yttrium Aluminum Garnet doped with Cerium (YAG-Ce) to convert the blue light into white [2]. FC-LEDs are typically bonded on first level to rigid substrates with matched coefficient of thermal expansion (CTE) like silicon or ceramic. The package is afterwards assembled on second level (PCB). Yole Development estimates the market share of flip-chip LEDs to grow for high power LEDs from 11 % in 2013 to 32 % in 2018 [4]. The demand for miniaturization, especially for design reasons in automotive sector, and in addition to offering an increased performance/cost ratio, flip-chip LEDs are also a key enabling technology for the development of chip-scale packages (CSP), which could allow further cost reduction [4]. The CSP package takes its name from the chip size and is defined so that the chip must occupy 80 % or more of the package area [5]. CSP presents several advantages (including miniaturized size and better thermal contact to substrates). However, eliminating several process steps of traditional LED packaging, CSPs have also an impact on the industrial supply chain, with some LED chip makers supplying their products directly to LED module makers [4]. Usually the CSP has a rigid substrate like silicon or ceramic. A wafer level package is a subtype of a CSP [6]. If the CSP has no carrier between chip and PCB it is manufactured on LED-wafer level and called wafer level package (WLP) or wafer level chip scale package (WL-CSP) [6]. In industry often these names are not strictly separated. The WL-CSP LED has the big advantage to allow to skip one assembly level. This reduces the costs in the manufacturing process. A schematic drawing of the WL-CSP LED used in this paper is depicted in Figure /17 $ IEEE DOI /ECTC

2 Figure 1. Structure of a modern WL-CSP LED (schematically, not to scale). By eliminating the stiff carrier, the thermo-mechanical interaction between PCB and LED die gets very strong. The epitaxial layer (EPI) is solely separated from the PCB by the redistribution layer and the solder joint. The overall mechanical design of the module will influence the reliability of the device. In addition to the mechanical support, a carrier also provides heat spreading for standard FC-LEDs. Without the carrier heat spreading has to be provided by the PCB [7]. Non symmetric design of the heat spreading in the PCB or voids in the solder interconnects will cause inhomogeneous heat distribution in the EPI and reduce the lifetime of the WL- CSP LEDs [8]. Modern semiconductors are highly efficient, but the thermal management has a significant influence to their life time. Especially for high power LEDs of the newest generation, a faultless thermal path is essential. A common test for thermo-mechanical induced failures is the air to air temperature shock test, where the devices are exposed to temperature cycles from -40 C to +125 C [9]. In this paper white and blue high power automotive WL- CSP LEDs are soldered directly on Al-IMS PCBs. The initial quality of the interconnect and module is tested by X-Ray and transient thermal analysis. After initial quality checks the test samples were exposed to temperature shock test -40 C / +125 C and, after a defined amount of cycles (500, 1000, 1500), the TTA is performed repeatedly. Also a high temperature operational life (HTOL) test is applied. In parallel a FEM simulation modes was developed to analyze the impact of the different failure modes on the transient thermal signal. II. EXPERIMENTAL METHODOLOGY A. LED Package and Assembly As the demand for LED matrix systems continues to increase, especially in the automotive sector, in this paper a modern fine-pitch 5 LED string with predevelopment high power WL-CSP LEDs was used. This LEDs can be assembled directly on printed circuit boards (PCB). Pictures of the LED and drawing of their foot print (drawing of their solder pads) are depicted in Figure 2. In the paper WL-CSP LEDs with and without phosphor converter were assembled to use scanning acoustic microscopy (SAM) for investigation of crack formation and delamination. Figure 2. Picture of the used unpackaged flip-chip LED (left picture) and corresponding drawing of the solder pad design (right top and bottom pictures) [10]. An aluminum insulated metal substrate (Al-IMS) was used as board material. The unpackaged blue and white flipchip LEDs were soldered directly on an Al-IMS board. Examples are shown in Figure 3. Figure 3. Used fine-pitch 5 LED string Al-IMS board with white (left picture) and blue (right picture) high power WL-CSP LEDs. The LED modules were manufactured using a standard SMD process, i.e. solder paste stencil printing (PBT Go3v), pick and place (Finetech Fineplacer Pico) and vacuum assisted reflow (Unitemp RSS-160). The solder joint provides the mechanical and thermal interconnection between the LED and the PCB. The solder joint need to withstand the high mechanical stress due to coefficients of thermal expansion (CTE) mismatch. In addition it has also to relax the thermos-mechanical stress and not to transfer it to the LED die, i.e. it has to have a high thermo- mechanical fatigue resistance. To evaluate the impact of the solder joint on the failure modes four different solder alloys were used: Batch 1: Au80Sn20 Preform Batch 2: Sn62Pb36Ag2 Type 4 Batch 3: Sn96.5Ag3Cu0.5 (SAC305) Type 4 Batch 4: Sn89.7Ag3.4Cu0.7Bi3.2Sb3.0 Type 4 (Special high reliability solder paste) To avoid large differences due to voiding of the solder paste a vacuum assisted solder process was used. The initial quality assessment of the samples is obtained by the combination of two non-destructive inspection methods: X-Ray inspection for void analysis TTA to inspect initial integrity of the thermal path (Mentor Graphics T3ster) 1137

3 By combination of the two measurement methods the quality of the sample directly after the assembly is guaranteed. Failures due to bad wetting and failures in the board (delamination between dielectric layer and Al-core or copper electrical layer) and the LED package which are not detectable by X-Ray can be observed by TTA. Afterwards, the LED modules are exposed to thermal shock tests (-40 C to +125 C) and the TTA is performed repeatedly. For three boards also a scanning acoustic microscopy (SAM) analysis was performed to prove the feasibility of this method for WL-CSP LEDs. B. The Transient Thermal Analysis For high power LEDs the thermal resistance of the assembly needs to be as low as possible. A highly heat conducting thermal path from the heat generation in the LED die, through the solder joint to the PCB, and finally over the heat sink to the ambient is essential. Many different defects can have an influence on the thermal path of an electronic system: on the one hand the faults during and directly after the production process, e.g. bad wetting of solder pads or voids inside the solder joint, and on the other hand the typical aging failures like cracks in the solder joint or delamination in the package as a result of the thermo-mechanical stress in the electronic system [11]. To evaluate the quality of the solder joint, the TTA is a powerful non-destructive inspection technique. The TTA measurements are performed as follows: a constant heat current I drive (1 A) is applied initially until the thermal equilibrium is reached in the LED module. Afterwards the current source switches to a smaller measurement current I sense (20 ma). The cooling down of the system into its new thermal equilibrium is detected by measuring time resolved the V f(t). For TTA the forward voltage (V f) of the LED junction is measured time resolved after a change of thermal load The general method is described in the JEDEC Standard JESD51-14 [12]. (1) The V f(t) = (V f(t) V f(t 0)) is dependent on the LED junction temperature difference T j(t) = (T j(t) T j(t 0)) (see (1)) and can be linearly approximated in an adequate small temperature range, e.g. below 50 C [1]. The time t = 0 denotes the change of the thermal load. The proportionality factor S VF between temperature and forward voltage of the LED, called the sensitivity, may vary for single LEDs from batch to batch. The typical value for the sensitivity for high power LEDs is around 2 mv/k. The reciprocal of the sensitivity is called k-factor. In this present paper the k-factor (proportional factor) free method, also called relative thermal resistance (relative R th), is used as described in [13]. The thermal load P th and the k- factor are not measured but normalized because only the relative changes of the transient signal have to be evaluated to observe structural defects. Starting with the measurement of the time dependent V f(t) the transient thermal resistance R th_real is obtained by: (2) Here P th denotes the power step, i.e. the difference of the thermal load when switching from heat-current to sensecurrent, and V f(t 0) the forward voltage at time t 0 as early as measurement of the thermal response is possible, i.e. as soon as the electrical response due to the junction capacity and further parasitic inductances and capacities decayed. This time delay is called the dead time. In practice the dead time is around 20 μs. With shorter dead time more information about the inner structure of the LED can be investigated. Due to the exponential time dependence the substitution z = ln(t) is introduced and the logarithmic time derivation of the transient thermal impedance is calculated. Then the function B(z) can be defined as: (3) The sensitivity factor and thermal load (P th) is transferred into a simple axis offset which can be eliminated by shifting the B(z) = B(ln(t)) curves perpendicular to the z-axis (t-axis) [14]. This is also called normalization and therefore B(z) is the normalized derivation of V f. For reference known good LED samples are used as reference, i.e. golden sample. The assembly quality of the this sample is completely analyzed. For the golden samples the sensitivity and thermal load are determined and this module requires a high quality solder joint and a faultless LED. As long as the thermal paths of the samples are comparable, the B(z) curves are also identical beside an axis offset (and also beside of measurement noise). This axis offset (shift perpendicular to the z-axis) is eliminated by a simple least square fit in a chosen normalization interval [11]. Changes in the thermal path influence the shape of the B(z) curve. The difference between the B(z) curve shape of the golden sample and the shape of the B(z) curve of the measured sample indicates failures. Therefore, with the normalized derivative it is possible to locate the defect in the thermal path. Especially the peak height and peak position describe the quality of the solder joint [11]. For the evaluation of the V f test result of the transient thermal analysis also the structure function is the common tool. In this graphical method on the Y-axis the thermal capacity C th is plotted and on the X-axis the absolute thermal resistance R th. For the correct absolute R th value of a LED the sensitivity and the thermal load are necessary. This measurements generate additional time and effort in the test and analysis process [11]. The validation of the thermal path used in the present paper is described in [13] and [15]. This paper focuses on the method to distinguish different failure modes based on TTA in combination with finite element (FE) simulations. C. Finite Element Method Analytical models in engineering have several practical uses: 1) rapid design optimization during the development 1138

4 phase of a product, 2) predicting field use limits, and 3) failure analysis of product returned from the field or failed in a qualification test [16]. To analyze failure modes in a LED module the finite element simulation is an important tool. Steady state thermal finite element simulations are well established and also known for WL-CSP LEDs [7]. For this study, Solid-Works Flow (FloEFD) from Mentor Graphics, was used to simulate the heat transfer process in LEDs. Two important features of this software are the capability of definition of global mesh based on geometry and the possibility of importing a 3D-Model of the LED, which is based on original CAD data. The model size was about 8 million cells. The multiple and complex die-layers are simplified to limit the level of refinement and number of cells. The effective heated die area of the package was 1 mm 2. The values for the thermal conductivity of the materials were taken from literature [17]. A heat load of W was distributed on the epitaxial layer. A temperature boundary condition T = 25 C was applied at the bottom of the temperature controlled plate. Figure 4. FEM model of the WL-CSP LED and the heat distribution after the steady-state simulation. A 3D-FE model, see Figure 4, was set-up and a steady state thermal simulation was run firstly, which simulates the equilibrium temperature distribution after heating. Starting with the temperature distribution of the steady state simulation the transient thermal simulation calculates the cooling down phase until the whole package reaches ambient temperature (25 C). After validation and calibration (see [17]), this model is used to analyzes the impact of different failures in the package on the transient temperature curves. This can be: Cracks in the solder joint Delamination between the redistribution layer and solder joint Delamination between the EPI and redistribution layer Delamination between the sapphire and EPI By the FE analysis the transient thermal measurements can be interpreted and failure analysis of the LED can be provided. Typically cracks and delaminations are growing from the outer edge to the inside [17]. Figure 5. Examples of the solder crack failure mode in the LED package FEM model (bottom view on the solder joint). In Figure 5 are examples of the solder crack failure mode in the LED package illustrated. For delaminations it is the same procedure. D. In-Situ Test HTOL and Thermal Shock To predict the devices durability and to evaluate the consequences of the thermo-mechanical stress, accelerated reliability testing is necessary. Here, temperature shock tests are suitable methods [9]. After initial transient thermal and X-Ray measurements of the test samples, the samples were exposed to a passive temperature shock test -40 C / +125 C (temperature profile see Figure 6). Within a validation of electronic systems in the automotive industry and the environmental reliability test specification this thermal shock profile is a typical test to prove the reliability of the solder joints. All norms in this context are defined by the Automotive Electronics Council (AEC). For automotive LED modules the norm AEC-Q101 (Failure Mechanism Based Stress Test Qualification for Discrete Semiconductors in Automotive Applications) is used (see [18]). The temperature shock test, also called temperature cycling, is one test required in the standard. Here the AEC-Q Standard refers to the JEDEC Standard JESD22-A104D (see [19]) in which the temperature profile is described in detail. Figure 6. Temperature profile of the thermal shock test according to AEC- Q101 described in [18]. A new method is the application of the TTA In-Situ during combination of high temperature operational life (HTOL) and 1139

5 also temperature cycle testing. The new developed construction is illustrated in Figure 7. Figure 8. Temperture difference of T j(t) (left picture) and b(z) (right picture) of different solder crack failures. Figure 8 shows the temperature difference of T j(t) and b(z) curves of the different failure modes. It is visible that the increase of the peak height (red circle) correlate to the increase of the solder crack. Also the maximum of the junction temperature T j depends from the size of the solder crack. Figure 7. Equipment for TTA In-Situ during combination of high temperature operational life (HTOL) and temperature cycle testing. The LED modules are mounted on a temperature controlled hot plate which is temperature cycled between low (T min) and high (T max) temperature. The LEDs are driven at nominal current during the dwell time at T max. For a short time the LEDs are switched off and the TTA is measured. The transient thermal analysis is also performed at cold conditions. Therefore the LEDs are switched on and off for short times. In industry more and more combined stress tests are introduced to accelerated stress testing and to access quicker potential failures. Here test qualification for integrated circuits (see [20]) are imitated. During the switch on time the LEDs are driven at their maximal allowed junction temperature (T case = 125 C). This is in accordance with the high temperature operational life test (HTOL) which is defined in the AEC-Q101 (1000 h at 125 C (see [21]). This combination is especially useful, because the TTA is done by shortly switching off the nominal drive current to a small detection current. Due to differences in thermomechanical stress under hot and cold conditions, additional information can be obtained. Currently the first tests are ongoing. Previous result are published in [8]. III. RESULTS A FEM simulation of the different failure modes were developed. In parallel real samples were assembled and analyzed. After initial quality checks the test samples were exposed to temperature shock test -40 C / +125 C and after a defined amount of cycles (500, 1000, 1500) the TTA is performed repeatedly. A. Results of the Finite Element Analysis With the FEM analysis the impact of different failures in the LED package on the transient temperature curves can be analyzed. Like in the TTA the transient temperature curve (or the forward voltage V f) is simulated time resolved. Due to the exponential time dependence, the substitution z = ln(t) will be introduced and the logarithmic time derivation b(z) is calculated. Figure 9. b(z) curves of different delamination failure modes in the LED package. Figure 9 illustrates b(z) curves of different delamination failure modes in the LED package. It is visible that the separation of the curves compared to the curve without any crack or failure starts in different time zones. The separation of the delamination under the EPI failure curve (blue line) starts at ca. 1 μs (red circle) and the delamination under the redistribution layer failure curve (green line) at ca. 3 μs (purple circle). The curve of the delamination on the EPI failure (cyan line) shows a total different behavior. This is a consequence of change of the thermal path upside through the sapphire to the phosphor. Due to the separation of the curves in this early time zone a transient thermal measurement equipment with a dead time < 10 μs is necessary Out of the transient simulated temperature curves also the structure functions were calculated. 1140

6 Figure 10. Structure functions of different solder crack failures. Figure 10 illustrates the structure function curves of different solder crack failures. It is visible that for solder joint cracks until 20 % (green line) only the vertical end of the structure function is moving right and the thermal resistance R th increases. For bigger solder cracks than 20 % additional to this changes also the early area (see zoomed area in Figure 10) of the structure function is changing. This is due to the change in the heat path within the EPI due to the cracks. Figure 12. Measured b(z) curve of a real WL-CSP LED (green line) and simulated b(z) curves with different solder cracks. In Figure 12 a comparison between a measured and simulated transient thermal curve is visible. For the first tests the simulated curves match acceptable to the measured curve. Further improvements of the FEM model are ongoing. The difference in the curves over 0.2 s are due to the different attachments to the heatsink of the simulated and real measured LED board. B. Solder Joint Inspection by the Transient Thermal Analysis With the methodology of the relative transient thermal analysis (see II.B) the normalized derivation (B(z) of V f(t)) was evaluated. In previous experiments WL-CSP LED directly soldered with SAC305 on Al-IMS PCBs, were temperature cycled to 1000 cycles and investigated also using TTA measurements and cross sections were done. In Figure 13 an example of a LED module with a solder crack is illustrated. Figure 11. Structure functions of different solder crack and delamination failures. In Figure 11 the structure functions of different solder cracks and delamination failures are visible. The separation of the structure functions in the early area (see zoomed section) can be correlated to the different failure modes. Figure 13. Initial B(z) (red line) and B(z) after 1000 cycles thermal shock (blue line) of a blue WL-CSP LED (left picture) and an image of the cross section of the board (right picture). It is visible that the shape of the initial B(z) curve and the shape of the B(z) curve after 1000 cycles thermal shock are comparable. Only an increase of the peak height is visible, but no difference in the early time area is detectable. In this example the increase of the peak height is Like described in [15] it is possible to correlate the increase of the peak height of B(z) to the increase of the thermal resistance R th. A peak increase of correspond to an increase of the thermal resistance R th of ca. 2 K/W. 1141

7 For the new assembled samples after initial quality checks the samples were exposed to temperature shock test - 40 C / +125 C and after a defined amount of cycles (500, 1000, 1500) the TTA is performed repeatedly. TABLE 1. OVERVIEW OF THE DIFFERENCES OF CURVE SHAPE IN EARLY TIME AREA TOGETHER WITH AN INCREASE OF THE PEAK AND ONLY PEAK INCREASE OF THE TTA AFTER 0 CYCLES AND 500 CYCLES THERMAL SHOCK Solder Alloy No. of Samples Difference of curve shape between 0 Cycles and 500 Cycles Early time area and Only peak peak increase increase Au80Sn Sn62Pb36Ag Sn96.5Ag3Cu Sn89.7Ag3.4Cu0.7Bi3.2Sb Table 1 is an overview of the differences of the curve shape of the TTA after 0 cycles and 500 cycles thermal shock. It is visible that no significant change of the curve shape is detectable. Only some of the samples soldered with the hard AuSn solder and one soldered with SnAgCuBiSb solder show a significant change of the curve shape after 500 cycles in the early time area indicating structural failures in the interconnect. Because of the high strength of gold-tin solder crack are unlikely for the AuSn solder joints. Figure 14 illustrates the initial B(z) (red line) and B(z) after 500 cycles thermal shock (blue line) of a white WL-CSP LED soldered with SnPbAg solder (top picture) and of a blue WL- CSP LED soldered with SnAgCu alloy (bottom picture). The graph shows that for this two examples the shape and peak height of the curves is almost equal. The difference between seconds (green circle) are the result of different TIM connections of the LED board to the heat sink of the controlled temperature table and are irrelevant. In Figure 14 also the high signal noise until 10 μs (black circle) as a consequence of the switch from I drive to I sense is obvious. In practice this long dead time prevents a more precise analysis of different failure modes of a LED module. Therefore the measurement hard- and software are in improvement. Also further developments of the signal-tonoise (S/N) ratio and the dead time in the early time domain (< 10 μs) are ongoing. Because of the different CTEs of the LED chip and the Al- IMS PCB the solder joint is exposed to thermo-mechanical stress which it has to compensate. Because of the larger modulus of elasticity of AuSn alloy and the high yield strength compared to tin-rich solder the AuSn solder joint transfers more stress to the package and more delamination in the LED package is expected. Figure 14. Initial B(z) (red line) and B(z) after 500 cycles thermal shock (blue line) of a white WL-CSP LED soldered with SnPbAg solder (top picture) and of a blue WL-CSP LED soldered with SnAgCu alloy (bottom picture). Figure 15. Initial B(z) (red line) and B(z) after 500 cycles thermal shock (blue line) of a blue WL-CSP LED soldered with AuSn solder (top picture) and of a white WL-CSP LED soldered with SnAgCuBiSb alloy (bottom picture). 1142

8 Some of the samples solder with AuSn and SnAgCuBiSb (e.g. see Figure 15) show a difference in the early time area (green circle) of the B(z) curve. This is an indication of delamination. This will be evidenced by cross sections of the affected LED boards. C. Solder Joint Inspection by X-Ray After the soldering process X-Ray images have been taken of the solder joints. This allowed to detect errors in the solder joint, like voids, or not wetted pad. The acoustic wave is focused and transported to the sample via a coupling medium (usually water) [22]. Typical scanning speeds are s/frame for operating in the frequency range of GHz, and for a field a view of up to 0.5 x 0.5 mm [22]. SAM can be used in different modes. The most used mode is the Confocal Scanning Acoustic Microscopy (C-SAM) [23]. This technique produces a horizontal section image of the analyzed sample. Figure 16. Examples of X-Ray images of the WL-CSP LED string soldered with SnPbAg solder (top picture), a sample soldered with SAC305 solder (middle picture) and a sample soldered with SnAgCuBiSb solder (bottom picture). Figure 16 illustrates examples of X-Ray images of the WL-CSP LED string soldered with SnPbAg solder (top picture), a sample soldered with SAC305 solder (middle picture) and a sample soldered with SnAgCuBiSb solder (bottom picture). No significant failures in the solder joints are detectable. The samples soldered with SnAgCuBiSb solder alloy show a higher share of voids compared to the samples soldered with SAC305 or SnPbAg. This confirms some internal studies that alloys with more than three elements show a higher void percentage. The percentage of voids are for all samples under 10 % void area to pad area ratio and therefore in an acceptable range. The solder beads are the consequence of the very close placement of the LED design with a solder resist thickness of too large thickness. However they do not influence the structural reliability. D. Solder Joints Inspection with Scanning Acoustic Microscopy The scanning acoustic microscopy (SAM) is a wellestablished and useful technique for imaging and investigating the properties of materials such as metals, ceramics and composites, as well as integrated circuits and biological samples [22]. SAM is a non-destructive, imaging method, which uses ultrasonic with high frequencies [22]. Defects in the inner structure of an electronic component such as cracks, delaminations and voids can be detected. Figure 17. Examples of X-Ray (left pictures), SAM (middle pictures) and microscope (right pictures) images of the WL-CSP LEDs directly after the assembly. The top pictures are a blue LED without phosphor, the bottom pictures are a white LED with phosphor. In Figure 17 examples of X-Ray (left pictures), SAM (middle pictures) and microscope (right pictures) images of the WL-CSP LEDs directly after the assembly are illustrated. The top pictures are a blue LED without phosphor, the bottom pictures are a white LED with phosphor. The top pictures of Figure 17 (blue LED, without phosphor) show, that the voids in the solder joint, which are detected with X-Ray, are also visible in the SAM image. In the two samples (total 10 LEDs) no defects like delamination can be detected. After 500 cycles of a temperature shock test (-40 C / +125 C) the samples where SAM analyzed again. Also there no delamination are visible. This is in accordance with the TTA results. In Figure 17 is illustrated that with phosphor no SAM analysis of the inner LED structure is possible. The SAM image does not fit to the X-Ray image. The phosphor on the blue LED chip produce too much reflection of the ultrasonic signal. IV. CONCLUSION By the TTA, the structural integrity of a LED module can be resolved and cracks or delamination can be identified. The 1143

9 change in the thermal path of the package can be compared with the TTA results of the initial reference sample, measured directly after the assembly. The FEM simulation results show that solder cracks increase the peak height of the derivative of the transient thermal b(z) curves. A delamination of an inner layer of the LED package creates additionally to the increase of the peak height also a separation of the b(z) curves between 1 μs and 5 μs. Therefore a transient thermal measurement equipment with a dead time < 10 μs is necessary which is currently under development. For correlation of these results LED modules soldered with different solder alloys were produced. After 500 thermal shock cycles to the LEDs the TTA was performed again. No significant change of the peak height of B(z) was observed. In especially for samples soldered with AuSn failures were observed with deviation in the early time range, which is an indication of a delamination close to the LED EPI. For blue LEDs without phosphor converter also SAM is a possible method to analyze the inner structure of a LED module. However for white LEDs, the phosphor converter disturbs the acoustic path and detection is not possible. Here TTA is the solution for failure identification. The combination of operational life and temperature cycle and In-Situ TTA is a suitable test to gain additional information by investigating the structural changes at different temperatures, whilst accelerating the degradation of the LED module. The experimental results on the application WL-CSP LEDs show additionally, that the reliability of the solder joint depends on the PCB design and the solder material transferring the stress from PCB to the LED die. ACKNOWLEDGMENT Special thanks go to Fraunhofer IZM team, Innovation & Design-In Automotive Team Lumileds Germany GmbH and the colleagues from the TH Ingolstadt for the helpful support. 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