DESCRIPTIO. LTC SMBus/I 2 C Accelerator* FEATURES APPLICATIO S TYPICAL APPLICATIO

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SMBus/I 2 C Accelerator* FEATRES Improves SMBus/I 2 C TM Rise Time Transition Ensures Data Integrity with Multiple Devices on the SMBus/I 2 C Improves Low State Noise Margin Wide Supply Voltage

1 SMBus/I 2 C Accelerator* FEATRES Improves SMBus/I 2 C TM Rise Time Transition Ensures Data Integrity with Multiple Devices on the SMBus/I 2 C Improves Low State Noise Margin Wide Supply Voltage Range: 2.7V to 6V Parallel Multiple Devices for Increased Drive Low Profile (1mm) SOT-23 (ThinSOT TM ) Package APPLICATIO S Notebook and Palmtop Computers Portable Instruments Battery Chargers Industrial Control Application TV/Video Products ACPI SMBus Interface DESCRIPTIO The LTC is a dual SMBus active pull-up designed to enhance data transmission speed and reliability under all specified SMBus loading conditions. The is also compatible with the Philips I 2 C Bus. The allows multiple device connections or a longer, more capacitive interconnect, without compromising slew rates or bus performance, by supplying a high pull-up current of 2.2mA to slew the SMBus or I 2 C lines during positive bus transitions During negative transitions or steady DC levels, the sources zero current. External resistors, one on each bus line, trigger the during positive bus transitions and set the pull-down current level. These resistors determine the slew rate during negative bus transitions and the logic low DC level. The is available in a -pin SOT-23 package., LTC and LT are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. I 2 C is a trademark of Philips Electronics N.V. *.S. Patent No. 6,60,17 TYPICAL APPLICATIO C1 0.1µF SMBus1 Comparison of SMBus Waveforms for the vs Resistor Pull-p SMBus SCL SDA GND SMBus2 R P1 R P2 1V/DIV R PLL-P = 1.8k DEVICE 1 DEVICE N TA01 = 1µs/DIV TA02 C LD = 200pF f SMBus = 100kHz 1

2 ABSOLTE MAXIMM RATGS W W W (Note 1) Supply Voltage ( )... 7V SMBus1, SMBus2 Inputs V to ( + 0.3V) Operating Ambient Temperature Range C... 0 C to 70 C I... 0 C to 8 C Junction Temperature C Storage Temperature Range... 6 C to 10 C Lead Temperature (Soldering, 10 sec.) C PACKAGE/ORDER FORMATION 1 GND 2 NC 3 TOP VIEW S PACKAGE -LEAD PLASTIC TSOT-23 T JMAX = 12 C, θ JA = 26 C/ W SMBus1 SMBus2 W ORDER PART NMBER CS IS S PART MARKG LTHE LTA9 Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = 2 C. = 2.7V to 6V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS M TYP MAX NITS Supply Voltage Range V I CC Supply Current SMBus1 = SMBus2 = 1 80 µa I PLL-P Pull-p Current Positive Transition on SMBus ( Figure 1) ma Slew Rate = 0./µs, SMBus > V THRES V THRES Input Threshold Voltage Slew Rate = 0./µs (Figure 1) V SR THRES Slew Rate Detector Threshold SMBus > V THRES V/µs t r SMBus Rise Time Bus Capacitance = 200pF (Note 2) µs Standard Mode I 2 C Bus Rise Time Bus Capacitance = 00pF (Note 3) µs f MAX SMBus Maximum Operating Frequency (Note ) 100 khz Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The rise time of an SMBus line is calculated from (V IL(MAX) 0.1) to (V IH(M) + 0.1) or 0.6 to 2.2. This parameter is guaranteed by design and not tested. With a minimum initial slew rate of 0./µs, a minimum pull-up current of 1mA and a maximum input threshold voltage of 0.9V: Rise Time = [(0.9V 0.6)/0./µs] + [( V) 200pF/1mA] = 0.77µs Note 3: The rise time of an I 2 C bus line is calculated from V IL(MAX) to V IH(M) or 1. to 3V (with = ). This parameter is guaranteed by design and not tested. With a minimum boosted pull-up current of 1mA: Rise Time = (3V 1.) 00pF/1mA = 0.6µs Note : This parameter is guaranteed by design and not tested. 2

3 TYPICAL PERFORMANCE CHARACTERISTICS W PLL-P CRRENT (ma) Pull-p Current = 6V 2.2 = = 2.7V TEMPERATRE ( C) G01 PLL-P CRRENT (ma) Pull-p Current vs SMBus Voltage 0 0 = 6V = = 2.7V SMBus VOLTAGE (V) LT169 G02 PT THRESHOLD VOLTAGE (V) = Input Threshold Voltage = 6V = 2.7V TEMPERATRE ( C) 169 G03 SLEW RATE DETECTOR THRESHOLD (V/µs) Slew Rate Detector Threshold = 6V = 2.7V = TEMPERATRE ( C) 169 G0 SPPLY CRRENT (µa) Standby Mode Supply Current = 6V = = 2.7V TEMPERATRE ( C) G0 3

4 P FNCTIONS (Pin 1): Power Supply Input. can range from 2.7V to 6V and requires a 0.1µF bypass capacitor to GND. Supply current is typically µa when the SMBus or I 2 C lines are inactive (SCL and SDA are a logic high level). GND (Pin 2): Ground. NC (Pin 3): No Connection. SMBus2 (Pin ): Active Pull-p for SMBus. SMBus1 (Pin ): Active Pull-p for SMBus. BLOCK DIAGRAM W 1 CHANNEL ONE 2.2mA SLEW RATE DETECTOR SMBus1 GND 2 + VOLTAGE COMP CONTROL LOGIC 0.6 V REF SMBus2 CHANNEL TWO (DPLICATE OF CHANNEL ONE) BD TEST CIRCITS C1 0.1µF SMBus1 GND SMBus2 200µA PLL-P = 2.2mA (TYP) I PLL-P = V R 1kΩ 200µA (TYP) 0µA TEST RAMP VOLTAGE LT HP BSS28 V R 1k TEST RAMP VOLTAGE 0V V THRES 0./µs F01b 10V F01a Figure 1

5 APPLICATIONS FORMATION SMBus Overview W SMBus communication protocol employs open-drain drives with resistive or current source pull-ups. This protocol allows multiple devices to drive and monitor the bus without bus contention. The simplicity of resistive or fixed current source pull-ups is offset by the slow rise times resulting when bus capacitance is high. Rise times can be improved by using lower pull-up resistor values or higher fixed current source values, but the additional current increases the low state bus voltage, decreasing noise margins. Slow rise times can seriously impact data reliability, enforcing a maximum practical bus speed well below the established SMBus maximum transmission rate. Theory of Operation The overcomes these limitations by providing a 2.2mA pull-up current only during positive bus transitions to quickly slew any bus capacitance. Therefore, rise time is dramatically improved, especially with maximum SMBus loading conditions. The has separate but identical circuitry for each SMBus output pin. The circuitry consists of a positive edge slew rate detector and a voltage comparator. The 2.2mA pull-up current is only turned on if the voltage on the SMBus line voltage is greater than the 0.6 comparator threshold voltage and the positive slew rate of the SMBus line is greater than the 0.2V/µs threshold of the slew rate detector. The pull-up current remains on until the voltage on the SMBus line is within 0. of and/or the slew rate drops below 0.2V/µs. Selecting the Values of R S and R P An external pull-up resistor R P is required in each SMBus line to supply a steady state pull-up current if the SMBus is at logic zero. This pull-up current is used for slewing the SMBus line during the initial portion of the positive transition in order to activate the 2.2mA pull-up current. sing an external R P to supply the steady state pull-up current permits the user the freedom to adjust rise time versus fall time as well as defining the low state logic level (V OL ). For I/O stage protection from ESD and high voltage spikes on the SMBus, a series resistor R S (Figure 2) is sometimes added to the open-drain driver of the bus agents. This is especially common in SMBus-controlled smart batteries. Both the values of R P and R S must be chosen carefully to meet the low state noise margin and all timing requirements of the SMBus. A discussion of the electrical parameters affected by the values of R S and R P, as well as a general procedure for selecting the values of R S and R P follows. R P R S R ON Figure F02 C BS SMBus Low State Noise Margin A low value of V OL, the low state logic level, is desired for good noise margin. V OL is calculated as follows: V OL = (R L )/(R L + R P ) (1) R L is the series sum of R S and R ON, the on-resistance of the open-drain driver. Increasing the value of R P decreases the value of V OL. Increasing R L increases the value of V OL. Initial Slew Rate The initial slew rate, SR, of the Bus is determined by: SR = ( V OL )/(R P C BS ) (2) SR must be greater than SR THRES, the slew rate detector threshold (0./µs max) in order to activate the 2.2mA pull-up current.

6 APPLICATIONS FORMATION SMBus Rise Time 6 W Rise time of an SMBus line is derived using equations 3, and. t r = t 1 + t 2 (3) t 1 = R P C BS ln[(v THRES )/ (V ILMAX 0.1 )] () if (V ILMAX 0.1) > V THRES, then t 1 = 0µs. t 2 = R P C BS ln{[v IHM (R P I PLL-P )]/[V THRES (R P I PLL-P )]} () By ignoring the current through R P, a simplified version of equation 3 is obtained: t 2 = (V IHM V THRES ) C BS /I PLL-P (6) For an SMBus system, V ILMAX = 0.8V and V IHM = 2.1V. For the, typically V THRES = 0.6 and I PLL-P = 2.2mA. C BS is the total capacitance of the SMBus line. Increasing the value of R P increases the rise time. SMBus Fall Time Fall time of an SMBus line is derived using equation 7: t f = R T C BS ln{[0.9 (R P + R L ) R L ]/ [(V ILMAX 0.1) (R P + R L )/ R L ]} (7) where R T is the parallel equivalent of R P and R L. The rise and fall time calculation for an I 2 C system is as follows. I 2 C Bus Rise and Fall Time Rise time of an I 2 C line is derived using equation 8. t r = R P C BS ln{[v IHM (R P I PLL-P )]/ [V ILMAX (R P I PLL-P )]} (8) Fall time of an I 2 C line is derived using equation 9: t f = R T C BS ln{[(v IHM / ) (R P + R L ) R L ]/ [(V ILMAX / ) (R P + R L ) R L ]} (9) For an I 2 C system with fixed input levels, V ILMAX = 1. and V IHM = 3V. For an I 2 C system with related input levels, V ILMAX = 0.3 and V IHM = 0.7. C BS is the total capacitance of the I 2 C line. A general procedure for selecting R P and R L is as follows: 1. R L is first selected based on the I/O protection requirement. Generally, an R S of 100Ω is sufficient for high voltage spike and ESD protection. R ON is determined by the size of the open-drain driver, a large driver will have a lower R ON. 2. Next, the value of R P is determined based on the rise and fall time requirements using equations 3 to 7 (for an SMBus system) or 8 and 9 (for an I 2 C system). The value chosen for R P must ensure that both the rise and fall time specifications are met simultaneously. 3. After R P and R L are selected, use equations 1 and 2 to check if the V OL and SR requirements are fulfilled. If SR is too low, decrease the value of R P. If V OL is too high, increase the value of R P. SMBus Design Example Given the following conditions and requirements: = 3.3V nom V OL = 0.V max C BS = 200pF max V ILMAX = 0.8V, V IHM = 2.1V t r = 0.8µs max, t f = 0.3µs max If an R S of 00Ω is used and the max R ON of the driver is 200Ω, then R L = = 700Ω. sing the max V THRES of 0.9V and a min I PLL-P of 1mA. sing equation 6 to calculate the approximate value of t 2 : t 2 = ( ) [( )/( )] = 0.27µs t 1 = = 0.3µs sing equation to find the required R P to meet t r : R P = t 1 /{C BS ln[(v THRES )/ (V ILMAX 0.1 )]} = 27k R T = (R P R L )/(R P + R L )

7 APPLICATIONS FORMATION W sing equations and to check exact value of t r : t r = 0.3µs + 0.2µs = 0.79µs sing equation 7 to check t f : t f = 0.222µs which is less than 0.3µs. sing equation 1 to check V OL : V OL = ( )/[700 + ( )] = 83mV which is less than 0.V. And using equation 2 to check the initial slew rate: SR = 3.3/[( ) ( )] = 0.61V/µs which is greater than 0./µs. Therefore, the value of R P chosen is 27k. ACK Data Setup Time Care must be taken in selecting the value of R S (in series with the pull-down driver) to ensure that the data setup time requirement for ACK (acknowledge) is fulfilled. An acknowledge is accomplished by the SMBus host releasing the SDA line (pulling high) at the end of the last bit sent and the SMBus slave device pulling the SDA line low before the rising edge of the ACK clock pulse. The 2.2mA pull-up current is activated when the SMBus host releases the SDA line, allowing the voltage to rise above the s comparator threshold of 0.6. If an SMBus slave device has a high value of R S, a longer time is required for this SMBus slave device to pull SDA low before the rising edge of the ACK clock pulse. To ensure sufficient data setup time for ACK, SMBus slave devices with high values of R S, should pull the SDA low earlier. Typically, a minimum setup time of 1.µs is needed for an SMBus device with an R S of 700Ω and a bus capacitance of 200pF. An alternative is that the SMBus slave device can hold SCL line low until the SDA line reaches a stable state. Then, SCL can be released to generate the ACK clock pulse. Connecting Multiple in Parallel The is designed to guarantee a maximum SMBus rise time of 1µs with a bus capacitance of 200pF. In some cases where the bus capacitance is higher than 200pF, multiple s can be connected in parallel to provide a higher pull-up current to meet the rise time requirement. Figure 3 shows a typical application with two s connected in parallel to supply a pull-up current of.ma. SMBus1 SMBus2 GND 1 2 C1 0.1µF 1 2 SMBus1 GND SMBus2 R P1 R P2 SMBus SCL SDA DEVICE 1 DEVICE N f03 Figure 3. Paralleling Two to Provide.mA of Pull-p Current Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 7

APPLICATIONS FORMATION W Comparison of SMBus Waveforms for the vs Resistor Pull-p 1V/DIV R PLL-P = 1.8k 1V/DIV R PLL-P = 10.k = C LD = 200pF f SMBus = 100kHz 1µs/DIV 169 TA03 = 3.

80 BSC 1.0 1.7 (NOTE ) P ONE RECOMMENDED SOLDER PAD LAY PER IPC CALCLATOR 0.80 0.90 0.9 BSC 0.30 0. TYP PLCS (NOTE 3) 0.20 BSC DATM A 1.00 MAX 0.01 0.10 0.30 0.0 REF NOTE: 1.

8 APPLICATIONS FORMATION W Comparison of SMBus Waveforms for the vs Resistor Pull-p 1V/DIV R PLL-P = 1.8k 1V/DIV R PLL-P = 10.k = C LD = 200pF f SMBus = 100kHz 1µs/DIV 169 TA03 = 3.3V C LD = 200pF f SMBus = 100kHz 1µs/DIV 169 TA0 PACKAGE DESCRIPTION 0.62 MAX 0.9 REF S Package -Lead Plastic TSOT-23 (Reference LTC DWG # ) 2.90 BSC (NOTE ) 1.22 REF 3.8 MAX 2.62 REF 1. M 2.80 BSC (NOTE ) P ONE RECOMMENDED SOLDER PAD LAY PER IPC CALCLATOR BSC TYP PLCS (NOTE 3) 0.20 BSC DATM A 1.00 MAX REF NOTE: 1. DIMENSIONS ARE MILLIMETERS 2. DRAWG NOT TO SCALE 3. DIMENSIONS ARE CLSIVE OF PLATG BSC (NOTE 3). DIMENSIONS ARE EXCLSIVE OF MOLD FLASH AND METAL BRR. MOLD FLASH SHALL NOT EXCEED 0.2mm 6. JEDEC PACKAGE REFERENCE IS MO-193 S TSOT RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTC1380/LTC Channel/-Channel Analog Multiplexer with SMBus interface Low R ON and Low Charge Injection LTC Bit Current DAC with SMBus Interface 0µA Full-Scale Current LTC1623 Dual High Side Switch Controller with SMBus Interface 8 Selectable Addresses/16 Channel Capability LTC1663 SMBus Interface 10-Bit Rail-to-Rail Micropower DAC DNL < 0.7LSB Max, -Lead SOT-23 Package LTC169 SMBus Accelerator Includes DC and AC Pull-p Current LT1786F SMBus-Controlled CCFL Switching Regulator 1.2A, 200kHz, Floating or Grounded Lamp Configurations LTC300A-1/LTC300A-2 Hot Swappable 2-Wire Bus Buffers Provides Capacitance Buffering, SDA and SCL Hot Swapping, Level Shifting 8 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA (08) FAX: (08) LT/TP 030 REV A 1K PRTED SA LEAR TECHNOLOGY CORPORATION 1999

DESCRIPTION TYPICAL APPLICATION. LTC Micropower, Regulated 5V Charge Pump in a 5-Pin SOT-23 Package FEATURES APPLICATIONS

DESCRIPTION TYPICAL APPLICATION. LTC Micropower, Regulated 5V Charge Pump in a 5-Pin SOT-23 Package FEATURES APPLICATIONS LTC117- Micropower, Regulated V Charge Pump in a -Pin SOT-23 Package FEATRES ltralow Power: I CC = 6µA Typ Short-Circuit/Thermal Protected V ±% Regulated Output Range: 2.7V to V Output Current: 10mA (