Cypress Semiconductor Technology Qualification Plan

Transcription

1 Cypress Semiconductor Technology Qualification lan QT# VERSION 1.0 November 2008 S8 SONOS Technology Qualification Non-Volatile SRAM roduct Family Qualification Cypress, CMI (Fab 4) CY14B104L/ CY14B104N 4M Non-Volatile SRAM Device CYRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Zhaomin Ji Mira Ben-Tzur rincipal Reliability Engineer Quality Engineering Director (408) (408)

2 S8 SONOS Technology Qualification age 2 of 8 4M nvsram roduct Qual: CY14B104L/ CY14B104N November 2008 ACKAGE QUALIFICATION HISTORY Qual Report Description of Qualification urpose To qualify S8 SONOS technology and 4M nvsram devices CY14B104L / CY14B104N (7C14104AC base die) using S8TNV-5R, fabricated at Cypress Minnesota CMI (Fab4) Date Comp Nov 08

3 S8 SONOS Technology Qualification age 3 of 8 4M nvsram roduct Qual: CY14B104L/ CY14B104N November 2008 RODUCT DESCRITION (for qualification) urpose: Qualification of S8 technology & S8TNV-5R 4M nvsram product at CMI (Fab 4) Marketing art #: CY14B104L / CY14B104N Device Description: 3V Commercial/Industrial, available in 44-Lead TSO II / 48 BGA Cypress Division: Cypress Semiconductor Corporation MID TECHNOLOGY/FAB ROCESS DESCRITION S8TNV-5R 3 Metal Composition: Metal 1: 300Å TiW / 3,200Å Al / 100Å Ti Metal 2: 300Å TiW / 3,200Å Al / 100Å Ti Metal 3: 300Å TiW / 8,000Å Al / 150Å Ti assivation: Si 2 N Å & SiO2 700Å Generic rocess Technology/Design Rule (drawn): S8TNV-5R/0.13µm Gate Oxide Material/Thickness (MOS): Name/Location of Die Fab (prime) Facility: Die Fab Line ID/Wafer rocess ID: 32Å (LV) & 110Å (HV) Cypress Semiconductor -- Bloomington, MN Fab4 / S8TNV-5R ACKAGE / ASSEMBLY INFORMATION Assembly Site: ackage: Mold Compound: Die Attach: Die Size: Leadframe Design: Leadfinish/solder ball: Wire (Al/Au) diam: HIL-M, CML-RA 44-Lead TSO II CEL 9200CYR-R QMI x 332 Mil (3910um x 8435um) C 7025 HALF HARD / 8 DOT SLOTTED RM NidAu 1.0 Mil/Au MSL: 3 Solder Reflow Temp: 260C Note: ackage Qualification details upon request

4 S8 SONOS Technology Qualification age 4 of 8 4M nvsram roduct Qual: CY14B104L/ CY14B104N November 2008 RELIABILITY TESTS ERFORMED ER SECIFICATION REQUIREMENT QT# Qualification Summary Stress/Test High Temperature Operating Life Early Failure Rate (EFR) High Temperature Operating Life Latent Failure Rate (LFR) Test Condition (Temp/Bias) Dynamic Operating Condition, 150 C, 2.7V, 48 Hours JESD22-A-108-B Dynamic Operating Condition, 150 C, 2.7V, 500 Hours JESD22-A-108-B Result /F re/ost LFR AC/DC Char AC/DC Critical arameter Char at LFR 0hrs, 80hrs & 500hrs Endurance 200K 90C, er datasheet Data Retention Cypress Spec C, 1000 Hours Temperature Cycle High Accelerated Saturation Test (HAST) ressure Cooker C to C, JESD22-A Cycs, Require recondition 130 C, 3.63V, 85%RH, JESD22-A-110-B 128 Hours, Require recondition 121 C/100%RH, JESD22-A102-C 168 Hours, Require recondition recondition JESD22 Moisture Sensitivity Electrostatic Discharge Human Body Model (ESD-HBM) Electrostatic Discharge Charge Device Model (ESD-CDM) Electrostatic Discharge Machine Model (ESD-MM) Latch-up Sensitivity 2,200V, JESD22-A114E 500V, JESD22-C101C Cypress Spec V, JESD22-A115-A Cypress Spec V,± 200mA, 125 C, EIA/JESD78 Cypress Spec Age Bond Strength Mil-Std-883, Method 2011 Acoustic (M3) Cypress Spec Soft Error (Alpha article) JESD89A, Cypress Spec Soft Error (Neutron/roton) JESD89A, Cypress Spec SEM X-Section XY audit at center wafer and edge wafer Low Temperature Operating Life Test Dynamic Operating Condition, 2.7V, -30 C, 500 Hours High Temp Steady State Life Test Static Operating Condition, 2.7V, 150 C, 1000 Hours Device Characterization (SS,SF,FS,FF) WLR/Etest/Sort Yield/Class Yield

5 S8 SONOS Technology Qualification age 5 of 8 4M nvsram roduct Qual: CY14B104L/ CY14B104N November 2008 RELIABILITY FAILURE RATE SUMMARY Stress/Test Device Tested/ Device Hours # Fails Activation Energy Thermal AF 4 Failure Rate High Temperature Operating Life Early Failure Rate High Temperature Operating Life 1,2, Long Term Failure Rate 4,283 Devices 0 N/A N/A 0 M 239,500 DHRs FITs 1 Assuming an ambient temperature of 55 C and a junction temperature rise of 15 C. 2 Chi-squared 60% estimations used to calculate the failure rate. 3 Thermal Acceleration Factor is calculated from the Arrhenius equation AF = exp E k A 1 T T1 where: E A =The Activation Energy of the defect mechanism. k = Boltzmann's constant = 8.62x10-5 ev/kelvin. T 1 is the junction temperature of the device under stress and T 2 is the junction temperature of the device at use conditions.

6 S8 SONOS Technology Qualification age 6 of 8 4M nvsram roduct Qual: CY14B104L/ CY14B104N November 2008 Reliability Test Data QT #: Device Fab Lot # Assy Lot # Assy Loc Duration Samp Rej Failure Mechanism STRESS: HIGH TEM DYNAMIC OERATING LIFE-EARLY FAILURE RATE, 150C, 2.7V, Vcc Max CY14B104L (7C14104AC) CML-RA CY14B104L (7C14104AC) CML-RA CY14B104L (7C14104AC) CML-RA CY14B104L (7C14104AC) CML-RA STRESS: HIGH TEM DYNAMIC OERATING LIFE-LATENT FAILURE RATE, 150C, 2.7V, Vcc Max CY14B104L (7C14104AC) CML-RA CY14B104L (7C14104AC) CML-RA CY14B104L (7C14104AC) CML-RA CY14B104L (7C14104AC) CML-RA STRESS: re-/ ost HIGH TEM DYNAMIC OERATING LIFE-LATENT FAILURE RATE CHAR CY14B104L (7C14104AC) CML-RA 80/ CY14B104L (7C14104AC) CML-RA 80/ CY14B104L (7C14104AC) CML-RA 80/ CY14B104L (7C14104AC) CML-RA 80/ STRESS: ENDURANCE, 200K CYCLES, 90C CY14B104L (7C14104AC) CML-RA COM 80 0 CY14B104L (7C14104AC) CML-RA COM 77 0 CY14B104L (7C14104AC) CML-RA COM CY14B104L (7C14104AC) CML-RA COM 80 0 CY14B104L (7C14104AC) / CML-RA COM STRESS: DATA RETENTION, 150C CY14B104L (7C14104AC) CML-RA CY14B104L (WAFER) CML-RA CY14B104L (7C14104AC) CML-RA CY14B104L (WAFER) CML-RA CY14B104L (7C14104AC) N/A CML-RA CY14B104L (WAFER) N/A CML-RA STRESS: ESD-HUMAN BODY CIRCUIT ER JEDEC EIA/JESD22-A114-B, 2,200V CY14B104L (7C14104AC) CML-RA COM 8 0 CY14B104L (7C14104AC) CML-RA COM 8 0 CY14B104L (7C14104AC) CML-RA COM 8 0

7 S8 SONOS Technology Qualification age 7 of 8 4M nvsram roduct Qual: CY14B104L/ CY14B104N November 2008 Reliability Test Data QT #: Device Fab Lot # Assy Lot # Assy Loc Duration Samp Rej Failure Mechanism STRESS: ESD-CHARGE DEVICE MODEL, 500V CY14B104L (7C14104AC) CML-RA COM 9 0 CY14B104L (7C14104AC) CML-RA COM 9 0 CY14B104L (7C14104AC) CML-RA COM 9 0 STRESS: ESD-MACHINE MODEL, 200V CY14B104L (7C14104AC) CML-RA COM 5 0 CY14B104L (7C14104AC) CML-RA COM 5 0 CY14B104L (7C14104AC) CML-RA COM 5 0 STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, 1.98V, RE COND 192 HR 30C/60%RH, MSL3 CY14B104L (7C14104AC) CML-RA CY14B104L (7C14104AC) CML-RA CY14B104L (7C14104AC) CML-RA STRESS: RESSURE COOKER TEST, 121C, 100%RH, 15 sig, RE COND 192 HR 30C/60%RH, MSL3 CY14B104L (7C14104AC) CML-RA CY14B104L (7C14104AC) CML-RA CY14B104L (7C14104AC) CML-RA STRESS: Temperature Cycle COND. C, -65C TO 150C, RE COND 192 HRS 30C/60%RH, MSL3 CY14B104L (7C14104AC) CML-RA CY14B104L (7C14104AC) CML-RA CY14B104L (7C14104AC) CML-RA STRESS: STATIC LATCH-U TESTING, 125C, 5.4V, ±200mA CY14B104L (7C14104AC) CML-RA COM 6 0 CY14B104L (7C14104AC) CML-RA COM 6 0 CY14B104L (7C14104AC) CML-RA COM 6 0 STRESS: AGE BOND CY14B104L (7C14104AC) CML-RA COM 10 0 CY14B104L (7C14104AC) CML-RA COM 10 0 CY14B104L (WAFER) N/A CML-RA COM 10 0 STRESS: ACOUSTIC-MSL3 CY14B104L (7C14104AC) CML-RA COM 15 0 CY14B104L (7C14104AC) CML-RA COM 15 0 CY14B104L (7C14104AC) CML-RA COM 15 0

8 S8 SONOS Technology Qualification age 8 of 8 4M nvsram roduct Qual: CY14B104L/ CY14B104N November 2008 Reliability Test Data QT #: Device Fab Lot # Assy Lot # Assy Loc Duration Samp Rej Failure Mechanism STRESS: SER ALHA ARTICLE, 3-TEM, 3-VOLTAGE, FIT=550 85C, Vcc Nom CY14B104L (7C14104AC) CML-RA COM 3 0 CY14B104L (7C14104AC) CML-RA COM 3 0 CY14B104L (7C14104AC) CML-RA COM 3 0 STRESS: SER NEUTRON/ROTON CY14B104L (7C14104AC) N/A CML-RA COM 3 0 STRESS: LOW TEMERATURE OERATING LIFE TEST, -30C, 2.7V, Vcc Max CY14B104L (7C14104AC) CML-RA STRESS: HIGH TEM STEADY STATE LIFE TEST, 150C, 2.7V, Vcc Max CY14B104L (7C14104AC) CML-RA