Software Defined Radio A High Performance Challenge

Transcription

1 Software efined adio A High Performance Challenge PFL, Lausanne, Switzerland, September 2006 Yuan Lin 1, Hyunseok Lee 1, Mark oh 1, Yoav Harel 1, Sangwon Seo 1, ob Mullenix 1 Scott Mahlke 1, Trevor Mudge 1, Chaitali Chakrabarti 2, Krisztian Flautner 3 1 Advanced Computer Architecture Lab, University of Michigan 2 epartment of lectrical ngineering, Arizona State University 3 AM, Ltd. 1

2 Anatomy of 3G Cellular Phone luetooth SP+ASCs GPS SP+ASCs GPS Analog ASCs -CMA luetooth Analog Analog ASCs S aseband Frontend Processor -CMA ASCs GPP+SP+ASCs GPP+SPs Analog ASCs Software efined adio (S): Use of software routines instead of ASCs for physical layer operations of wireless protocol systems Analog ASCs Power Manager Power Manager Application Processor GPP+SP GPP Transport Network Link MAC Camera Keyboard isplay Speaker SP+ASCs SPs Microphone PHY 2

3 Advantages of Software efined adio Multi-mode operations Lower costs Faster time to market Prototyping and bug fixes Chip volumes Longevity of platforms Protocol complexity favors software dominated solutions nables future wireless communication innovations Cognitive radio 3

4 hy is S Challenging? 1000 S esign Objectives for 3G and ifi Throughput requirements 40Gops 100 peak throughput Peak Performance (Gops) Power budget 10 Mobile S equirements 100 Mops/m 10 Mops/m etter Power fficiency 100m~500m peak power T C6x mbedded SPs 1 Mops/m General Purpose Processors Pentium M M Cell High-end SPs Power (atts) 4

5 The Anatomy of ireless Protocols -CMA Physical Layer Processing Fron tend / A A / LPF-Tx scrambler spreader nterleaver searcher LPF-x descrambler despreader. descrambler despreader combiner Transmitter Channel encoder eceiver Channel deinteleaver decoder (turbo/viterbi) Upp er layers 1. Filtering: suppress signals outside frequency band 2. Modulation: map source information onto signal waveforms 3. Channel stimation: stimate channel condition for transceivers 4. rror Correction: correct errors induced by noisy channel 5

6 Spreader/espreader Allow the transmission of several signals at the same time. (x[n] and y[n] in the below diagram) t is based on the orthogonality between spreading codes c i [n] c i [n] N! 1 1 N & n= 0 " 1, if i = j ci[ n] # c j[ n] = $ % 0, otherwize <orthogonality between codes> x[n] y[n] c j [n] c j [n]!! x[n] y[n] spreader despreader 6

7 Scrambler/escrambler andomize the output signal by multiplying pseudo random sequence so called scrambling code. Allow multiple terminals to communicate at the same time. Amount of operation : ~ 3 Gops c sc,i [n] c* sc,i [n] x[n] Complex multiplication Complex multiplication x[n] y[n] Complex multiplication Complex multiplication y[n] c sc,j [n] Terminal 1, with scrambling code n Scrambler c* sc,j [n] Terminal 2, with scrambling code m escrambler 7

8 ake eceiver Multipath fading ake receiver mitigates multipath fading effect Multipath fading is a major cause of unreliable wireless channel characteristic x(t) y(t) = a 0 x(t)+a 1 x(t-d 1 )+a 2 x(t-d 2 ) 8

9 ake eceiver - Functions deally the function of rake receiver is to aggregate the signal terms with proper delay compensation y(t) = a 0 x(t)+a 1 x(t-d 1 )+a 2 x(t-d 2 ) ake receiver r(t) = a 0 x(t)+a 1 x(t-d 1 -d est1 )+a 2 x(t-d 2 -d est2 ) = (a 0 +a 1 +a 2 ) * x(t)! 0! 0 e need to know delay spread of received signal that randomly varies 9

10 ake eceiver etect elay Spread Scan the received signal in frame buffer while computing correlation with scrambling code sequence. Correlation window Correlation esult eceived signal y[ n] = a x[ n] + a x[ n! d ] + a x[ n! d ] a 1 a 2 a 0 0 d 1 d 2 10

11 S Application Specific esign ireless protocols are systems of SP algorithms System-level xample: Specification of -CMA CH channel Algorithm-level xample: mplementation of a 64 point FFT 11

12 System Level esign ecisions System Characteristics 1. Algorithm macro-pipelining with streaming computation 2. Multiple periodic real-time deadlines 3. Low streaming throughput between algorithms SOA Architectural ecisions 1. Multi-core system 2. Communication through MA 3. eterministic hardware behavior 4. Compile-time algorithm mapping and scheduling 5. Low throughput interconnect 4. Heterogeneous interalgorithm communication 6. Multi-level scratchpad memories 12

13 SOA System Architecture 4 Ps static kernel mapping and scheduling SM+Scalar units 1 AM GPP controller scalar algorithms and protocol controls AM System Architecture Local Local Local Mem Mem Mem P P P xecution xecution xecution Unit Unit Unit MA scalar scalar MM SM MM tos & Sto Scalar SM Global Mem Local Mem P xecution Unit SM 13

14 SOA Memory Organization 2-Level scratchpad memories 12K Local scratchpad memory for stream queues 64K global scratchpad memory for large buffers Low-throughput shared bus 200MHz 32-bit bus inter-p communication using MA AM scalar Local Mem P xecution Unit scalar MM Scalar System Architecture MA tos & Sto Local Mem P xecution Unit SM MM Local Mem P xecution Unit SM SM Global Mem Local Mem P xecution Unit 14

15 SP Algorithm Characteristics 8 to 16-bit precision Vector operations Algorithms Type of Computation -CMA Vector idth long vectors constant vector size Static data movement patterns Scalar operations Filter Modulation Channel st. rror Correction Filter Modulation (FFT) Channel st. rror Correction Vector Vector Vector Mixed a Vector Vector Mixed Mixed or

16 SOA P Architecture P SM pipeline SM Memory (8K) 32x 2 issue L (400MHz) - SM + (Scalar or AGU) MA: - mem-to-mem transfer - access global memory 32-way SM S S N nst. Mem. 4K Scalar pipeline AGU pipeline 12bit Vector to Scalar Stage 1 Scalar Memory (4K) AGU Vector to Scalar Stage 2 Scalar to Vector 512bit MA Scalar US AGU 16

17 SOA P SM Pipeline P SM pipeline SM Memory (8K) 32x 32-way SM S S N nst. Mem. 4K AGU pipeline 12bit 16-bit 16 entries 2 read/ 1 write port Scalar pipeline Vector to Scalar Stage 1 Scalar Memory (4K) AGU Vector to Scalar Stage 2 Scalar to Vector 16- bit 512bit MA 16-bit 40-bit ACC Scalar US AGU 17

18 SOA P SM Pipeline P SM pipeline SM Memory (8K) 32x 32-way SM S S N nst. Mem. 4K Scalar pipeline AGU pipeline 12bit Vector to Scalar Stage 1 Vector to Scalar Stage 2 Scalar to Vector SM: Scalar Memory (4K) - 32 AGU wide - predicated exec. - predicated neg. 18 MA Scalar 512bit Memory: US - 512bit AGU port - 1 read port - 1 write port - 8 Kytes

19 SOA P SM Shuffle Network P SM pipeline SM Memory (8K) 32x 32-way SM S S N nst. Mem. 4K Scalar pipeline AGU pipeline 12bit Vector to Scalar Stage 1 Scalar Memory (4K) AGU Vector to Scalar Stage 2 Scalar to Vector 512bit MA Scalar nverse Shuffle SM xchange terative Shuffle xchange Feedback Only xchange Network () (S) (S) US AGU 19

20 Floorplan 20

21 SOA P Scalar Pipeline P 32-way SM SM pipeline S S N SM Memory (8K) 32x Scalar: - One 16-bit datapath - No mult unit Scalar memory: - port - 1 read/write port - 4 Kytes Scalar-to-Vector Vector-to-Scalar nst. Mem. 4K Scalar pipeline AGU pipeline 12bit Vector to Scalar Stage 1 Scalar Memory (4K) AGU Vector to Scalar Stage 2 Scalar to Vector 512bit MA Scalar US AGU 21

22 -CMA Mapping On SOA -CMA Physical Layer Processing Frontend / A A / LPF-Tx scrambler spreader nterleaver searcher LPF-x descrambler despreader. descrambler despreader combiner Transmitter Channel encoder eceiver Channel deinteleaver decoder (turbo/viterbi) Upper layers AM P P P P Global Memory espreader einterleaver Combiner PN Code uffer T/ (1K ytes) uffer uffer (2K ytes) (1K ytes) 2 LPF-x Misc. Turbo Searcher Control ecoder uffer uffer (1K ytes) (10 ytes) e- Power scrambler Control uffer (1K ytes) Turbo ncoder nterleaver Spreader Scrambler 4 LPF-x FFO Queue (12.5 Kytes) uffer (20 Kytes) uffer (20 Kytes) CMA eceiver CMA Transmitter 22

23 S Performance istribution Computations (Mcycles) filter modulation channel estimation error correction -CMA (2Mbps) a (24Mbps) a has higher number of total computational cycles -CMA requires higher computational cycles per bit 23

24 Power Consumption at 180nm 1400 Power (m) in 180nm P ata Memory P SM P SM s P SM Pipeline P Others Global Memory System Others -CMA (2Mbps) a (24Mbps) ide SM requires higher number of pipeline registers a consumes higher power than -CMA 8-bit -CMA computation versus 16-bit a computation 24

25 Summary of Prototype Hardware S Hardware equirements Comp. requirements: 10 ~ 100 GOPS Sub-watt power budget: ~ 0.2 att for cellular phones SOA esults -CMA & a: 1.3 ~ 2 GOPS (with SOA L ops) 180nm: ~ 3 atts (area: 26.6mm 2 ) 90nm (est.): ~ 0.5 att (6.7 mm 2 ) Key features of SOA Multi-P with scratchpad memories Low throughput shared bus 2-issue L: SM+(Scalar or AGU) 32-wide SM processing SM shuffle network 25

26 Further Power Saving Opportunities Terminal operation modes dle mode >95% of the operation time active mode idle mode active mode voice call web browsing t awake period 50msec x sleep period 1~4 sec x t 26

27 Generalized Operation Flow pulse shaping synchronization channel quality measurement pulse shaping channel estimation demodulation cell selection channel decoding 27

28 Computation Patterns x[n] Z - 1 Z - 1 Z - 1 c 0 c 1... c L- 1 y[n] 28

29 SOA P Architecture P SM pipeline SM Memory (8K) 32x Move the SSN out of the critical path Voltage scaling longer compute times 10s of n possible 32-way SM S S N nst. Mem. 4K Scalar pipeline AGU pipeline 12bit Vector to Scalar Stage 1 Scalar Memory (4K) AGU Vector to Scalar Stage 2 Scalar to Vector 512bit MA Scalar US AGU 29

30 SOA Programming Model Hardware Multi-P organization Software managed memory ide SM arithmetic units Software/SP Algorithms eal-time computation Concurrent algorithm executions Vector computations 30

31 -CMA Mapping On SOA -CMA Physical Layer Processing Frontend / A A / LPF-Tx scrambler spreader nterleaver searcher LPF-x descrambler despreader. descrambler despreader combiner Transmitter Channel encoder eceiver Channel deinteleaver decoder (turbo/viterbi) Upper layers AM P P P P Global Memory espreader einterleaver Combiner PN Code uffer T/ (1K ytes) uffer uffer (2K ytes) (1K ytes) 2 LPF-x Misc. Turbo Searcher Control ecoder uffer uffer (1K ytes) (10 ytes) e- Power scrambler Control uffer (1K ytes) Turbo ncoder nterleaver Spreader Scrambler 4 LPF-x FFO Queue (12.5 Kytes) uffer (20 Kytes) uffer (20 Kytes) CMA eceiver CMA Transmitter 31

32 SP: Programming Language Two-tier model Protocol system level description Concurrent kernel objects Communication through channels Algorithm kernel level description First-class vector objects and operations Flexible data permutation patterns 32

33 System-level Compilation Control/data separation Control processor: AM ata engines: Ps Control processor Non-preemptive kernel scheduling MA scheduling ata engines Kernel executions 33

34 System-level Compilation Static kernel-to-p assignment Channel variables MA operations for inter-p communications Memory copies for intra-p communications eal-time kernel scheduling by control processor Kernel executions Non-preemptive Software managed kernel contexts 34

35 Kernel-level Compilation Transforming vector computation into SM operations Mapping data movements with SM permutation operations Scheduling AGU operations for memory access 35

36 Prototype completed in August ehavioral synthesis Language by ecember eferences Future ork H. Lee, Y. Lin, Y. Harel, M. oh, S. Mahlke, T. Mudge, K. Flautner. Software defined radio - A high performance embedded challenge. Proc. 1st nt. Conf. High Performance mbedded Architectures and Compilers (HiPAC'05), arcelona, Spain, Nov ds. T. Conte, N. Navarro,.. Hwu, M. Valero, T. Ungerer. Lecture Notes in Computer Science, Springer-Verlag GmbH, vol / 2005, pp H. Lee, T. Mudge. A dual processor solution for the MAC layer of a software defined radio terminal. Proc. Conf. Compiler and Architecture Support for mbedded Systems (CASS'05), Sep. 2005, CA, pp Y. Lin, H. Lee, Y. Harel, M. oh, N. aron, S. Mahlke, T. Mudge, K. Flautner. A system solution for highperformance, low-power S. Proc S Technical Conf., Annaheim, CA, Nov. 2005, 6 pp. Y. Lin, H. Lee, M. oh, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti, K Flautner. SOA: A low-power architecture for software radio. Proc. 33rd Ann. nt. Symp. on Computer Architecture, oston, MA USA, June H. Lee, C. Chakrabarti, T. Mudge. educing idle mode power in software defined radio terminals. Proc. nt. Symp. Low Power lectronic esign (SLP), to appear. 36

37 Questions? 37

38 ackup Slides 38

39 ifferent Levels of Software adio Tier Tier 0 Tier 1 Tier 2 Tier 3 Tier 4 Name Hardware adio (H) Software Controlled adio (SC) Software efined adio (S) deal Software adio (S) Ultimate Software adio (US) escription mplemented using hardware components. Cannot be modified Only control functions are implemented in software: inter-connects, power levels, etc. Software control of a variety of modulation techniques, wide-band or narrow-band operation, security functions, etc. Programmability extends to the entire system with analog conversion only at the antenna. efined for comparison purposes only <source: 39

40 Power Methodology Our flow sequence was esign Compiler and Silicon nsemble For nitial Floorplan stimation Physical Compiler For placement and Optimization Silicon nsemble outing e optimized for power and delay locks like memory were generated with Artisan Memory Generators e used the Synopsys P locks as much as possible to get better compiled blocks 40

41 Time 1 -CMA frame (15 slots), 10 msec Power Control eal-time Critical Path (0.67 msec) Searcher eal-time Critical Path (5 msec) PN Code <0.1 msec Power Control <0.1 msec einterleaver 0.2 msec A M P P N C P N P P N C P P N C P N P C P P N C P N P C P P N C P P N C P N P C P P N C P N P C P P N C P P N C P N P C P 1 F M O F M O F M O F M O F M O F M O F M O F M O F M O F M O F M O F M O F M O F M O P 2 Searcher 5 msec F(x) 0.3 msec emodulation 0.1 msec P 3 Turbo ecoder 10 msec P 4 N C Modulation F Turbo ncoder 0.2 msec nterleaver 0.2 msec Modulation 1 msec F(Tx) 8 msec nput from A/ AM: PN/Power Ctrl. P1 F/Mod. P2 Searcher P3 Turbo P4 T P N SYNC P1, AM F SYNC P1, P2, AM P N M F P N 1 slot 0.67 msec SYNC P1, AM M F P N SYNC P1, AM M Searcher F P N SYNC P1, AM M SYNC P1, AM P C 41