Design Considerations for VRM Transient Response Based on the Output Impedance *

Transcription

1 Design nsideratins fr VRM Transient Respnse Based n the Output Impedane * Kaiwei Ya, Yu Meng, Peng Xu and Fred. ee enter fr Pwer Eletrnis Systems The Bradley Department f Eletrial and mputer Engineering Virginia Plytehni Institute and State University Blaksburg, VA 246 USA Abstrat This paper disusses the transient respnse f vltage regulatr mdules (VRMs) based n the small-signal mdels. The nept f nstant resistive utput impedane design fr the VRM is prpsed, and its limitatin in appliatin is analyzed. The impat f the utput filter and the feedbak ntrl bandwidth shws that there is an ptimum design fr the VRM t ahieve fast transient respnse, small size and gd effiieny. Simulatins and experimental results prve the theretial analysis. I. INTRODUTION As the lk speed f mirpressrs is develped t be faster than GHz, a lwer peratin vltage is better fr data pressing effiieny. urrently, the supply vltage level is abut.5v, and it will derease further in the future. Fr suh a lw value, the allwable differene between the maximum and minimum vltage is very small. Fr example, a Pentium IV nly allws a tlerane f abut 3mV[]. nversely, the mirpressr is mre pwer-hungry beause f the high-density semindutr integratin. The supply urrent is already mre than 5A fr a Pentium IV, and it will be even larger fr the next generatin f mirpressrs. The large supply urrent nt nly pses a stringent hallenge n effiieny, but als adds a heavy burden n the transient respnse. One reasn is the large urrent step; anther ne is the very fast urrent slew rate (5A/us nw, and muh higher in the future). Simply put, as a speial pwer supply fr the mirpressr, the vltage regulatr mdule (VRM) must maintain a lw utput vltage within a tight tlerane range during the large urrent step transient with high slew rate. T meet suh transient requirements, many apaitrs are used in the VRM utput, whih inreases the size and st. Originally, the feedbak ntrl keeps the VRM utput vltage at the same level fr the entire lad range. As a result, the utput vltage spike during the transient must be smaller than half f the vltage tlerane windw. If the utput vltage level is a little higher than the minimum value at full lad and a little lwer than the maximum value at light lad, the whle vltage tlerane range an be used fr the vltage jump r drp during the transient. This is the nept f adaptive vltage psitin (AVP) design [2~3]. Fig. shws * This wrk was supprted by Intel, Texas Instruments, Natinal Semindutrs, Intersil, TDK, Hitahi, Hipr, Pwer-One and Delta Eletrnis. Als, this wrk made use f ER shared failities supprted by the Natinal Siene Fundatin under Award Number EE the transient mparisn between nn-avp and AVP designs. It is very lear that the AVP design allws the use f fewer utput apaitrs, and hene redues the VRM st. Anther benefit f the AVP design is that the VRM utput pwer at full lad is redued, whih greatly failitates the thermal design. V min V min W/O AVP W/ AVP i O.5*( -V min ) -V min Fig.. Transient withut and with AVP designs. The AVP is related t the steady-state peratin f the VRM. If the transients between the tw steady-state stages have n spikes and n sillatins, whih situatin is shwn in Fig. 2, the AVP design is ptimal. The transient an take advantage f the whle vltage tlerane windw. The mparisn between the urrent and the related utput vltage wavefrms (Fig. 2) reveals that the VRM equals an ideal vltage sure in series with a resistr R O.Fig.3shws the equivalent iruit fr the VRM. V min i O V O Fig. 2. The ideal AVP design fr the transient. I O V O Nw it is very lear that the nstant resistive utput impedane design fr the VRM is an ptimum design fr the transient. Atually, imprving the dynami regulatin f a nverter based n the utput impedane nsideratin is an ld nept [4~7]. Hwever, nt every nverter an ahieve nstant resistive utput impedane. Additinally, it is nt lear hw t design the feedbak ntrl lp. This paper /2/$7. () 2 IEEE

2 larifies these issues. Setin II prpses a simple methd t realize the nstant utput impedane. Bth the vltage and urrent mde ntrls are disussed. Setin III investigates the limitatin f the nstant utput impedane design based n the small-signal analysis methd. Finally, Setin IV shws an example f ptimal design. R O = V O / I O VRM i O + V O - PU the parasiti resistane f the traes. The is the equivalent series resistane (ESR) f the utput apaitr. The is the pwer stage duble ple and the T(s) is the lsed-lp gain. Fig. 5 shws the pen-lp utput impedane. At high frequenies, determines the utput impedane. N matter hw the lsed-lp gain T(s) is designed, has the same value as beynd the bandwidth. Feedbak ntrl an nly attenuate the utput impedane in the lw-frequeny range. As a result, the is the nly value that is able t ahieve the nstant utput impedane. 4 R Fig. 3. The equivalent iruit f the VRM fr the ideal AVP design. II. ONSTANT OUTPUT IMPEDANE DESIGN urrently, the multi-phase synhrnus buk nverter is widely used fr VRMs. The small-signal mdel an be simplified as a single-phase buk nverter in ntinuusurrent mde [8]. As a result, a simple buk nverter, shwn in Fig. 4, is used t analyze the utput impedane with pen lp and with lsed lp. The equivalent series indutr (ES) f the utput apaitr is ignred here sine the highfrequeny erami apaitrs in parallel greatly redue its effet. V in Q T Gate Driver d F m Q B - G n + V V ref R Fig. 4. Output impedane analysis using a buk nverter. Based n the small-signal analysis methd [9~], it is easy t derive the pen-lp utput impedane and the lsed-lp utput impedane : ( + s / ) ( + s / ) = R () 2 2 s /( Q ) + s / =, (2) T =, =, ESR R, / Q. (3) R + Here, R inludes the D resistane f the indutr, the ndutin resistane R ds-n f the MOSFETs Q T and Q B,and Fig. 5. The utput impedane with pen and lsed lps.. The design methd is simple. First, the lsed-lp utput impedane is derived: it is a funtin f the mpensatr transfer funtin G n (s). Then, G n (s) an be derived by slving the equatin =. Finally, the mpensatr an be designed t be as lse as pssible t the ideal transfer funtin G n (s). Thus, sme simple mpensatr designs an ahieve apprximately nstant resistive utput impedane. Bth the vltage mde and peak urrent mde ntrls are disussed in the fllwing setin. A. Vltage Mde ntrl Fr vltage mde ntrl, the lsed-lp utput impedane is: = =, (4) T Fm Gvd Gn where F m is the mparatr gain and G vd (s) is the transfer funtin f the utput vltage V t the duty yle d. Fig. 6 shws the ideal mpensatr transfer funtin t ahieve =. Sine the small-signal mdel is n lnger effetive beynd the half swithing frequeny, the real mpensatr design nly needs t be aurate fr the lwfrequeny range. A single ple and zer mpensatr an satisfy this requirement. s / zv Gn = K (5) V s / pv Further mathemati analysis shws the detailed values f the D gain, ple and zer. R ESR K v = (6) ESR Vin Fm = (7) pv /2/$7. () 2 IEEE

3 2 b b 4 a zv = (8) 2 a R ESR a = 2 b = R ( ESR + ) Q = R (9) f (Hz) mpensatr Gain zv pv mpensatr Phase Fig. 7 shws the lsed-lp utput impedane using this mpensatr design. It is almst nstant. Simulatin results in Fig. 8 shw the nearly perfet transient respnse with AVP ntrl. B. urrent Mde ntrl Fr urrent mde ntrl, the analysis is slightly mre mpliated. Fig. 9 shws the dual-lp feedbak ntrl system. The peak urrent mde ntrl is used as an example fr this analysis. Sine the urrent lp design is nrmally fixed arding t the applied ntrl hip, the majr issue is hw t design the vltage lp mpensatr. V in Q T Gate Driver d F m T i R S Q B R i i T v - G n + V R K V ref f (Hz) Fig. 6. mpensatr design fr vltage mde ntrl. 3 db Fig. 7. The utput impedane with vltage mde ntrl. 25A di/dt=5a/us Fig. 8. Simulatin results with vltage mde ntrl. Fig. 9. A buk nverter using urrent mde ntrl. With the urrent lp lsed, the utput impedane with the pen vltage lp is: Ti Gvd Gii i = +, () Ti Gid where T i (s) is the urrent lp gain, G ii (s) is the indutr urrent t the lad urrent transfer funtin, and G id (s) is the indutr urrent t the duty yle transfer funtin. The utput impedane with the bth lps lsed is: i ( + Ti ) i = =, () T2 Ti + Fm Gvd Gn where T 2 (s) is the uter lp gain, whih determines the system bandwidth and phase margin. Fig. shws the ideal mpensatr transfer funtin t ahieve =. As is the ase fr vltage mde ntrl, a real mpensatr with ne ple and ne zer is gd enugh t me lse t the ideal design. s / zi Gn( s) = K (2) i + s / pi Further mathemati analysis shws the detailed values f the D gain, ple and zer as fllws: Ri K i, (3) ESR =, and (4) pi zi =, (5) π f s /2/$7. () 2 IEEE

4 where R i is the urrent sensing gain and f s is the swithing frequeny. There is mre physial meaning fr the mpensatr design than was the ase fr vltage mde ntrl. A ple mpensates the utput apaitr ESR zer, and a zer mpensates the duble right half plane zer intrdued by the urrent sample and hld effet. Fig. shws the lsed-lp utput impedane with this mpensatr design. It is almst nstant. Simulatin results in Fig. 2 shw the nearlyt perfet transient respnse with AVP ntrl mpensatr Gain mpensatr Phase pi zi Fig.. mpensatr design fr urrent mde ntrl i Fig.. The utput impedane with urrent mde ntrl. I V I V III. IMITATION OF THEONSTANTOUTPUT IMPEDANE DESIGN Based n the previus analysis, it seems that a VRM with any r values an ahieve nstant utput impedane, but this is nt true. Fr vltage mde ntrl, if R <,whih is pssible fr VRM design, the D gain will be negative, arding t Equatin. 6. This is impssible fr a real design. Even with R >, the D gain is t lw t attenuate the swithing nise. Als, it is nt easy t ahieve urrent sharing between multi-hannels with vltage mde ntrl. The urrent mde ntrl is different. The lsed urrent lp makes the nverter perate like a urrent sure, whih has very high utput impedane at lw frequeny. The i in Fig. shws this learly. As a result, the uter lp T 2 needs a high D gain t attenuate the utput impedane at lw frequeny. Hwever, there is a speial requirement fr the bandwidth in rder t ahieve the nstant utput impedane. Mathematial analysis shws that the bandwidth is just n the ESR zer f the utput apaitr, as fllws: f =. (6) 2 π ESR This is easy t understand, sine the pen-lp utput impedane i (vltage lp pen, but urrent lp lsed) has a zer just n that pint. Fig. 3 shws the relatinship learly. The ESR zers f different kinds f utput apaitrs are als different. Fig. 3 shws that if the bandwidth is t near t half f the swithing frequeny, the system will nt have suffiient phase margins and will beme unstable. As a result, if the ESR zer is t high, it is impssible t realize nstant utput impedane Gain Phase i T 2 T 2 f 2 π.5 f s Fig. 2. Simulatin results with urrent mde ntrl. Fig. 3. The required uter lp gain /2/$7. () 2 IEEE

5 Table I lists the ESR zers f three majr kinds f utput apaitrs fr the VRM appliatin. Fr the Osn apaitr, there is n diffiulty in ahieving 6KHz rssver frequeny with ~3KHz swithing frequeny. The ESRE is a speial kind f eletrial film apaitr prdued by rnell Dubilier; its size is muh smaller than that f the Osn. Hwever, a higher swithing frequeny is required t ahieve the 4KHz bandwidth. Fr the erami apaitr, it is impssible t ahieve nstant utput impedane with the state-f-the-art tehnlgy. TABE I. ESR ERO FOR DIFFERENT KINDS OF APAITORS. ap Type apaitane ESR ESR er Osn (SanY) 8µF 2mΩ 6KHz ESRE (DE) 27µF 5mΩ 4KHz erami (TDK) µf.4mω.mhz The preeding analysis is based n the small-signal mdel. If the duty yle is saturated, the lsed-lp utput impedane an n lnger be used fr transient analysis. Instead, the pen-lp utput impedane is effetive in the transient. Sine the pen-lp utput impedane is muh larger than that f the lsed-lp, the transient respnse f the frmer will be wrse. T guarantee a gd transient vltage wavefrm, the duty yle shuld nt beme saturated. The ritial indutane nept [8,2] reveals the pint at whih the duty yle will g t saturatin in a vltage mde ntrlled VRM. The rssver frequeny determines the ritial indutane value, abve whih the duty yle will g t saturatin. V = in v min( D, D) (7) 4 I f In the same way, a ritial indutane value an be als derived fr the urrent mde ntrl. Fig. 4 shws the urrent transfer funtin G ii (s), and Fig. 5 shws the step respnse indutr urrent with peak urrent mde ntrl. The indutr urrent with lsed lp respnds t the step lad urrent hange as a first-rder system, in whih the time nstant is simply the bandwidth. The average indutr urrent during transient is Apprximately: t 2 π f i ( t) = I ( e ), (8) where f is the rssver frequeny. The indutr urrent slew rate with average small-signal mdel is: t 2 π f Si ( t) = I 2 π f e. (9) Hwever, the maximum indutr urrent slew rate annt exeed the Faraday aw limitatin, in whih di/dt=v / fr step dwn and di/dt=(v in -V )/ fr step up. arger value frm Equatin (9) means the duty yle is saturated and the small-signal mdel is n lnger effetive. The equivalent pints give the ritial indutane value: Vin i = min( D, D). () 2 π I f 4 4 Outer-p Gain f = 2 π f Open-p = 2 π lsed-p Fig. 4. The indutr urrent transfer-funtin f urrent mde ntrl S max / = ts ( ) i Fig. 5. The step-respnse f the indutr urrent. As a result, in rder t avid duty yle saturatin, the utput filter indutr shuld nt be designed with a higher value than the ritial indutane. Sine a larger indutane value an imprve effiieny by reduing the urrent ripple, the ritial indutane value is a gd design pint fr bth transient and effiieny nsideratins. IV. A DESIGN EXAMPE Based n the understanding f the nstant utput impedane design and its related limitatins, an ptimum design fr ertain utput apaitrs an be ahieved, whih simultaneusly nsiders VRM size, transient and effiieny. A design press is shwn here fr a 2V t.6v/25a VRM using the Osn apaitr shwn in Table I. The required vltage tlerane is mv. With the nstant utput impedane design, the ESR f the utput apaitr limits the transient vltage spike. In rder t meet the mv vltage transient vltage spike requirement with 25A lad urrent transient, the ESR f the utput apaitrs shuld be less than 4mΩ. As a result, fur apaitrs shuld be used in parallel. A mmerial peak urrent ntrller (SI65) fr twphase interleaving is seleted fr the VRM design. It an ahieve urrent-sharing autmatially, and the mpensatr an be designed arding t the disussin in Setin II t ahieve nstant utput impedane. The uter-lp bandwidth is at exatly 6KHz, whih is the ESR zer f the Osn apaitr /2/$7. () 2 IEEE

6 Then, the utput filter indutane an be determined based n the ritial indutane value. 5nH is seleted arding t Equatin s that eah hannel indutane is µh. This indutane value an guarantee that the duty yle will nt beme saturated during the transient. Finally, the swithing frequeny is seleted arding the bandwidth and the indutr urrent ripple. Here, a 25KHz swithing frequeny is seleted, whih easily ahieves 6KHz rssver frequeny with a stable system and is gd enugh t limit the indutr urrent ripple t 2% f the indutr D urrent. Als, the swithing frequeny is nt s high that the swithing lss is relatively small. Tw MOSFETs with SO-8 pakages are used in eah hannel, ne fr the tp swith Q T and anther fr the bttm swith Q B. Si4842 is seleted fr Q T beause f its lw gate harge, and Si4442 is seleted fr Q B beause f its lw R ds_n. The gate driver M2726 is seleted fr its fast driving apability and very small dead time. Vishay s surfaemunted indutr IHP-55E is used fr its small size and lw prfile. Fig. 6 shws the tested transient respnse wavefrm with the nstant utput impedane design. Perfet AVP is ahieved. Fig. 7 shws the extended transient wavefrms during the step-up and step-dwn perids. The duty yle is nt saturated during the transient with the ritial indutane design. The tested uter-lp bandwidth in Fig. 8 shws that the rssver frequeny is just n the ESR zer f the utput apaitr. Fig. 9 shws the high effiieny ahieved by using nly fur SO-8 MOSFETs based n the ptimum design press. VI. ONUSION This paper disusses the nstant utput impedane design methd utilized t ahieve perfet AVP fr the VRM transient respnse. Bth the vltage mde and urrent mde ntrls an ahieve the nstant utput impedane. The limitatin f vltage mde ntrl is disussed. Fr urrent mde ntrl, the bandwidth is just n the ESR zer f the utput apaitr, suh that the utput apaitr determines the feasibility f the nstant utput impedane design methd. Als, the limitatin f the small-signal mdel shws the design guideline fr the utput filter indutane. Finally, an ptimum design press is prpsed, and a design example is given that ahieves small size, high effiieny and gd transient respnse. Simulatin and experimental results prve that the nstant utput impedane design is a gd design methd. AKNOWEDGMENTS The authrs wuld like t thank Silinix and Vishay fr supplying free devie samples. A I V Fig. 6. Experimental results fr the transient. I V (a) (b) D I V D Fig. 7. Extended transient wavefrms: (a) step-dwn and (b) step-dwn /2/$7. () 2 IEEE

7 Effiieny Outer-p Gain f=6.6khz Phase Fig. 8. The tested uter-lp gain and phase. 85% ad urrent (A) Fig. 9. The tested effiieny. REFERENES [] Intel dument, VRM 9. D-D nverter design guidelines, Order number: , April. [2] M. hang, Pwering Intel Pentium 4 pressrs, Intel Tehnlgy Sympsium,. [3] A.Waizman and.y. hung, "Resnant free pwer netwrk design using extended adaptive vltage psitining (EAVP) methdlgy," IEEE Trans. Advaned Pakaging,vl.24,pp , Aug.. [4] R. Redl and N. O. Skal, Near-ptimum dynami regulatin f D-D nverters using feed-frward f utput urrent and input vltage with urrent-mde ntrl, IEEE Trans. Pwer Eletrn., vl., pp. 8 92, July 986. [5] G. K. Shneman and D. M. Mithell, Output impedane nsideratins fr swithing regulatrs with urrent-injeted ntrl, in Pr. IEEE PES, 987, pp [6].D. Varga and N.A. si, Synthesis f zer-impedane nverter, IEEE Trans. Pwer Eletrn.,vl.7,pp.52 7, Jan [7] R. Redl, B.P. Erisman and. ansky, Optimizing the lad transient respnse f the buk nverter, in Pr. IEEE APE, 998, pp [8] P.. Wng, Perfrmane imprvements f multi-hannel interleaving vltage regulatr mdules with integrated upling indutrs, Dissertatin f Virginia Plytehni Institute and State University, Marh. [9] R. Tymerski, V. Vrperian, F.. ee and W.T. Baumann, Nnlinear mdeling f the PWM swith, IEEE Trans. Pwer Eletrn., vl. 4, pp , April 989. [] R.B. Ridley, B.H. h and F.. ee, Analysis and interpretatin f lp gains f multilp-ntrlled swithing regulatrs, IEEE Trans. Pwer Eletrn., vl. 3, pp , Ot [] R.B. Ridley, A new ntinuus-time mdel fr urrent-mde ntrl, IEEE Trans. Pwer Eletrn.,vl.6,pp.27 28, April 99. [2] P.. Wng, F.. ee, P. Xu and K. Ya, ritial indutane in vltage regulatr mdules, in Pr. IEEE APE, /2/$7. () 2 IEEE