Efficient Circuit Analysis

Transcription

1 Efficient Circuit Analysis Chris Myers, Nathan Barker, Kevin Jones, Hiroyuki Kuwahara, Scott Little, Curtis Madsen, Nam Nguyen, Robert Thacker, David Walter University of Utah CE Junior Seminar September 5, 2006 C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

2 What do these have in common? C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

3 What do these have in common? All can be analyzed by tools developed in my research group. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

4 Timed Circuit Analysis For 15 years, our research group has been developing design methods and tools for timed circuits. To support the synthesis of these circuits, we have developed efficient timing analysis tools. Our tools have been used to analyze: Intel s RAPPID circuit, a highly optimized timed asynchronous circuit. IBM s guts processer, a highly optimized timed synchronous circuit. Research resulted in numerous publications, patents, 7 MS degrees, and 7 PhDs degrees (4 now in academia). Also, published a textbook used in ECE/CS 5750/6750. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

5 Analog/Mixed-Signal Circuit Analysis 75% of all chips include analog and mixed-signal (AMS) circuits. While AMS circuits only make up 2% of the devices and 20% of the area, they are taking 40% of the design effort. About 50% of errors requiring redesign due to errors in the AMS portion. Therefore, improvements in AMS circuit validation methodology are becoming increasingly important. 0 Data on this slide is from IBS Corp s industry reports (2003). C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

6 Formal Verification of AMS Circuits Validation today uses SPICE-level simulations with parameters varied to reflect minimum, typical, and maximum values. All permutations of these corner simulations are run for major parameters resulting in a long simulation time. While these simulations analyze global variation, they fail to account for local transistor-to-transistor mismatch. This can be evaluated using Monte Carlo simulations in which threshold voltage of each transistor is assigned a random value. This method results in extremely long simulation time and is unlikely to find the worst-case mismatch scenario. Formal verification uses non-determinism and state exploration to validate designs over a range of parameters and initial conditions. It is a promising mechanism to validate AMS circuits in the face of noise and uncertain parameters. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

7 Motivating Example: Nuclear Reactor Controller ADC Input 1 LPF AMP Temp. Sensor 1 Micro Controller HC11 ADC Input 2 PB2 PB1 PB0 LPF Shutdown Rod2 Rod1 AMP Temp. Sensor 2 C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

8 VHDL-AMS and LHPN for Changing Rates if rod1 = 0 use if rod2 = 0 use t dot == 32.0; else t dot == -10.0; end use; else if rod2 = 0 use t dot == -25.0; else t dot == 0.0; end use; end use; {rod1 rod2} t := 25 {rod1 rod2} t := 32 {rod1 rod2} t := 0 p0 {rod1 rod2} t := 10 C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

9 VHDL-AMS and LHPN for Changing Rates if rod1 = 0 use if rod2 = 0 use t dot == 32.0; else t dot == -10.0; end use; else if rod2 = 0 use t dot == -25.0; else t dot == 0.0; end use; end use; {rod1 rod2} t := 25 {rod1 rod2} t := 32 {rod1 rod2} t := 0 p0 {rod1 rod2} t := 10 C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

10 VHDL-AMS and LHPN for Changing Rates if rod1 = 0 use if rod2 = 0 use t dot == 32.0; else t dot == -10.0; end use; else if rod2 = 0 use t dot == -25.0; else t dot == 0.0; end use; end use; {rod1 rod2} t := 25 {rod1 rod2} t := 32 {rod1 rod2} t := 0 p0 {rod1 rod2} t := 10 C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

11 VHDL-AMS and LHPN for Changing Rates if rod1 = 0 use if rod2 = 0 use t dot == 32.0; else t dot == -10.0; end use; else if rod2 = 0 use t dot == -25.0; else t dot == 0.0; end use; end use; {rod1 rod2} t := 25 {rod1 rod2} t := 32 {rod1 rod2} t := 0 p0 {rod1 rod2} t := 10 C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

12 VHDL-AMS and LHPN for Changing Rates if rod1 = 0 use if rod2 = 0 use t dot == 32.0; else t dot == -10.0; end use; else if rod2 = 0 use t dot == -25.0; else t dot == 0.0; end use; end use; {rod1 rod2} t := 25 {rod1 rod2} t := 32 {rod1 rod2} t := 0 p0 {rod1 rod2} t := 10 C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

13 Reactor Software unsigned char t1, t2, c1=80, c2=80; int main() { OPTION = 0x80; TMSK1 = 0x80; TFLG1 = 0x80; TOC1 = TCNT + 30; while (1) { if ((t1-t2 > 1) (t1-t2 < -1)) PORTB = 7; if (t1 > 220) { if (c1 >= 80) { PORTB = 1; while (t1 > 50); { PORTB = 0; c1=0; } else if (c2 >= 80) { PORTB = 2; while (t1 > 50); { PORTB = 0; c2=0; } else PORTB = 7; } } } C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

14 Reactor Software unsigned char t1, t2, c1=80, c2=80; int main() { OPTION = 0x80; TMSK1 = 0x80; TFLG1 = 0x80; TOC1 = TCNT + 30; while (1) { if ((t1-t2 > 1) (t1-t2 < -1)) PORTB = 7; if (t1 > 220) { if (c1 >= 80) { PORTB = 1; while (t1 > 50); { PORTB = 0; c1=0; } else if (c2 >= 80) { PORTB = 2; while (t1 > 50); { PORTB = 0; c2=0; } else PORTB = 7; } } } C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

15 Reactor Software unsigned char t1, t2, c1=80, c2=80; int main() { OPTION = 0x80; TMSK1 = 0x80; TFLG1 = 0x80; TOC1 = TCNT + 30; while (1) { if ((t1-t2 > 1) (t1-t2 < -1)) PORTB = 7; if (t1 > 220) { if (c1 >= 80) { PORTB = 1; while (t1 > 50); { PORTB = 0; c1=0; } else if (c2 >= 80) { PORTB = 2; while (t1 > 50); { PORTB = 0; c2=0; } else PORTB = 7; } } } C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

16 Reactor Software unsigned char t1, t2, c1=80, c2=80; int main() { OPTION = 0x80; TMSK1 = 0x80; TFLG1 = 0x80; TOC1 = TCNT + 30; while (1) { if ((t1-t2 > 1) (t1-t2 < -1)) PORTB = 7; if (t1 > 220) { if (c1 >= 80) { PORTB = 1; while (t1 > 50); { PORTB = 0; c1=0; } else if (c2 >= 80) { PORTB = 2; while (t1 > 50); { PORTB = 0; c2=0; } else PORTB = 7; } } } C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

17 Reactor Software unsigned char t1, t2, c1=80, c2=80; int main() { OPTION = 0x80; TMSK1 = 0x80; TFLG1 = 0x80; TOC1 = TCNT + 30; while (1) { if ((t1-t2 > 1) (t1-t2 < -1)) PORTB = 7; if (t1 > 220) { if (c1 >= 80) { PORTB = 1; while (t1 > 50); { PORTB = 0; c1=0; } else if (c2 >= 80) { PORTB = 2; while (t1 > 50); { PORTB = 0; c2=0; } else PORTB = 7; } } } C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

18 Reactor Software unsigned char t1, t2, c1=80, c2=80; int main() { OPTION = 0x80; TMSK1 = 0x80; TFLG1 = 0x80; TOC1 = TCNT + 30; while (1) { if ((t1-t2 > 1) (t1-t2 < -1)) PORTB = 7; if (t1 > 220) { if (c1 >= 80) { PORTB = 1; while (t1 > 50); { PORTB = 0; c1=0; } else if (c2 >= 80) { PORTB = 2; while (t1 > 50); { PORTB = 0; c2=0; } else PORTB = 7; } } } C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

19 Reactor Software unsigned char t1, t2, c1=80, c2=80; int main() { OPTION = 0x80; TMSK1 = 0x80; TFLG1 = 0x80; TOC1 = TCNT + 30; while (1) { if ((t1-t2 > 1) (t1-t2 < -1)) PORTB = 7; if (t1 > 220) { if (c1 >= 80) { PORTB = 1; while (t1 > 50); { PORTB = 0; c1=0; } else if (c2 >= 80) { PORTB = 2; while (t1 > 50); { PORTB = 0; c2=0; } else PORTB = 7; } } } C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

20 Periodic Interrupt Routine #pragma interrupt_handler TOC1handler() void TOC1handler() { TFLG1 = 0x80; TOC1 = TOC ; ADCTL = 0x10; while ((ADCTL & 0x80) == 0); t1 = ADR1; t2 = ADR2; if (c1 < 80) c1++; if (c2 < 80) c2++; } C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

21 Periodic Interrupt Routine #pragma interrupt_handler TOC1handler() void TOC1handler() { TFLG1 = 0x80; TOC1 = TOC ; ADCTL = 0x10; while ((ADCTL & 0x80) == 0); t1 = ADR1; t2 = ADR2; if (c1 < 80) c1++; if (c2 < 80) c2++; } C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

22 Periodic Interrupt Routine #pragma interrupt_handler TOC1handler() void TOC1handler() { TFLG1 = 0x80; TOC1 = TOC ; ADCTL = 0x10; while ((ADCTL & 0x80) == 0); t1 = ADR1; t2 = ADR2; if (c1 < 80) c1++; if (c2 < 80) c2++; } C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

23 Periodic Interrupt Routine #pragma interrupt_handler TOC1handler() void TOC1handler() { TFLG1 = 0x80; TOC1 = TOC ; ADCTL = 0x10; while ((ADCTL & 0x80) == 0); t1 = ADR1; t2 = ADR2; if (c1 < 80) c1++; if (c2 < 80) c2++; } C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

24 Verification at Assembly Level unsigned char t1, t2; int main() { while (1) { if ((t1-t2 > 1) (t1-t2 < -1)) PORTB = 7;... } } loop: skip:. ldab t1 subb t2 clra aba adda #1 cmpa #2 bls skip ldaa #7 staa $ bra loop C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

25 Verification at Assembly Level unsigned char t1, t2; int main() { while (1) { if ((t1-t2 > 1) (t1-t2 < -1)) PORTB = 7;... } } loop: skip:. ldab t1 subb t2 clra aba adda #1 cmpa #2 bls skip ldaa #7 staa $ bra loop C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

26 Verification at Assembly Level unsigned char t1, t2; int main() { while (1) { if ((t1-t2 > 1) (t1-t2 < -1)) PORTB = 7;... } } loop: skip:. ldab t1 subb t2 clra aba adda #1 cmpa #2 bls skip ldaa #7 staa $ bra loop C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

27 Verification at Assembly Level unsigned volatile char t1, t2; int main() { while (1) { if ((t1-t2 > 1) (t1-t2 < -1)) PORTB = 7;... } } loop: skip:. ldab t1 subb t2 clra aba adda #1 cmpa #2 bls skip ldaa #7 staa $ bra loop C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

28 Verification at Assembly Level unsigned volatile char t1, t2; int main() { while (1) { if ((t1-t2 > 1) (t1-t2 < -1)) PORTB = 7;... } } loop: ldab t1 What if interrupt occurs here? subb t2 clra aba adda #1 cmpa #2 bls skip ldaa #7 staa $1004 skip:... bra loop C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

29 Verification at Assembly Level loop: ldab t1 What if interrupt occurs unsigned volatile char t1, t2; here? int main() { while (1) { if ((t1-t2 > 1) (t1-t2 < -1)) PORTB = 7; subb t2 clra aba adda #1 cmpa #2... bls skip } ldaa #7 } staa $1004 skip:... bra loop If analysis of environmental model shows that temperature cannot change by > 5 b/w interrupts, there is no problem. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

30 Current Research Have an SRC grant to pursue this research. Developing efficient reachability algorithms for LHPNs. Several examples successfully verified. Further investigating methods for automatic generation of LHPN models from VHDL-AMS and SPICE descriptions. Extending this work into embedded software verification. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

31 Genetic Circuit Analysis Microarrays and other new technologies can show how genes interact to perform complex biological functions. Systems biology perspective needed to reason about genetic circuits. Engineers have extensive experience reasoning about complex systems. The engineering approach is as follows: Examine experimental data in order to develop models. Develop efficient analysis methods to reason about these models. Use these analysis methods to assist in the design of new systems. We are doing research in all three of these areas: Developing a method for learning genetic circuit models that exploits the nature of time series experimental data. Implementing a tool to abstract a reaction-based model into a stochastic asynchronous circuit to facilitate efficient analysis. Designing a genetic Muller C-element. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

32 Phage λ Decision Circuit C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

33 Phage λ Decision Circuit C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

34 Microarrays C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

35 Microarrays E. Coli response to DNA damage from UV radiation 5 minutes Source: Stanford Microarray Database, experimenter Arkady Khodursky C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

36 Microarrays E. Coli response to DNA damage from UV radiation 10 minutes Source: Stanford Microarray Database, experimenter Arkady Khodursky C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

37 Microarrays E. Coli response to DNA damage from UV radiation 20 minutes Source: Stanford Microarray Database, experimenter Arkady Khodursky C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

38 Microarrays E. Coli response to DNA damage from UV radiation 40 minutes Source: Stanford Microarray Database, experimenter Arkady Khodursky C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

39 Microarrays E. Coli response to DNA damage from UV radiation 60 minutes Source: Stanford Microarray Database, experimenter Arkady Khodursky C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

40 Possible Genetic Circuits Models 10^15 CII CI 1 N Cro CIII C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

41 Our Approach to Learning Genetic Circuit Models Targets learning genetic circuits with tight feedback. Performs local analysis to find potential parents. Looks at two sequential time points to determine the probability of an increase in gene expression. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

42 Evaluation Method SBML Chemical Reaction Based Model A Stochastic Simulator Translator O P transcription O P Gene CII mrna translation Gene CI CII Protein Time Series Data Time N Cro CI CII CIII GeneNet Algorithm High Level Description High Level Description CII CI CII CI N Cro CIII Compare and Evaluate N Cro CIII C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

43 Genetic Circuits Used in Our Results The phage λ decision circuit gene networks inspired by Guet s synthetic circuits. 10 randomly generated 10-gene circuits. The gene circuits from Yu et al. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

44 Recall Results GeneNet Yu et al. GeneNet wins or ties in 62 of the 69 cases. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

45 Precision Results GeneNet Yu et al. GeneNet wins or ties in 57 of the 69 cases. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

46 Genetic Circuit Analysis Traditional methods use differential equation simulation. Requires assumption that molecule counts are high and reactions occur deterministically. Not true for genetic circuits, so expensive discrete, stochastic monte carlo simulation is required. Only practical for small systems with no major reaction time-scale separations. Abstraction is essential for efficient analysis. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

47 Our Approach Reactionbased Model Reactionbased Abstraction Methods Abstracted Reactionbased Model N-ary Transformation Stochastic Asynchronous Circuit Model Begins with a reaction-based model in SBML created by tools such as BioSPICE s PathwayBuilder. Next, it automatically abstracts this model leveraging the quasi-steady state assumption, whenever possible. Finally, it encodes chemical species concentrations into Boolean (or n-ary) levels to produce a stochastic asynchronous circuit model. It can now be analyzed using Markov chain analysis. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

48 Phage λ Decision Circuit C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

49 Phage λ Decision Circuit C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

50 Phage λ Results Original model has 61 species and 75 reactions. Abstracted model has 5 species and 11 reactions. Analyzed original and abstracted models for 10,000 Monte Carlo runs. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

51 Probability of Lysogeny vs. MOI Probability of Lysogeny Original Reaction Model Multiplicity of Infection Simulation time is 56.5 hours. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

52 Probability of Lysogeny vs. MOI Probability of Lysogeny Original Reaction Model Abstracted Reaction model Multiplicity of Infection Simulation time is 9.8 hours. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

53 Stochastic Asynchronous Circuit M k PL n k 2 k 1 ciii M k PL N 0.2 M k PL n k 3 k 5 Cro CroH M k PR n k 4 M k PR cii M k PRE ci M k PR M k PRM cih 0.5 M k PR k 6 C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

54 Kourilsky s Experiments Measured fraction of lysogeny vs average phage input (API). Using a Poisson distribution of the phages over the population, can map MOI results to determine fraction of lysogens versus API. The equations used are: P(M,A) = F lysogens (A) = M AM M! e A P(M,A) F(M) where M is the MOI, A is the API, and F(M) is the probability of lysogeny for each MOI value determined by Markov analysis. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

55 Fraction of Lysogens vs. API Estimated Fraction of Lysogens Stochastic Asynchronous Circuit (starved) 1e-05 O- Experimental (starved) P- Experimental (starved) Master Eqn Simulation (starved) Stochastic Asynchronous Circuit (well-fed) O- Experimental (well-fed) 1e Average Phage Input (API) SAC results generated in only 7 minutes. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

56 E. Coli Fim Switch C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

57 E. Coli Fim Switch Results [HNS]=0nM [HNS]=100nM On-to-Off switching probability [Lrp] (nm) Simulation time is 11.3 hours. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

58 E. Coli Fim Switch Results Original model -- [HNS]=0nM Original model -- [HNS]=100nM Abstracted model -- [HNS]=0nM Abstracted model -- [HNS]=100nM On-to-Off switching probability [Lrp] (nm) Simulation time is 1.0 hour. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

59 E. Coli Fim Switch Results Original model -- [HNS]=0nM Original model -- [HNS]=100nM Abstracted model -- [HNS]=0nM Abstracted model -- [HNS]=100nM Finite-state model x10 -- [HNS]=0nM Finite-state model x10 -- [HNS]=100nM On-to-Off switching probability [Lrp] (nm) Simulation time is 14 minutes. C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

60 Synthesis of Genetic Circuits Construct DNA sequence for a genetic circuit and insert into a living cell. These circuits may be used to synthesize protein therapeutics, sense toxic wastes, or as gene therapy to correct faulty cellular processes. Can also help us learn more about how microorganisms function. Researchers at MIT have even begun a registry of standard biological parts (parts.mit.edu) for use as building blocks in these circuits. Question: Can asynchronous synthesis tools be adapted to requirements for a genetic circuit technology? Challenges: Genetic circuits have no signal isolation. Gates have fan-in and fan-out complications. Gates in a genetic circuit library usually can only be used once. While Boolean logic gates have been built, there are still open issues in design of sequential logic gates (i.e., ones that use feedback to store state). C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

61 Genetic Muller C-Element x y C x y z z 1 0 z z C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

62 Genetic Muller C-Element Heat LuxI 3OC6HSL CI RBS Gene luxi Gene ci Terminator Red Light LuxR CI LacI RBS Gene luxr Gene ci Terminator RBS Gene laci Terminator LuxR 3OC6HSL TetR RBS Gene tetr Terminator Green Light LacI TetR RBS Gene GFP Gene laci Terminator RBS Gene tetr Terminator C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

63 Genetic Muller C-Element 3OC6HSL LuxI CI RBS Gene luxi Gene ci Terminator LuxR CI RBS Gene luxr Gene ci Terminator RBS Gene laci Terminator LuxR 3OC6HSL TetR RBS Gene tetr Terminator TetR RBS Gene GFP Gene laci Terminator RBS Gene tetr Terminator C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

64 Genetic Muller C-Element 3OC6HSL LuxI CI RBS Gene luxi Gene ci Terminator Red Light RBS Gene luxr Gene ci Terminator RBS Gene laci Terminator RBS Gene tetr Terminator TetR RBS Gene GFP Gene laci Terminator RBS Gene tetr Terminator C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

65 Genetic Muller C-Element Heat RBS Gene luxi Gene ci Terminator Red Light LacI RBS Gene luxr Gene ci Terminator RBS Gene laci Terminator RBS Gene tetr Terminator Green Light LacI RBS Gene GFP Gene laci Terminator RBS Gene tetr Terminator C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

66 Genetic Muller C-Element Heat RBS Gene luxi Gene ci Terminator LuxR CI RBS Gene luxr Gene ci Terminator RBS Gene laci Terminator RBS Gene tetr Terminator Green Light LacI RBS Gene GFP Gene laci Terminator RBS Gene tetr Terminator C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

67 Genetic Muller C-Element 3OC6HSL LuxI CI RBS Gene luxi Gene ci Terminator LuxR CI RBS Gene luxr Gene ci Terminator RBS Gene laci Terminator LuxR 3OC6HSL TetR RBS Gene tetr Terminator TetR RBS Gene GFP Gene laci Terminator RBS Gene tetr Terminator C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50

68 Current Research Have an NSF grant to pursue this research. Developing methods to infer genetic circuit from experimental data. Completing abstraction methodology from reaction-based models to stochastic asynchronous circuits. Beginning to explore the design of synthetic genetic circuits. More information about both projects available at our website: C. Myers et al. (U. of Utah) Efficient Circuit Analysis ECE/CS 3991 / Sept 5, / 50