Chapter 5: Register-Transfer Level (RTL) Design

Transcription

1 Chpter 5: Register-Trnsfer Level (RTL) Design Slides to ccompny the textbook, First Edition, by, John Wiley nd Sons Publishers, Copyright 27 Instructors of courses requiring Vhid's textbook (published by John Wiley nd Sons) hve permission to modify nd use these slides for customry course-relted ctivities, subject to keeping Digitl this copyright Design notice in plce nd unmodified. These slides my be posted s unnimted pdf versions on publicly-ccessible course websites.. PowerPoint source (or pdf with nimtions) my not be posted to publicly-ccessible websites, but my be posted for students on internl protected sites or distributed directly to students by other electronic mens. Instructors my mke printouts of the slides vilble to students for resonble photocopying chrge, without incurring roylties. Any other use requires explicit permission. Instructors my obtin PowerPoint Frnk source Vhid or obtin specil use permissions from Wiley see for informtion.

2 si nsis e z Introduction 5. Chpter 3: Controllers Control input/output: single bit (or just few) representing event or stte Finite-stte mchine describes behvior; implemented s stte register nd combintionl logic Chpter 4: Dtpth components Dt input/output: Multiple bits collectively representing single entity Dtpth components included registers, dders, ALU, comprtors, register files, etc. This chpter: custom processors Processor: Controller nd dtpth components working together to implement n lgorithm bi FSM inputs clk bi Register ALU Combintionl logic s s Stte register Controller Note: Slides with nimtion re denoted with smll red "" ner the nimted items bo n n Combintionl logic s s Stte register bo n n FSM outputs Comprtor Register file Register file ALU Dtpth 2

3 RTL Design: Cpture Behvior, Convert to Circuit Recll Chpter 2: Combintionl Logic Design First step: Cpture behvior (using eqution or truth tble) Remining steps: Convert to circuit Chpter 3: Sequentil Logic Design First step: Cpture behvior (using FSM) Remining steps: Convert to circuit RTL Design (the method for creting custom processors) First step: Cpture behvior (using highlevel stte mchine, to be introduced) Remining steps: Convert to circuit Cpture behvior Convert to circuit 3

4 RTL Design Method 5.2 4

5 RTL Design Method: Preview Exmple Sod dispenser c: bit input, when coin deposited : 8-bit input hving vlue of deposited coin s: 8-bit input hving cost of sod d: bit output, processor sets to when totl vlue of deposited coins equls or exceeds cost of sod c d c d s Sod dispenser processor 5 s Sod dispenser processor tot: 5 25 How cn we precisely describe this processor s behvior? 5

6 Preview Exmple: Step -- Cpture High-Level Stte Mchine Declre locl register tot Init stte: Set d=, tot= Wit stte: wit for coin If see coin, go to Add stte Add stte: Updte totl vlue: tot = tot + Remember, is present coin s vlue Go bck to Wit stte In Wit stte, if tot >= s, go to Disp(ense) stte Disp stte: Set d= (dispense sod) Return to Init stte Inputs: c (bit), (8 bits), s (8 bits) Outputs: d (bit) Locl registers: tot (8 bits) Init d= tot= c d Wit c s 8 8 Sod dispenser processor Add c *(tot<s) c *(tot<s) tot=tot+ Disp d= 6

7 Need tot register Need 8-bit comprtor to compre s nd tot Need 8-bit dder to perform tot = tot + Wire the components s needed for bove Crete control input/outputs, give them nmes Preview Exmple: Step 2 -- Crete Dtpth tot_ld tot_clr tot_lt_s s 8 ld clr Dtpth 8-bit < tot Inputs : c (bit), (8 bits), s (8 bits) Outputs : d (bit) Locl registers: tot (8 bits) 8 8-bit dder 8 Init d= tot= 8 Wit c (tot<s) c c (tot<s) 7 Add tot= tot+ Disp d=

8 Controller s inputs Preview Exmple: Step 3 Connect Dtpth to Controller Externl input c (coin detected) Input from dtpth comprtor s output, which we nmed tot_lt_s Controller s outputs Externl output d (dispense sod) Outputs to dtpth to lod nd cler the tot register c d Controller tot_ld tot_clr tot_lt_s tot_ld tot_clr tot_lt_s s 8 8 Dtpth s 8 Dtpth ld clr 8-bit < tot 8 8-bit dder 8 8 8

9 Preview Exmple: Step 4 Derive the Controller s Sme sttes nd rcs s high-level stte mchine But set/red dtpth control signls for ll dtpth c opertions d nd conditions FSM Inputs: :c,tot_lt_s(bit) Outputs:d,tot_ld, tot_clr (bit) Init d= tot_clr= Wit c d c * tot_lt_s c Controller Add tot_ld= c * tot_lt_s Disp tot_ld tot_clr tot_lt_s tot_ld s 8 8 tot_clr Dtpth tot_lt_s tot_ld tot_clr tot_lt_s s 8 ld clr 8-bit < Dtpth tpt 8 8-bit dder 8 8 Controller d= 9

10 Preview Exmple: Completing the Design Implement the FSM s stte register nd logic As in Ch3 Tble shown on right Init s s c tot_lt_s n n d tot_ld tot_clr c d Inputs: :c,tot_lt_s(bit) Outputs:d, tot_ld, tot_clr (bit) Init d= tot_clr= Wit c * tot_lt_s c Add tot_ld= c * tot_lt_s Disp tot_ld tot_clr tot_lt_s Disp Add Wit Controller d=

11 Step : Crete High-Level Stte Mchine Let s consider ech step of the RTL design process in more detil Step Sod dispenser exmple Not n FSM becuse: Multi-bit (dt) inputs nd s Locl register tot Dt opertions tot=, tot<s, tot=tot+. Useful high-level stte mchine: Dt types beyond just bits Locl registers Arithmetic equtions/expressions Inputs: c (bit), (8 bits), s (8 bits) Outputs: d (bit) Locl registers: tot (8 bits) Init d= tot= Wit c c (tot<s) c (tot<s) tot=tot+ Disp d=

12 Step Exmple: Lser-Bsed Distnce Mesurer T (in seconds) lser sensor D 2D = T sec * 3* 8 m/sec Object of interest Exmple of how to crete high-level stte mchine to describe desired processor behvior Lser-bsed distnce mesurement pulse lser, mesure time T to sense reflection Lser light trvels t speed of light, 3* 8 m/sec Distnce is thus D = T sec * 3* 8 m/sec / 2 2

13 Step Exmple: Lser-Bsed Distnce Mesurer T (in seconds) lser B from button L to lser sensor D to disply 6 Lser-bsed distnce mesurer S from sensor Inputs/outputs B: bit input, from button to begin mesurement L: bit output, ctivtes lser S: bit input, senses lser reflection D: 6-bit output, displys computed distnce 3

14 Step Exmple: Lser-Bsed Distnce Mesurer Inputs: B, S( bit ech) Outputs: L (bit), D (6 bits) from button B D to disply 6 Lserbsed distnce mesurer L to lser S from sensor S? L = (lser off) D = (distnce = ) Step : Crete high-level stte mchine Begin by declring inputs nd outputs Crete initil stte, nme it S Initilize lser to off (L=) Initilize displyed distnce to (D=) 4

15 Step Exmple: Lser-Bsed Distnce Mesurer Inputs: B, S ( bit ech) Outputs: L (bit), D (6 bits) B (button not pressed) from button B D to disply 6 Lserbsed distnce mesurer L to lser S from sensor S L = D = S B? (button pressed) Add nother stte, cll S, tht wits for button press B sty in S, keep witing B go to new stte S2 Q: Wht should S2 do? A: Turn on the lser 5

16 Step Exmple: Lser-Bsed Distnce Mesurer Inputs: B, S ( bit ech) Outputs: L (bit), D (6 bits) B from button B D to disply 6 Lserbsed distnce mesurer L to lser S from sensor S S B S2 L = D = L = (lser on) S3 L = (lser off) Add stte S2 tht turns on the lser (L=) Then turn off lser (L=) in stte S3 Q: Wht do next? A: Strt timer, wit to sense reflection 6

17 Step Exmple: Lser-Bsed Distnce Mesurer Inputs: B, S ( bit ech) Outputs: L (bit), D (6 bits) Locl Registers: Dctr (6 bits) B S (no reflection) B from button D to disply 6 Lser-bsed distnce mesurer L to lser S from sensor S S B S2 S3 L = D = Dctr = (reset cycle count) L = L = Dctr = Dctr + (count cycles) S (reflection)? Sty in S3 until sense reflection (S) To mesure time, count cycles for which we re in S3 To count, declre locl register Dctr Increment Dctr ech cycle in S3 Initilize Dctr to in S. S2 would hve been O.K. too 7

18 Step Exmple: Lser-Bsed Distnce Mesurer Inputs: B, S ( bit ech) Outputs: L (bit), D (6 bits) Locl Registers: Dctr (6 bits) B from button D to disply 6 Lser-bsed distnce mesurer L to lser S from sensor B S S S S2 S3 B S L = Dctr = L = L= D = Dctr = Dctr + Once reflection detected (S), go to new stte S4 S4 D = Dctr / 2 (clculte D) Clculte distnce Assuming clock frequency is 3x 8, Dctr holds number of meters, so D=Dctr/2 After S4, go bck to S to wit for button gin 8

19 Step 2: Crete Dtpth Dtpth must Implement dt storge Implement dt computtions Look t high-level stte mchine, do three substeps () Mke dt inputs/outputs be dtpth inputs/outputs (b) Instntite declred registers into the dtpth (lso instntite register for ech dt output) (c) Exmine every stte nd trnsition, nd instntite dtpth components nd connections to implement ny dt computtions Instntite: to introduce new component into design. 9

20 Step 2 Exmple: Lser-Bsed Distnce Mesurer () Mke dt inputs/outputs be dtpth inputs/outputs (b) Instntite declred registers into the dtpth (lso instntite register for ech dt output) (c) Exmine every stte nd trnsition, nd instntite dtpth components nd connections to implement ny dt computtions Dreg_clr Dreg_ld Dctr_clr Dctr_cnt Inputs: B, S ( bit ech) Outputs: L (bit), D (6 bits) Locl Registers: Dctr (6 bits) S S B S2 S3 L = D = Dctr = Dtpth cler count B S Q Dctr: 6-bit up-counter S L = L= Dctr = Dctr + cler lod I Q S4 D = Dctr / 2 (clculte D) Dreg: 6-bit register 6 D 2

21 Step 2 Exmple: Lser-Bsed Distnce Mesurer (c) (continued) Exmine every stte nd trnsition, nd instntite dtpth components nd connections to implement ny dt computtions Dreg_clr Dreg_ld Dctr_clr Dctr_cnt Inputs: B, S ( bit ech) Outputs: L (bit), D (6 bits) Locl Registers: Dctr (6 bits) Dtpth cler count B S S S B S2 S3 L = D = Dctr = Q Dctr: 6-bit up-counter S L = L= Dctr = Dctr + 6 cler lod >> 6 I Q Dreg: 6-bit register 6 S4 D = Dctr / 2 (clculte D) D 2

22 Step 2 Exmple Showing Mux Use Loclregisters: E, F, G, R (6 bits) E F G E F G E F G T R = E + F A + B A + B dd_a_s dd_b_s 2 2 T R = R + G R R A + B () (b) (c) R Introduce mux when one component input cn come from more thn one source (d) 22

23 Step 3: Connecting the Dtpth to Controller from button to disply B D 6 Controller Dreg_clr Dreg_ld Dctr_clr Dctr_cnt 3 MHz Clock Dtpth L S to lser from sensor Lser-bsed distnce mesurer exmple Esy just connect ll control signls between controller nd dtpth Dtpth Dreg_clr Dreg_ld Dctr_clr Dctr_cnt cler count Q Dctr: 6-bit up-counter 6 cler lod >> 6 I Q Dreg: 6-bit register 6 D 23

24 Step 4: Deriving the Controller s FSM B from buton Controller Dreg_clr Dreg_ld L to lser from sensor S Inputs: B, S ( bit ech) Outputs: L (bit), D (6 bits) Locl Registers: Dctr (6 bits) B S Dctr_clr Dtpth to disply D 6 3 MHz Clock Dctr_cnt FSM hs sme structure s highlevel stte mchine Inputs/outputs ll bits now Replce dt opertions by bit opertions using dtpth S S S2 S3 B S L = Dctr = L = L= D = Dctr = Dctr + Inputs: B, S Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt B S B S S S2 S3 L = L = Dreg_clr = L = Dreg_clr = L = Dreg_ld = Dreg_ld = Dctr_clr = Dctr_clr = Dctr_cnt = Dctr_cnt = (cler count) (lser on) Dreg_clr = Dreg_ld = Dctr_clr = Dctr_cnt = (lser off) (cler D reg) Dreg_clr = Dreg_ld = Dctr_clr = Dctr_cnt = (lser off) (count up) S S4 S4 D = Dctr / 2 (clculte D) L = Dreg_clr = Dreg_ld = Dctr_clr = Dctr_cnt = (lod D reg with Dctr/2) (stop counting) 24

25 Step 4: Deriving the Controller s FSM B S B S S S2 S3 S S4 L = L = Dreg_clr = L = Dreg_clr = L = Dreg_ld = Dreg_ld = Dctr_clr = Dctr_clr = Dctr_cnt = Dctr_cnt = (cler count) (lser on) Dreg_clr = Dreg_ld = Dctr_clr = Dctr_cnt = (lser off) (cler D reg) Dreg_clr = Dreg_ld = Dctr_clr = Dctr_cnt = (lser off) (count up) L = Dreg_clr = Dreg_ld = Dctr_clr = Dctr_cnt = (lod D reg with Dctr/2) (stop counting) Using shorthnd of outputs not ssigned implicitly ssigned Inputs: B, S Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt B S B S S S2 S3 L = Dctr_clr = L = L = (cler count) (lser on) Dctr_cnt = (lser off) (count up) Dreg_clr = (lser off) (cler D reg) S S4 Dreg_ld = Dctr_cnt = (lod D reg with Dctr/2) (stop counting) 25

26 Step 4 from button to disply B D 6 Controller Dreg_clr Dreg_ld Dctr_clr Dctr_cnt 3 MHz Clock Dtpth L to lser from sensor S Dreg_clr Dreg_ld Dctr_clr Dctr_cnt Dtpth cler count Q Dctr: 6-bit up-counter 6 cler lod >> 6 I Q Dreg: 6-bit register 6 D Inputs: B, S Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt B S B S S S2 S3 L = Dctr_clr = L = L = Dreg_clr = (cler count) (lser on) Dctr_cnt = (lser off) (lser off) (cler D reg) (count up) S S4 Dreg_ld = Dctr_cnt = (lod D reg with Dctr/2) (stop counting) Implement FSM s stte register nd logic (Ch3) to complete the design 26

27 RTL Design Exmples nd Issues 5.3 We ll use severl more exmples to illustrte RTL design Exmple: Bus interfce Mster processor cn red register from ny peripherl Ech register hs unique 4-bit ddress Assume register/periph. Sets rd=, A=ddress Approprite peripherl plces register dt on 32-bit D lines Periph s ddress provided on Fddr inputs (mybe from DIP switches, or nother register) Mster processor rd 32 D 4 A Per Per Per5 to/from processor bus rd D A Bus interfce Q Min prt Peripherl Fddr 4 27

28 RTL Exmple: Bus Interfce Inputs: rd (bit); Q (32 bits); A, Fddr (4 bits) Outputs: D (32 bits) Locl register: Q (32 bits) rd ((A = Fddr) nd rd ) WitMyAddress D = Z Q = Q (A = Fddr) nd rd SendDt D = Q rd Step : Crete high-level stte mchine Stte WitMyAddress Output nothing ( Z ) on D, store peripherl s register vlue Q into locl register Q Wit until this peripherl s ddress is seen (A=Fddr) nd rd= Stte SendDt Output Q onto D, wit for rd= (mening min processor is done reding the D lines) 28

29 RTL Exmple: Bus Interfce Inputs: rd (bit); Q (32 bits); A, Fddr (4 bits) Outputs: D (32 bits) Locl register: Q (32 bits) rd ((A = Fddr) nd rd ) WitMyAddress D = Z Q = Q (A = Fddr) nd rd SendDt D = Q rd clk Inputs rd St t e Outputs W W SD W W SD SD W D Z Q Z Q Z 29

30 RTL Exmple: Bus Interfce Inputs: rd (bit); Q (32 bits); A, Fddr (4 bits) Outputs: D (32 bits) Locl register: Q (32 bits) rd ((A = Fddr) nd rd) WitMyAddress D = Z Q = Q (A = Fddr) nd rd SendDt D = Q rd Q_ld A_eq_Fddr A Fddr Q ld Q = (4-bit) 32 Step 2: Crete dtpth () Dtpth inputs/outputs (b) Instntite declred registers (c) Instntite dtpth components nd connections D_en Bus interfce Dtpth 32 D 3

31 RTL Exmple: Bus Interfce Inputs: rd (bit); Q (32 bits); A, Fddr (4 bits) Outputs: D (32 bits) Locl register: Q (32 bits) rd Inputs: rd, A_eq_Fddr ((A = (bit) Fddr) Outputs: Q_ld, D_en nd (bit) rd) rd WitMyAddress rd SendDt D = Z Q = Q WitMyAddress D_en = Q_ld = (A = Fddr) nd (A_eq_Fddr rd nd rd) A_eq_Fddr nd rd D = Q SendDt rd D_en = Q_ld = rd A Fddr Q Q_ld ld Q = (4-bit) A_eq_Fddr 32 D_en 32 Step 3: Connect dtpth to controller Step 4: Derive controller s FSM Bus interfce Dtpth D 3

32 RTL Exmple: Video Compression Sum of Absolute Differences Only difference: bll moving Frme Frme 2 Frme Frme 2 Digitized frme Digitized frme 2 Digitized frme Difference of 2 from Mbyte () Mbyte Mbyte Video is series of frmes (e.g., 3 per second) Most frmes similr to previous frme Compression ide: just send difference from previous frme (b). Mbyte Just send difference 32

33 RTL Exmple: Video Compression Sum of Absolute compre Frme Frme 2 Differences Ech is pixel, ssume represented s byte (ctully, color picture might hve 3 bytes per pixel, for intensity of red, green, nd blue components of pixel) Need to quickly determine whether two frmes re similr enough to just send difference for second frme Compre corresponding 6x6 blocks Tret 6x6 block s 256-byte rry Compute the bsolute vlue of the difference of ech rry item Sum those differences if bove threshold, send complete frme for second frme; if below, cn use difference method (using nother technique, not described) 33

34 !(i<256) RTL Exmple: Video Compression Sum of Absolute Differences 256-byte rry A SAD 256-byte rry B sd integer go Wnt fst sum-of-bsolute-differences (SAD) component When go=, sums the differences of element pirs in rrys A nd B, outputs tht sum 34

35 !(i<256) RTL Exmple: Video Compression Sum of Absolute Differences A B SAD sd Inputs: A, B (256 byte memory); go (bit) Outputs: sd (32 bits) Locl registers: sum, sd_reg (32 bits); i (9 bits) go S: wit for go S: initilize sum nd index S2: check if done (i>=256) S3: dd difference to sum, increment index S4: done, write to output sd_reg (i<256) S S S2 S3 S4 go!go sum = i = i<256 sum=sum+bs(a[i]-b[i]) i=i+ sd_reg = sum 35

36 !(i<256)(i_lt_256)!(i<256) RTL Exmple: Video Compression Sum of Absolute Differences Inputs: A, B (256 byte memory); go (bit) Outputs: sd (32 bits) Locl registers: sum, sd_reg (32 bits); i (9 bits) (i<256) S S S2 S3 S4 go!go sum = i = i<256 sum=sum+bs(a[i]-b[i]) i=i+ sd_reg=sum i_lt_256 i_inc i_clr sum_ld sum_clr sd_reg_ld Dtpth <256 AB_ddr A_dt B_dt sum 32 9 i sd_reg bs Step 2: Crete dtpth sd 36

37 ?!(i<256)(i_lt_256)!(i<256)(i_lt_256)!(i<256) RTL Exmple: Video Compression Sum of Absolute Differences go AB_rd AB_ddr A_dt B_dt S go S S2 S4 go sum= sum_clr= i= i_clr= i<256 i_lt_256 S3 sum=sum+bs(a[i]-b[i]) sum_ld=; AB_rd= i=i+ i_inc= sd_reg=sum sd_reg_ld= Controller i_lt_256 i_inc i_clr sum_ld sum_clr sd_reg_ld <256 sum sd_reg sd 9 i bs Step 3: Connect to controller Step 4: Replce high-level stte mchine by FSM 37

38 !(i<256)(i_lt_256)!(i<256) RTL Exmple: Video Compression Sum of Absolute Differences Compring softwre nd custom circuit SAD Circuit: Two sttes (S2 & S3) for ech i, 256 i s 52 clock cycles Softwre: Loop (for i = to 256), but for ech i, must move memory to locl registers, subtrct, compute bsolute vlue, dd to sum, increment i sy bout 6 cycles per rry item 256*6 = 536 cycles Circuit is bout 3 times (3%) fster Lter, we ll see how to build SAD circuit tht is even fster (i<256) S2 S3 i<256 sum=sum+bs(a[i]-b[i]) i=i+ 38

39 RTL Design Pitflls nd Good Prctice Common pitfll: Assuming register is updte in the stte it s written Finl vlue of Q? Finl stte? Answers my surprise you Vlue of Q unknown Finl stte is C, not D Why? Stte A: R=99 nd Q=R hppen simultneously Stte B: R not updted with R+ until next clock cycle, simultneously with stte register being updted Locl registers: R, Q (8 bits) A R=99 Q=R clk R Q A 99?? B R=R+ () R< B 99? (b) R<? C C R>= D 39

40 RTL Design Pitflls nd Good Prctice Solutions Red register in following stte (Q=R) Insert extr stte so tht conditions use updted vlue Other solutions re possible, depends on the exmple Locl registers: R, Q (8 bits) A R=99 Q=R clk R A 99? B R=R+ Q=R () B2 R< R< R>= B B2 D 99 C R>= D Q?? (b) 4

41 RTL Design Pitflls nd Good Prctice Common pitfll: Reding outputs Outputs cn only be written Solution: Introduce dditionl register, which cn be written nd red Inputs: A, B (8 bits) Outputs: P (8 bits) S P=A () T P=P+B Inputs: A, B (8 bits) Outputs: P (8 bits) Locl register: R (8 bits) S R=A P=A (b) T P=R+B 4

42 RTL Design Pitflls nd Good Prctice Good prctice: Register ll dt outputs In fig (), output P would show spurious vlues s ddition computes Furthermore, longest register-to-register pth, which determines clock period, is not known until tht output is connected to nother component In fig (b), spurious outputs reduced, nd longest register-to-register pth is cler R () + P B R + Preg P (b) B 42

43 Control vs. Dt Dominted RTL Design Designs often ctegorized s control-dominted or dtdominted Control-dominted design Controller contins most of the complexity Dt-dominted design Dtpth contins most of the complexity Generl, descriptive terms no hrd rule tht seprtes the two types of designs Lser-bsed distnce mesurer control dominted Bus interfce, SAD circuit mix of control nd dt Now let s do dt dominted design 43

44 Dt Dominted RTL Design Exmple: FIR Filter Filter concept Suppose X is dt from temperture sensor, nd prticulr input sequence is 8, 8, 8, 24, 8, 8 (one per clock cycle) Tht 24 is probbly wrong! Could be electricl noise Filter should remove such noise in its output Y Simple filter: Output verge of lst N vlues Smll N: less filtering Lrge N: more filtering, but less shrp output X clk 2 digitl filter 2 Y 44

45 Dt Dominted RTL Design Exmple: FIR Filter FIR filter Finite Impulse Response Simply configurble weighted sum of pst input vlues y(t) = c*x(t) + c*x(t-) + c2*x(t-2) Above known s 3 tp Tens of tps more common Very generl filter User sets the constnts (c, c, c2) to define specific filter RTL design Step : Crete high-level stte mchine But there relly is none! Dt dominted indeed. Go stright to step 2 X Y 2 digitl filter 2 clk y(t) = c*x(t) + c*x(t-) + c2*x(t-2) 45

46 Dt Dominted RTL Design Exmple: FIR Filter Step 2: Crete dtpth Begin by creting chin of xt registers to hold pst vlues of X X clk 2 digitl filter y(t) = c*x(t) + c*x(t-) + c2*x(t-2) 2 Y Suppose sequence is: 8, 8, 24 3-tp FIR filter x(t) x(t-) x(t-2) X xt xt xt Y clk 46

47 Dt Dominted RTL Design Exmple: FIR Filter Step 2: Crete dtpth (cont.) Instntite registers for c, c, c2 Instntite multipliers to compute c*x vlues X Y 2 digitl filter 2 clk y(t) = c*x(t) + c*x(t-) + c2*x(t-2) X 3-tp FIR filter x(t) c x(t-) c x(t-2) xt xt xt2 c2 clk Y 47

48 Dt Dominted RTL Design Exmple: FIR Filter Step 2: Crete dtpth (cont.) Instntite dders X Y 2 digitl filter 2 clk y(t) = c*x(t) + c*x(t-) + c2*x(t-2) X clk 3-tp FIR filter x(t) c x(t-) c x(t-2) c2 xt xt xt2 + + Y 48

49 Dt Dominted RTL Design Exmple: FIR Filter Step 2: Crete dtpth (cont.) Add circuitry to llow loding of prticulr c register X clk 2 digitl filter y(t) = c*x(t) + c*x(t-) + c2*x(t-2) 2 Y CL C C C e 3 2x4 2 3-tp FIR filter X clk x(t) c x(t-) c x(t-2) c2 xt xt xt2 * * * + + yreg Y 49

50 Dt Dominted RTL Design Exmple: FIR Filter y(t) = c*x(t) + c*x(t-) + c2*x(t-2) Step 3 & 4: Connect to controller, Crete FSM No controller needed Extreme dt-dominted exmple (Exmple of n extreme control-dominted design n FSM, with no dtpth) Compring the FIR circuit to softwre implementtion Circuit Assume dder hs 2-gte dely, multiplier hs 2-gte dely Longest pst goes through one multiplier nd two dders = 24-gte dely -tp filter, following design on previous slide, would hve bout 34-gte dely: multiplier nd 7 dders on longest pth Softwre -tp filter: multiplictions, dditions. Sy 2 instructions per multipliction, 2 per ddition. Sy -gte dely per instruction. (*2 + *2)* = 4 gte delys Circuit is more thn times fster (,% fster). Wow. 5

51 Determining Clock Frequency 5.4 Designers of digitl circuits often wnt fstest performnce Mens wnt high clock frequency Frequency limited by longest register-to-register dely Known s criticl pth If clock is ny fster, incorrect dt my be stored into register Longest pth on right is 2 ns Ignoring wire delys, nd register setup nd hold times, for simplicity clk 2 ns dely + c b 5

52 Criticl Pth Exmple shows four pths to c through +: 2 ns to d through + nd *: 7 ns b to d through + nd *: 7 ns b b to d through *: 5 ns Longest pth is thus 7 ns Fstest frequency / 7 ns = 42 MHz 2 ns dely Mx (2,7,7,5) = 7 ns 2 ns + * c 7 ns 7 ns 7 ns 7 ns d 5 ns 5 ns dely 52

53 3ns Criticl Pth Considering Wire Delys Rel wires hve dely too Must include in criticl pth Exmple shows two pths Ech is = 3 ns Trend 98s/99s: Wire delys were tiny compred to logic delys But wire delys not shrinking s fst s logic delys Wire delys my even be greter thn logic delys! Must lso consider register setup nd hold times, lso dd to pth Then dd some time to the computed pth, just to be sfe e.g., if pth is 3 ns, sy 4 ns insted clk.5 ns 3 ns + c 3 ns b.5 ns 2 ns.5 ns 53

54 A Circuit My Hve Numerous Pths Pths cn exist s In the dtpth Combintionl logic 8 8 In the controller d Between the controller nd dtpth My be hundreds or thousnds of pths Timing nlysis tools tht evlute ll possible pths utomticlly very helpful c tot_lt_s clk s s Stte register tot_ld tot_clr (c) n n tot_lt_s (b) ld clr Dtpth 8-bit < tot 8 8-bit dder () 8 54

55 Behviorl Level Design: C to Gtes 5.5 (i<256) S go S S2!go sum = i = i<256 sum=sum+bs(a[i]-b[i]) S3 i=i+ S4 sd_reg = sum C code int SAD (byte A[256], byte B[256]) // not quite C syntx { uint sum; short uint I; sum = ; i = ; while (i < 256) { sum = sum + bs(a[i] B[i]); i = i + ; } return sum; } Erlier sum-of-bsolute-differences exmple Strted with high-level stte mchine C code is n even better strting point -- esier to understnd 55

56 Behviorl-Level Design: Strt with C (or Similr Lnguge) Replce first step of RTL design method by two steps Cpture in C, then convert C to high-level stte mchine How convert from C to high-level stte mchine? Step A: Cpture in C Step B: Convert to high-level stte mchine 56

57 Converting from C to High-Level Stte Mchine Convert ech C construct to equivlent sttes nd trnsitions Assignment sttement Becomes one stte with ssignment trget = expression; trget= expression If-then sttement Becomes stte with condition check, trnsitioning to then sttements if condition true, otherwise to ending stte if (cond) { // then stmts } cond (then stmts)!cond then sttements would lso be converted to sttes (end) 57

58 Converting from C to High-Level Stte Mchine If-then-else Becomes stte with condition check, trnsitioning to then sttements if condition true, or to else sttements if condition flse if (cond) { // then stmts } else { // else stmts } (end)!cond cond (then stmts) (else stmts) While loop sttement!cond Becomes stte with condition check, trnsitioning to while loop s sttements if true, then trnsitioning bck to condition check while (cond) { // while stmts } cond (while stmts) (end) 58

59 Simple Exmple of Converting from C to High- Level Stte Mchine Inputs: uint X, Y Outputs: uint Mx!(X>Y)!(X>Y) X>Y X>Y if (X > Y) { Mx = X; (then stmts) (else stmts) Mx=X Mx=Y } else { } Mx = Y; (end) (end) () Simple exmple: Computing the mximum of two numbers Convert if-then-else sttement to sttes (b) Then convert ssignment sttements to sttes (c) (b) (c) 59

60 Exmple: Converting Sum-of-Absolute-Differences C code to High-Level Stte Mchine Convert ech construct to sttes Simplify when possible, e.g., merge sttes From high-level stte mchine, follow RTL design method to crete circuit Thus, cn convert C to gtes using strightforwrd utomtble process Not ll C constructs cn be efficiently converted Use C subset if intended for circuit Cn use lnguges other thn C, of course Inputs: byte A[256, B[256] bit go; Output: int sd min() { uint sum; short uint I; while () { } while (!go); sum = ; i = ; while (i < 256) { (b) sum = sum + bs(a[i] - B[i]); i = i + ; } } sd = sum;!go go ()!go go sum= i= sum= i= i<256 while stmts (e)!(i<256)!go sd = sum (f)!(!go) i<256 sum=sum + bs i = i +!(i<256)!go sum= i= (c)!go go (g) go sum= i= sd = sum i<256 sum=sum + bs i = i +!go!(i<256) sum= i= (d) 6 go

61 Memory Components 5.6 Register-trnsfer level design instntites dtpth components to crete dtpth, controlled by controller A few more components re often used outside the controller nd dtpth MxN memory M words, N bits wide ech Severl vrieties of memory, which we now introduce M words N-bits wide ech M Nmemory 6

62 Rndom Access Memory (RAM) RAM Redble nd writble memory Rndom ccess memory Strnge nme Creted severl decdes go to contrst with sequentilly-ccessed storge like tpe drives Logiclly sme s register file Memory with ddress inputs, dt inputs/outputs, nd control RAM usully just one port; register file usully two or more RAM vs. register file RAM typiclly lrger thn roughly 52 or 24 words RAM typiclly stores bits using bit storge pproch tht is more efficient thn flip flop RAM typiclly implemented on chip in squre rther thn rectngulr shpe keeps longest wires (hence dely) short 32 4 W_dt W_ddr R_dt R_ddr W_en R_en 6 32 register file 32 Register file from Chpt dt ddr rw en RAM RAM block symbol 62 4

63 dr RAM Internl Structure 32 dt ddr rw en 24x32 RAM Let A = log 2 M d wdt(n-) word enble wdt(n-2) wdt bit storge block (k cell ) ddr ddr ddr(a-) AxM d decoder (A-) word dt cell clk en rw e d(m-) to ll cells rdt(n-) rdt(n-2) rdt word word enble enble rw dt RAM cell Similr internl structure s register file Decoder enbles pproprite word bsed on ddress inputs rw controls whether cell is written or red Let s see wht s inside ech RAM cell 63

64 32 dt ddr rw en 24x32 RAM ddr ddr ddr ddr(a-) clk en rw Sttic RAM (SRAM) wdt(n-) Let A = log 2 M word enble d A M d decoder (A-) Sttic RAM cell 6 trnsistors (recll inverter is 2 trnsistors) Writing this cell word enble input comes from decoder When, vlue d loops round inverters Tht loop is where bit stys stored When, the dt bit vlue enters the loop dt is the bit to be stored in this cell dt enters on other side Exmple shows being written into cell e d(m-) to ll cells rdt(n-) wdt(n-2) rdt(n-2) wdt rdt bit storge block,, (k cell ) word,, dt cell word enble word enble rw dt word enble dt SRAM cell dt word enble SRAM cell word enble d dt dt cell d d d dt cell d dt 64

65 Sttic RAM (SRAM) 32 dt ddr rw en 24x32 RAM Sttic RAM cell Reding this cell Somewht trickier When rw set to red, the RAM logic sets both dt nd dt to The stored bit d will pull either the left line or the right bit down slightly below Sense mplifiers detect which side is slightly pulled down The electricl description of SRAM is relly beyond our scope just generl ide here, minly to contrst with DRAM... ddr ddr ddr ddr(a-) clk en rw wdt(n-) Let A = log 2 M word enble d A M d decoder (A-) e d(m-) to ll cells rdt(n-) wdt(n-2) rdt(n-2) wdt rdt bit storge block,, (k cell ) word,, dt cell word enble word enble rw dt SRAM cell word enble dt dt d < To sense mplifiers 65

66 Dynmic RAM (DRAM) 32 dt ddr rw en 24x32 RAM Dynmic RAM cell trnsistor (rther thn 6) Relies on lrge cpcitor to store bit Write: Trnsistor conducts, dt voltge level gets stored on top plte of cpcitor Red: Just look t vlue of d Problem: Cpcitor dischrges over time ddr ddr ddr ddr(a-) clk en rw wdt(n-) Let A = log 2 M word enble d A M d decoder (A-) e d(m-) to ll cells rdt(n-) wdt(n-2) rdt(n-2) wdt Must refresh regulrly, by reding d nd then writing it right bck rdt bit storge block,, (k cell ) word,, dt cell word enble word enble rw dt DRAM cell word enble dt enble d dt d () dischrges (b) cell cpcitor slowly dischrging 66

67 Compring Memory Types Register file Fstest But biggest size SRAM Fst More compct thn register file DRAM Slowest And refreshing tkes time But very compct Use register file for smll items, SRAM for lrge items, nd DRAM for huge items Note: DRAM s big cpcitor requires specil chip design process, so DRAM is often seprte chip register file MxN Memory implemented s : SRAM DRAM Size comprison for sme number of bits (not to scle) 67

68 Reding nd Writing RAM clk ddr dt rw en mens write 999 Z 5 RAM[9] RAM[3] now equls 5 now equls 999 vlid vlid setup time hold time setup time Writing (b) Put ddress on ddr lines, dt on dt lines, set rw=, en= Reding Set ddr nd en lines, but put nothing (Z) on dt lines, set rw= Dt will pper on dt lines Don t forget to obey setup nd hold times In short keep inputs stble before nd fter clock edge 3 clk ddr dt rw Z 5 ccess time 68

69 RAM Exmple: Digitl Sound Recorder RAM dt ddr rw en wire microphone nlog-todigitl converter 6 d_buf d_ld 2 R Rrw Ren processor d_ld digitl-tonlog converter wire Behvior speker Record: Digitize sound, store s series of bit digitl vlues in RAM We ll use 496x6 RAM (2-bit wide RAM not common) Ply bck lter Common behvior in telephone nswering mchine, toys, voice recorders To record, processor should red -to-d, store red vlues into successive RAM words To ply, processor should red successive RAM words nd enble d-to- 69

70 RAM Exmple: Digitl Sound Recorder RTL design of processor Crete high-level stte mchine Begin with the record behvior Keep locl register Stores current ddress, rnges from to 495 (thus need 2 bits) Crete stte mchine tht counts from to 495 using For ech Red nlog-to-digitl conv.» d_ld=, d_buf= Write to RAM t ddress» R=, Rrw=, Ren= nlog-todigitl converter 6 d_buf d_ld Record behvior S = 496x6 RAM 2 processor Locl register: (2 bits) T d_ld= d_buf= R= Rrw= Ren= R Rw Ren d_ld <495 U =+ =495 digitl-tonlog converter 7

71 RAM Exmple: Digitl Sound Recorder Now crete ply behvior Use locl register gin, crete stte mchine tht counts from to 495 gin For ech Red RAM Write to digitl-to-nlog conv. Note: Must write d-to- one cycle fter reding RAM, when the red dt is vilble on the dt bus The record nd ply stte mchines would be prts of lrger stte mchine controlled by signls tht determine when to record or ply nlog-todigitl converter 6 d_buf d_ld Ply behvior V = 496x6 RAM 2 processor Locl register: (2 bits) W d_buf= R= Rrw= Ren= R Rw Ren d_ld <495 X d_ld= =+ =495 dt bus digitl-tonlog converter 7

72 Red-Only Memory ROM Memory tht cn only be red from, not written to Dt lines re output only No need for rw input Advntges over RAM Compct: My be smller Nonvoltile: Sves bits even if power supply is turned off Speed: My be fster (especilly thn DRAM) Low power: Doesn t need power supply to sve bits, so cn extend bttery life Choose ROM over RAM if stored dt won t chnge (or won t chnge often) For exmple, tble of Celsius to Fhrenheit conversions in digitl thermometer dt ddr rw en dt ddr en RAM RAM block symbol 24x32 ROM ROM block symbol 72

73 dr Red-Only Memory ROM 32 dt ddr en 24x32 ROM ROM block symbol ddr ddr ddr(a-) Let A = log 2 M d AxM d decoder (A-) word enble bit storge block (k cell ) word dt clk en e d(m-) word word enble enble dt rdt(n-) rdt(n-2) rdt ROM cell Internl logicl structure similr to RAM, without the dt input lines 73

74 ROM Types If ROM cn only be red, how re the stored bits stored in the first plce? Storing bits in ROM known s progrmming Severl methods Msk-progrmmed ROM Bits re hrdwired s s or s during chip mnufcturing 2-bit word on right stores word enble (from decoder) simply psses the hrdwired vlue through trnsistor Notice how compct, nd fst, this memory would be ddr word enble ddr ddr ddr(a-) en Let A = log 2 M word enble d A M d decoder (A-) e d(m-) dt(n-) dt(n-2) dt dt line cell bit storge block,, ( cell ),, word dt cell word word enble enble dt dt line cell 74

75 ROM Types Fuse-Bsed Progrmmble ROM Ech cell hs fuse A specil device, known s progrmmer, blows certin fuses (using higher-thn-norml voltge) Those cells will be red s s (involving some specil electronics) Cells with unblown fuses will be red s s 2-bit word on right stores Also known s One-Time Progrmmble (OTP) ROM ddr ddr ddr ddr(a-) en word enble Let A = log 2 M word enble d A M d decoder (A-) e d(m-) cell fuse dt(n-) dt(n-2) dt dt line bit storge block,, ( cell ) word,, cell blown fuse dt cell word word enble enble dt dt line 75

76 ting or t r et t g ROM Types Ersble Progrmmble ROM (EPROM) Uses floting-gte trnsistor in ech cell Specil progrmmer device uses higherthn-norml voltge to cuse electrons to tunnel into the gte Electrons become trpped in the gte Only done for cells tht should store Other cells (without electrons trpped in gte) will be 2-bit word on right stores Detils beyond our scope just generl ide is necessry here To erse, shine ultrviolet light onto chip Gives trpped electrons energy to escpe Requires chip pckge to hve window ddr floting-gte trnsistor ddr ddr ddr(a-) en word enble Let A = log 2 M word enble d A M d decoder (A-) e d(m-) dt(n-) dt(n-2) dt dt line cell bit storge block,, ( cell ) word,, dt cell word word enble enble dt dt line e Ð e Ð trpped electrons cell 76

77 ting or t r et t g ROM Types Electroniclly-Ersble Progrmmble ROM (EEPROM) Similr to EPROM Uses floting-gte trnsistor, electronic progrmming to trp electrons in certin cells But ersing done electroniclly, not using UV light Ersing done one word t time Flsh memory Like EEPROM, but ll words (or lrge blocks of words) cn be ersed simultneously Become common reltively recently (lte 99s) Both types re in-system progrmmble Cn be progrmmed with new stored bits while in the system in which the ROM opertes Requires bi-directionl dt lines, nd write control input Also need busy output to indicte tht ersing is in progress ersing tkes some time 32 dt ddr en write busy 24x32 EEPROM 77

78 d ROM Exmple: Tlking Doll 496x6 ROM Hello there! Hello there! udio divided into 496 smples, stored in ROM speker Hello there! 6 R Ren digitl-tonlog converter vibrtion sensor processor d_ld v Doll plys prerecorded messge, trigger by vibrtion Messge must be stored without power supply Use ROM, not RAM, becuse ROM is nonvoltile And becuse messge will never chnge, use msk-progrmmed ROM or OTP ROM Processor should wit for vibrtion (v=), then red words to 495 from the ROM, writing ech to the d-to- 78

79 d ROM Exmple: Tlking Doll 496x6 ROM = Locl register: (2 bits) v <495 S T 6 R Ren processor d_ld digitl-tonlog converter v v R= Ren= =495 U d_ld= =+ High-level stte mchine Crete stte mchine tht wits for v=, nd then counts from to 495 using locl register For ech, red ROM, write to digitl-to-nlog converter 79

80 busy ROM Exmple: Digitl Telephone Answering Mchine Using Flsh Memory Wnt to record the outgoing nnouncement When rec=, record digitized sound in loctions to 495 When ply=, ply those stored sounds to digitl-tonlog converter Wht type of memory? Should store without power supply ROM, not RAM Should be in-system progrmmble EEPROM or Flsh, not EPROM, OTP ROM, or msk-progrmmed ROM Will lwys erse entire memory when reprogrmming Flsh better thn EEPROM nlog-todigitl converter 6 d_buf d_ld 2 496x6 Flsh We re not home. microphone R Rrw Rener processor rec record ply speker bu d_ld digitl-tonlog converter 8

81 d w r en ROM Exmple: Digitl Telephone Answering Mchine Using Flsh Memory High-level stte mchine Once rec=, begin ersing flsh by setting er= Wit for flsh to finish ersing by witing for bu= Execute loop tht sets locl register from to 495, reding nlog-todigitl converter nd writing to flsh for ech nlog-todigitl converter S = er= rec 6 d_buf d_ld 2 microphone 496x6 Flsh R processor record Rrw Ren er rec ply speker bu d_ld Locl register: (3 bits) bu <496 T bu U er= d_ld= d_buf= R= V Rrw= Ren= =+ =496 digitl-tonlog converter 8

82 Blurring of Distinction Between ROM nd RAM We sid tht RAM is redble nd writble ROM Flsh RAM EEPROM NVRAM ROM is red-only But some ROMs ct lmost like RAMs EEPROM nd Flsh re in-system progrmmble Essentilly mens tht writes re slow Also, number of writes my be limited (perhps few million times) And, some RAMs ct lmost like ROMs Non-voltile RAMs: Cn sve their dt without the power supply One type: Built-in bttery, my work for up to yers Another type: Includes ROM bckup for RAM controller writes RAM contents to ROM before turning off New memory technologies evolving tht merge RAM nd ROM benefits e.g., MRAM Bottom line Lot of choices vilble to designer, must find best fit with design gols 82

83 Queues 5.7 A queue is nother component sometimes used during RTL design Queue: A list written to t the bck, from red from the front Like list of witing resturnt customers Writing clled push, reding clled pop Becuse first item written into queue will be the first item red out, lso clled FIFO (first-infirst-out) write items to the bck of the queue bck front red (nd remove) items from front of the queue 83

84 Queues Queue hs ddresses, nd two pointers: rer nd front Initilly both point to Push (write) Item written to ddress pointed to by rer rer incremented Pop (red) Item red from ddress pointed to by front front incremented If front or rer reches 7, next (incremented) vlue should be (for queue with ddresses to 7) A B r 2 r B B r f A f A f A r f 84

85 r Queues Tret memory s circle If front or rer reches 7, next (incremented) vlue should be rther thn 8 (for queue with ddresses to 7) Two conditions of interest Full queue no room for more items In 8-entry queue, mens 8 items present No further pushes llowed until pop occurs Cuses front=rer Empty queue no items No pops llowed until push occurs Cuses front=rer Both conditions hve front=rer To detect whether front=rer mens full or empty, need stte mchine tht detects if previous opertion ws push or pop, sets full or empty output signl (respectively) B r f 7 B 2 6 r f A

86 Queue Implementtion Cn use register file for item storge Implement rer nd front using up counters rer used s register file s write ddress, front s red ddress Simple controller would set control lines for pushes nd pops, nd lso detect full nd empty situtions FSM for controller not shown wdt wr rd reset Cont roller 8 6 register file 6 6 wdt rdt 3 clr inc 3-bit up counter rer eq wddr wr = clr rddr rd inc 3-bit up counter front 3 8-word 6-bit queue rdt full empty 86

87 Computer keybord Common Uses of Queue Pushes pressed keys onto queue, menwhile pops nd sends to computer Digitl video recorder Pushes cptured frmes, menwhile pops frmes, compresses them, nd stores them Computer network routers Pushes incoming pckets onto queue, menwhile pops pckets, processes destintion informtion, nd forwrds ech pcket out over pproprite port 87

88 Queue Usge Exmple Exmple series of pushes nd pops Note how rer nd front pointers move Note tht popping doesn t relly remove the dt from the queue, but tht dt is no longer ccessible Note how rer (nd front) wrps round from ddress 7 to Note: pushing full queue is n error As is popping n empty queue Initilly empty queue. After pushing 9, 5, 8, 5, 7, 2, 3 2. After popping 3. After pushing 6 4. After pushing r 7 r f 5 f 5 r f 9 f 9 9 r 3 dt: 9 full r f 5. After pushing 4 ERROR! Pushing full queue results in unknown stte 88

89 P r o vin c e P r o vin c e2 P r o vin c e3 vin P r o c e vin P r o c e2 vin P r o c Hierrchy A Key Design Concept 5.8 Hierrchy An orgniztion with few items t the top, with ech item decomposed into other items Common exmple: A country item t the top (the country) Country item decomposed into stte/province items Ech stte/province item decomposed into city items Hierrchy helps us mnge complexity To go from trnsistors to gtes, muxes, decoders, registers, ALUs, controllers, dtpths, memories, queues, etc. Imgine trying to comprehend controller nd dtpth t the level of gtes CityA CityB CityC Province Province CityD CityE Province 2 Country A Province 2 CityF CityG Province 3 Mp showing ll levels of hierrchy Country A Province 3 Mp showing just top two levels of hierrchy 89

90 P r o vin c e P r o vin c e2 P r o vin c e3 vin P r o c e vin P r o c e2 vin P r o c e3 Hierrchy nd Abstrction Abstrction Hierrchy often involves not just grouping items into new item, but lso ssociting higher-level behvior with the new item, known s bstrction e.g., n 8-bit dder hs n understndble high-level behvior it dds two 8-bit binry numbers Frees designer from hving to remember, or even from hving to understnd, the lower-level detils 7.. b7.. b 8-bit dder ci co s7.. s 9

91 P r o vin c e P r o vin c e2 P r o vin c e3 vin P r o c e vin P r o c e2 vin P r o c e3 Hierrchy nd Composing Lrger Components from Smller Versions A common tsk is to compose smller components into lrger one Gtes: Suppose you hve plenty of 3-input AND gtes, but need 9-input AND gte Cn simple compose the 9-input gte from severl 3-input gtes Muxes: Suppose you hve 4x nd 2x muxes, but need n 8x mux s2 selects either top or bottom 4x ss select prticulr 4x input Implements 8x mux 8 dt inputs, 3 selects, one output i i i2 i3 i4 i5 i6 i7 4 i i i2 i3 4 i i i2 i3 s d s d i i s 2 d s s s s s2 9

92 dr en P r o vin c e P r o vin c e2 dr en P r o vin c e3 P r o P r o vin P r o c e3 Hierrchy nd Composing Lrger Components from Smller Versions Composing memory very common Mking memory words wider Esy just plce memories side-by-side until desired width obtined Shre ddress/control lines, conctente dt lines Exmple: Compose 24x8 ROMs into 24x32 ROM ddr 24x8 ROM en dt ddr 24x8 ROM en dt ddr 24x8 ROM en dt ddr 24x8 ROM en dt dt(3..) 24x32 ROM dt 32 92

93 P r o vin c e P r o vin c e2 P r o vin c e3 dr en P vin dr en P r o c e2 vin P r o c e3 Hierrchy nd Composing Lrger Components from Smller Versions Creting memory with more words Put memories on top of one nother until the number of desired words is chieved Use decoder to select mong the memories Cn use highest order ddress input(s) s decoder input Although ctully, ny ddress line could be used Exmple: Compose 24x8 memories into 248x8 memory just chooses which memory to ccess 98 ddr 24x8 ROM en ddr en dt 24x8 ROM dt 9.. i 248x8 ROM dt 8 x2 dcd e d d ddr en 24x8 ROM ddr en dt 24x8 ROM 8 dt To crete memory with more words nd wider words, cn first compose to enough words, then widen. 8 93

94 Chpter Summry Modern digitl design involves creting processor-level components Four-step RTL method cn be used. High-level stte mchine 2. Crete dtpth 3. Connect dtpth to controller 4. Derive controller FSM Severl exmple Control dominted, dt dominted, nd mix Determining fstest clock frequency By finding criticl pth Behviorl-level design C to gtes By using method to convert C (subset) to high-level stte mchine Additionl RTL components Memory: RAM, ROM Queues Hierrchy: A key concept used throughout Chpters