ECE 327 Solution to Midterm 2016t1 (Winter)

Transcription

1 ECE 7 Solution to Midterm 6t (Winter) All requests for re-mrks must be submitted in writing to Mrk Agrd before 8:m on ridy Mrch. A rndom collection of midterms were scnned. Exms tht re submitted for re-mrking will be verified ginst this set. Totl Approx. Mrks Time Pge VL Semntics Control Circuitry SM 5 9 Totls 7

2 ECE 7 6t (Winter) Solution to Midterm (5 Mrks) VL Semntics (estimted time: 5 minutes) or the VL progrm below, clculte the vlues for the signls c, d, e, nd f t 5ns. NOTES:. All of the processes re in the sme rchitecture.. The signls, b, c, d, e, nd f re declred to be unsigned(5 downto ).. or full mrks you must justify your nswer, using text nd/or the wveform digrm. You my, but re not required to, show delt-cycle simultion. process begin clk <= ; wit for ns; clk <= ; wit for ns; end process; process begin <= (others => ); wit for ns; <= + ; <= + ; wit until rising_edge( clk ); <= + ; <= + ; wit until rising_edge( clk ); <= + ; <= + ; wit until rising_edge( clk ); <= + ; <= + ; wit; end process; clk <= clk; b <= ; process begin wit until rising_edge( clk ); c <= ; d <= b; end process; process begin wit until rising_edge( clk ); e <= ; f <= b; end process; (pge of )

3 ECE 7 6t (Winter) Solution to Midterm Answer: The schemtic is not necessry prt of the nswer. c e δ b d f clk δ clk ns 5ns ns+δ ns+δ ns+δ ns+δ clk clk b vlue t 5ns c U c d U d e U e f U f No chnges from end of ns + δ simultion cycle to 5 ns Mrking: + mrk if nswered completely with correct justifiction -5% of erned mrk if insufficient or incorrect justifiction c d 6 mrks mrks mrks mrks 6 mrks mrks mrks, e f 6 mrks mrks,, mrks mrks 6 mrks mrks, mrks mrks,, (pge of )

4 ECE 7 6t (Winter) Solution to Midterm (5 Mrks) (estimted time: minutes) Beginning with the dt-dependency grph below, design dtflow digrm, nd then perform lloction. Idx i Lo Idx i Lo I z NOTES:. Reset initilizes Idx, i, nd Lo. Your dtflow digrm shll not show this initiliztion.. Outputs shll be registered. Optimiztion gols in order of decresing importnce: () minimize re i. number of components ii. number of components iii. number of components iv. number of I components v. number of registers vi. number of multiplexers vii. number of chip-enbles (b) minimize ltency (c) minimize clock period. You shll not use ny lgebric optimiztions, Answer: Idx i Lo mx possible: 5 mrks muxes ce I r r r r s s s s r r r r r r r r r r I r r r r r r r Ltency Clock period Number of Number of Number of Number of I Number of regs Number of : muxes Number of chip-enbles lop + Mx( ++, I) I r r r Idx i Lo o (pge of )

5 ECE 7 6t (Winter) Solution to Midterm Idx i Lo mx possible: mrks muxes ce I r r r r s s s s r r r r r r r r r I r r r r r r r Ltency Clock period Number of Number of Number of Number of I Number of regs Number of : muxes Number of chip-enbles lop + Mx( +, +, +I) I r r r Idx i Lo o mx possible: mrks (pge 5 of )

6 ECE 7 6t (Winter) Solution to Midterm Idx i Lo I r r r r s s s s r r r r r r r r r I muxes ce 5 r r r r r r r Ltency Clock period Number of Number of Number of Number of I Number of regs Number of : muxes Number of chip-enbles lop + Mx( +, +, I) 5 r r r I r r Idx i Lo r o Idx i Lo mx possible: 8 mrks muxes ce I r r r r s s s s r r r r r r r r I 6 r r r r r r r Ltency Clock period Number of Number of Number of Number of I Number of regs Number of : muxes Number of chip-enbles lop + Mx( +, +, I) 6 I r r r Idx i Lo o (pge 6 of )

7 ECE 7 6t (Winter) Solution to Midterm Mrking: 7 mrks is syntcticlly nd functionlly correct ll inter-prcel vribles t top of ll inter-prcel vribles t bottom of registered inter-prcel vribles output correct,,, I connections 5 mrks Scheduling nd lloction one instnce of ech of,,, I registers register lloction to minimize muxes register lloction to minimize chip-enbles ltency clock period mrks Anlysis (pge 7 of )

8 ECE 7 6t (Winter) Solution to Midterm (5 Mrks) Control Circuitry (estimted time: 5 minutes) Just s nother freezing rin storm descends upon Ontrio, your mnger is clled wy to n urgent business meeting in Thiti. You hve been given the tsk of finishing the lloction nd the schemtic for the dtflow digrm shown below. NOTES:. You shll not mke ny chnges to the dtflow digrm, except to complete the lloction.. The system shll use n ASAP prcel schedule.. The vrible P shll be initilized to.. The schemtic shll include the control circuitry nd the dtpth. 5. The control circuitry shll be drwn using Boolen gtes nd flip-flops (i.e., you my not drw cloud). 6. In the schemtics, the lbel of dtpth component is used s the nme of the component s output signl. 7. In the schemtic, lbel ll signls to mtch the dtflow digrm. 8. You shll not drw the clock signl. inish the lloction Answer is in blck. P s i reset i_vlid rw the schemtic v v v v o_vlid r i r v s r r i i m v s reset CE r m s r CE r P + mrk i + mrk r nd r in cycle # + mrk r in cycle # + mrk no dditionl lloctions + mrks i vlid nd o vlid + mrks vlid-bit chin of flip flops + mrks vlid-bits re reset + mrks r initiliztion + mrks r chip-enble= in idle stte + mrks r chip-enble= in v + mrks s multiplexer - mrk ech mistke (pge 8 of )

9 ECE 7 6t (Winter) Solution to Midterm (5 Mrks) SM (estimted time: minutes) Ech of the three stte mchines on the next pge is intended to meet the system description below:. The inputs to the system re: strt, stop, nd. The output is z.. In the first clock cycle, strt nd stop re both gurnteed to be.. The counting shll begin in the clock cycle fter strt=.. The counting shll continue up to, but not including, the next clock cycle in which stop=. 5. The current vlues of strt, stop, nd shll ffect z in the next clock cycle. 6. In the clock cycle fter stop=, the output z shll be set to nd shll remin until the next sequence of counting begins. 7. The system my put constrint on the inputs such tht there is minimum gp of clock cycles between stop= nd the next strt=. Ech stte mchine my hve its own vlue for the minimum gp. The minimum gp my be s smll s clock cycles. counting sequence gp= gp=5 strt stop z z is updted ech cycle, beginning fter strt= nd stopping when stop= = hs no effect if not counting gp= strt stop z strt= hs no effect in the middle of counting sequence stop= hs no effect if not counting NOTES:. If the stte mchine is correct, nswer wht the minimum gp vlue is.. If the stte mchine is incorrect, explin either how the mchines behviour differs from the system description or how the stte mchine could be modified to fix the incorrect behviour. (pge 9 of )

10 ECE 7 6t (Winter) Solution to Midterm Answer: Incorrect. Explntion: When =, the output z is updted in the current clock cycle. It should be updted in the next clock cycle. z= z= strt S x =!strt S stop!stop! z=x z = x+ x =z b Answer: Correct. p=. Explntion: z is initilized in the first clock cycle nd when stop=. When stop=, strt is smpled in the sme clock cycle. z =!strt S!strt strt strt!stop S stop z =! z = z+ c Answer: Incorrect. Explntion (required): The input is not smpled every clock cycle during the counting sequence. z = S!strt strt S stop z = S!!stop S z =z+ (pge of )

11 ECE 7 6t (Winter) Solution to Midterm Mrking: sm is correct, student sys correct + mrks Correct +5 mrks p 5 mrks correct vlue mrks Off by one mrk Off by two sm is correct, student sys buggy 5 mrks Perceptive observtion with correct informtion mrks Significnt correct informtion mrk Some correct informtion sm is buggy, student sys buggy + mrks Buggy +5 mrks Justifiction 5 mrks Justifiction is correct nd well written. mrks Justifiction is techniclly correct, but poorly written. mrks Justifiction is lmost correct. mrks Significnt mount of correct informtion. SM is buggy, student sys correct 5 mrks p is correct vlue mrks p is off by one mrk p is off by two + mrk Answered ll three questions completely. (pge of )