Datapath&Design&Approaches. Increasing&the&Initiation&Rate
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1 atapath&esign&approaches Previous&Topic,&estimate&minimum&number&of& resources&and&then&try&to&schedule&them May&equire&Iteration,&can&ive&minimum&resource& datapath Another&approach&is&to&build&a&schedule&first& (based&on&the&specifications),&then&determine& required&resources Can&meet&latency&specification&immediately,&but& may&exceed&area&limitations Increasing&the&Initiation&ate X a0 X@1 a1 X@2 a2 X@3 a3 Y N2 N3 N4 N5 N6 N7 N8 4"Clocks" equired"if" Non3 chained The&flowgraph&below&has&a&longest&path&of&4&clocks.&&This& means&the&computations&cannot&be&completed&in&less&than& 4&clocks&(min.&latency)&because&of&data&dependencies. However,(we(CAN( increase(the( initiation(rate((rate(at( which(new(input( values(are( accepted)
2 Latency&=&4 Make&No&Assumptions&About&esources&Yet Lets&look&at&the&operations&needed&with&latency=4&for& several&clock&cycles.&& Successive&Sample&values&are&labeled&A,B,C&etc. Sample A Sample B Sample C 1 N4() N5(), Input x 2 N2(),N3(),N7() 3 N6 () 4 N8() Initiation&Period&=&2 Make&No&Assumptions&About&esources&Yet Lets&look&at&the&operations&needed&with&initiation&period&=& 2&and&latency=4&for&several&clock&cycles.&& Successive&Sample&values&are&labeled&A,B,C&etc. Sample A Sample B Sample C 1 N4() N5(), Input x 2 N2(),N3(),N7() 3 N6 () N4() N5(), Input x 4 N8() N2(),N3(),N7() 5 N6() 6 N8() 7 8
3 Initiation&Period&=&2 Lets&look&at&the&operations&needed&with&initiation&period&=& 2&for&several&clock&cycles.&&Successive&Sample&values& are&labeled&a,b,c&etc. Sample A Sample B Sample C 1 N4() N5(), Input x 2 N2(),N3(),N7() 3 N6 () N4() N5(), Input x 4 N8() N2(),N3(),N7() 5 N6() N4() N5(), Input x 6 N8() N2(),N3(),N7() 7 N6() 8 N8() esources Sample A Sample B Sample C 1 N4() N5(), Input x 2 N2(),N3(),N7() 3 N6() N4() N5(), Input x 4 N8() N2(),N3(),N7() 5 N6() N4() N5(), Input x 6 N8() N2(),N3(),N7() 7 N6() 8 N8() Two&multiplies&per&clock,&so&need&two&multipliers&(A,&B). In&Clock,&Clock&we&have&two&additions,&so&need&two& adders&(a,&b).
4 Initiation&Period&and&Latency The&initiation&period of&this&design&is&2. The latency is&4.& When&initiation&period latency,&then&system&level& pipelining is&occurring&because&the&computations&for& more&than&one&input&sample&are&being&accomplished& in&a&single&clock&period. Pipelining&implies¶llelism&(in&time)&T more&than& one&sample&computation&is&in&progress&at&any&given& clock&cycle. To&schedule,&need&to&generalize&the&table. eneralized&schedule Sample J-1: Sample J Sample J1 I-2 N4() N5(), Input X I-1 N2(),N3(),N7() I0 N6() N4() N5(), Input X I1 N8() N2(),N3(),N7() I2 N6() N4() N5(), Input X I3 N8() N2(),N3(),N7()
5 Schedule&&I0 What&do&we&need&in&egisters&at&Clock&I0? Schedule&&IT1:& or&sample J-1: N2, N3, N7 or&sample J: or&sample J1: No&operations egisters: A: B: C: : N2, : N3, :N7 Schedule&&I0: Sample&J-1: N6(N3N7) overwrite&n7 value,&no&longer&needed Sample&J: Input&x x overwrite N3 value, no&longer&needed Sample&J: N4(x@2a2) Ba2 add&new®ister to&hold N4 Sample&J: N5(x@3a3) A Aa1 overwrite&x@3 value,&no&longer&needed inished:((added(extra(egister Schedule&&I1 egisters: A: N5, B: x@2, C: x@1, : N2, : x, :N6, : N4 After&Clock,&egisters&need&to&be&setup&for&next&clock: A: x@3, B: x@2, C: x@1, : N2, : N3, :N7 Schedule&&I1: Sample&J-1: N8(N2N6) Y output&goes&to Y bus Sample&J: N2(xa0) a0 overwrite&old N2 value,&no&longer needed Important&that N2 go&into because&this&is&needed&for&next&clock&cycle. Sample&J: N3(x@1a1) Ca1 Need&=N3 for&next&clock x value&is¤tly&in.&&in&the&next&clock, x= x@1 for&sample J1, so&move x into&c register. Sample&J1: C=x@1 C J1:x@1 = J:x Sample J: N7(N4N5) A Need&N7 in& for&j1 sample Sample&J1: A=x@3 A B J1: x@3 = J:x@2 Sample&J1: B=x@2 B C J1: x@2 = J:x@1 inished:((no(extra(registers(needed
6 Schedule:&s&&I2,&I3 Schedule&for&&I2&is&repeat&of&&I0!!! Schedule&for&&I3&is&repeat&of&&I1!! Actually,&generalized&schedule&only&needs& two&clocks esource&comparison Init ate esources Multipliers Adders egisters oubling&the&initiation&rate&did¬&double&the& hardware&resources&needed.&&&why? Because&xecution&units&for&Initiation&period&=&4& were¬&fully&utilized!
7 xecution&unit&utilization Init ate xecution Unit Utilization Mult A Mult B Add A Add B 4 50% (2/4) 50 (2/4) 75% (3/4) N/A 2 100% (2/2) 100% (2/2) 100% (2/2) 50% (1/2) Note&that&multipliers&were¬&fully&utilized&for&Initiation& period&=&2, we&used&this&free&time&in&the&schedule&for&initiation& period&=&4. Init&Period&=&1 Sample A Sample B Sample C Sample 1 N4() N5(), Input x 2 N2(),N3(), N7() N4() N5(), Input x 3 N6() N2(),N3(),N7() N4() N5(), Input x 4 N8() N6() N2(),N3() N4() N5(), Input x,n7() 5 N8() N6() N2(),N3(), N7() 6 N8() N6() 7 N8() our&multiplies&in&clock&4,&so&need&four&multipliers: (A,&B,&C,&). Three&additions&in&clock&4,&so&need&three&adders:& (A,&B,&C).
8 esource&comparison&again Latency&for&all&of&these&designs&is&4&clocks. This&table&clearly&illustrates&the&time&versus&area& tradeoff&in&igital&systems. Will&cost&you&MO&resources&to&do&something&in& LSS&Time! Less&Clock&cycles,&Lower&Clock&Period Computation&Time&=&#of&Clocks Clock&Period& Throughput&=&1/(Computation&Time) Increasing&the&initiation&period&will&increase&the& computation&rate&in&terms&of&clock&cycles Less&clock&cycles&between&new&outputs To&decrease&the&clock&period&(increase&clock& frequency),&need&to&have&shorter&combinational& paths&in&the&design PIPLIN&the&individual&execution&units Multiplier&will&have&much&longer&delay&than&adder,&so&will& want&to&pipeline&this&first
9 ecall&pipelining MULTIPLI MULTIPLI two(stages MULTIPLI three(stages MULTIPLI four(stages one(stage Assume&Multiplier&with&2TStage&Pipeline Schedule&with&Initiation&Period&=&Latencyb&2&mult,&1&adder Scheduling&now&takes&6&clocks.&&&N7 depends&on&n5, N4 T can t&do&this&until&&&4&because&multiplier&result¬&ready.
10 lowgraph&annotated&with&elay& Values&(weighted&A) x a0 N2 3 clks 3 clks N3 a1 x@2 3 clks N8 Y N4 N6 a2 3 clks x@3 N7 N5 a3 Longest(path( is(now(6( clocks ecreasing&initiation&period&to&2
11 ecreasing&initiation&period&to&2 Schedule&with&Initiation&Period&=2 Schedule&with&Initiation&Period&=&Latencyb&2&mult,&2&adders Adder A Adder B MultA MultB IO I N6 (j-2) idle N5 (j) N4 (j) Input x I1 N8 (j-2) N7 (j-1) N3 (j) N2(j) I2 N6 (j-1) idle N5(j1) N4(j1) Input x I3 N8 (j-1) N7 (j) N3(j1) N3(j1) I4 N6 (j) idle N5(j2) N4(j2) Input x I5 N8 (j) N7 (j1) N3(j2) N3(j2) eneral&schedule&is&i,&i1.&&6&clocks&shown&to&complete&one&&computation.&& Initiation&Period&=&2,&&Latency&=&6.&&&&Overlapping&computations&of&three& samples.
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