ADAPTIVE EQUALIZATION AT MULTI-GHZ DATARATES

Transcription

1 ADAPTIVE EQUALIZATION AT MULTI-GHZ DATARATES Department of Electrical Engineering Indian Institute of Technology, Madras 1st February 2007

2 Outline Introduction. Approaches to electronic mitigation - ADC & Digital FIR Filter. - Analog Traveling Wave and Transversal Equalizers. Problems and prospects of analog adaptive filters. Conclusions

3 Non-Return-to-Zero (NRZ) Data Transmission bit period NRZ Pulse At 10 Gbps, 1 Bit period is 100 picoseconds

4 What is Inter-Symbol-Interference? Tx Ch 1 Ch 2

5 Why is ISI Bad? Smaller "Distance" Smaller separation, more likely to make an error

6 What is an Eye Diagram? Graphics Source : Electronic Design Magazine

7 Eye Diagram : No ISI, no noise Amplitude Time (ps)

8 Eye Diagram : No ISI, with noise Amplitude Time (ps)

9 Eye Diagram : With ISI, no noise Amplitude Time (ps)

10 Eye Diagram : With ISI, with noise Amplitude Time (ps)

11 Typical Optical Fiber Data Link Photodiode Receiver Transmitter Fiber

12 Typical Optical Fiber Data Link Photodiode Receiver Transmitter Fiber TIA Transimpedance Amplifier LA Limiting Amplifier CDR Clock/Data Recovery Data

13 Typical Optical Fiber Data Link Transimpedance Amplifier TIA Limiting Amplifier LA Clock/Data Recovery CDR Data

14 ISI in Optical Links Dispersion in fiber due to manufacturing tolerances Polarization Mode Dispersion in Single Mode Fiber Impulse Response : αδ(t) + (1 α)δ(t T d ) α is called the Power Split T d is called the Differential Group Delay (DGD) Two paths with different delays and gains Much worse (many more paths, greater spread) in multi-mode fibers

15 Example Eye : No ISI, Finite Tx Bandwidth Amplitude Time (ps)

16 PMD, Finite Tx BW, DGD = 75 ps Amplitude Time (ps)

17 PMD, Finite Tx BW, DGD = 75 ps & Noise

18 Mitigating ISI Input Channel Output 1 β y(t) y(t) - βy(t-t b ) + β 2 y(t-2t b ) 1 1 β y(t) y(t-t b ) β 1 β 1 y(t-2t b ) y(t) β βy(t-t b ) β β 2 + β 2 y(t-2t b ) β 2 β 3 1 β 3

19 Mitigating ISI : Equalization 1/T b Input Channel Output T b T b T b w 1 w 2 w 3 w 4 Output(nT b ) = k=n 1 k=0 Σ Output w k y(nt b kt b ) (1) Tapped-delay line Equalizer Weights need to be adaptive, since channel is varying (slowly) with time

20 Mitigating ISI : Equalization 1/T b Channel Filter T Input b T b T b w 1 w 2 w 3 w 4 Σ Output 4 tap" adaptive equalizer Need a filter before sampling Called the matched filter"

21 Digital Receiver : Baud Spaced Equalizer (BSE) TIA/VGA FILTER ADC 10 Gbps 6-bit Timing Phase sensitivity in a BSE High speed (10 Gbps), 6-bit ADC Digital FIR LMS ENGINE Data Example : Bell Labs (2003) - 6-bit 10 G ADC W and yields 4 effective bits in 0.18µm SiGe BiCMOS Technology (state of the art) Parallelism in the equalizer - more area

22 Digital Receiver : Baud Spaced Equalizer (BSE) 10 Gbps 6-bit Digital FIR ADC Data FILTER TIA/VGA LMS ENGINE Too much power / area ADC is a big project in itself

23 Digital Receiver : Fractionally Spaced Equalizer (FSE) 20 Gbps 6-bit Digital FIR ADC Data FILTER TIA/VGA LMS ENGINE Insensitive to timing phase High speed (20 Gbps), 6-bit ADC! Parallelism in the equalizer

24 Digital Implementation : Summary Power hungry! ADC may be doable 10Gbps Solution doesnt scale well to higher speeds (40 Gbps)

25 Analog Implementation Analog Input Channel Filter T b T b T b w 1 w 2 w 3 w 4 Σ 1/T b Output Sampling after equalization Delays implemented using transmission lines FSE 10Gbps : Each delay line is 50 ps long

26 System Model b n ε { 0, 1} Σ b n δ(t - nt) IID BIT SOURCE Tx FILTER αδ(t) + (1-α)δ(t-τ) PMD CHANNEL FIBER LOSS (β) 1/β 4th Order Butterworth + TIA & VGA + EQUALIZER AA FILTER f s OUT Offset Correct AWGN

27 System Model a n ε { 1/2, 1/2} Σ a n δ(t - nt) αδ(t) + (1-α)δ(t-τ) 4th Order Butterworth IID BIT SOURCE Tx FILTER PMD CHANNEL + EQUALIZER AA FILTER f s OUT AWGN (b) w 1 x 1 (t) IID BIT SOURCE a n ε { 1/2, 1/2} Σa n δ(t - nt) p(t) Tx Filter & Channel + n(t) x 2 (t) w 2 AA Filter v ncir v i v r(t) out w N-1 y(t) x (N-1) (t) x N (t) w N f s y(n) OUT EQUALIZER (c)

28 System Model a n ε { 1/2, 1/2} Σa n δ(t - nt) x 1 (t) w 1 IID BIT SOURCE p(t) Tx Filter & Channel + n(t) v i x N (t) f s v out y(t) y(n) OUT w N EQUALIZER

29 MMSE solution a n ε { 1/2, 1/2} Σa n δ(t - nt) IID BIT SOURCE p(t) Tx Filter & Channel + n(t) v i x 1 (t) x N (t) w 1 f s vout y(t) y(n) OUT w N EQUALIZER c i (t) = p(t) x i (t) N y(t) = w i a(k) c i (t kt ) + i=1 k= N w i n(t) x i (t) N n N y(n) = w i a(k) c i (nt kt ) + w i (n(t) x i (t)) t=nt i=1 i=1 k= i=1

30 MMSE solution y(n) = N n i=1 k= w i a(k) c i (nt kt ) + N w i (n(t) x i (t)) t=nt i=1 c 1 (0.T ) c 2 (0.T )... c N (0.T ) y(n) = a T c 1 (T ) c 2 (T )... c N (T ) (n) c 1 (L.T ) c 2 (L.T )... c N (L.T ) w 1 w 2. w N +ηt (n) w 1 w 2. w N a T (n) = [a(n) a(n 1) a(n L)] η T (n) = [ (n(t) x 1 (t)) t=nt (n(t) x 2 (t)) t=nt (n(t) x N (t)) t=nt ] Equalizer output is y(n) = a T (n)cw + η T (n)w

31 MMSE solution Equalizer output & desired outputs are y(n) = a T (n)cw + η T (n)w y d (n) = a(n δ) = a T (n) h δ The error at the output of the equalizer is e(n) = y(n) a T (n)h δ = a T (n) (Cw h δ ) + η T (n)w [ e(n) 2] [ ] = (Cw h δ ) T E a(n) T a(n) (CW h δ )+w T E E [ a(n) T a(n) ] = σ 2 a I, where σ 2 a = E[ a(n) 2 ]. [ ] η T (n)η(n) w

32 MMSE solution E [ ] η T (n)η(n) = M = N o 2 0 x 1(t)x 1 (t)dt... 0 x 1(t)x N (t)dt 0 x 2(t)x 1 (t)dt... 0 x 2(t)x N (t)dt x N(t)x 1 (t)dt... x N(t)x N (t)dt so that [ E e(n) 2] = σa 2 (Cw h δ ) T (Cw h δ ) + w T Mw 0 It can be shown that w opt = A 1 C T h δ MMSE = σa 2 h T δ (I CA 1 C T )h δ where A = C T C + M/σa 2

33 Tapped Delay Line Filters : Transversal G R T R T Z o, T Z o, T v i v 1 v 2 v 3 w 1 w 2 w 3 v g i v out R T /2 i = gv Delay Elements are passive Tap weights : variable gain amplifiers (Differential pair) Summation : Kirchoffs Current Law

34 Choices for On-chip Delay Lines : Microstrip Wideband Need 50 ps delay Velocity of light 150 µm/ps 50 ps 7.5 mm! (and we need several of them) Conclusion : No good What can we do to make the delay line smaller?

35 Spiral Delay Lines Metal 1 Metal 5 Spiral : reduces size Use metal interconnect layers Mutual coupling results in increased inductance

36 Spiral Delay Lines Metal 1 Metal 5 Ground plane is broken to avoid image currents Attempt to distribute capacitance uniformly across the inductor Typical size - 300µm on a side Accurate model through EM Simulations

37 Tunable Weights om op Vdd Sign S Q5,6 S Q7,8 S Vdd ip Q1 Q4 im Q2 Q3 Magnitude Example of a tunable tap weight implementation

38 Problems with Transversal Filters G R T Z o, T Z o, T R T v i v 1 v+ v+(t-2t) 1 >> Γ Τ >> Γ 2 Τ... h v1 (t) 1 Γ T v+(t-4t) Γ T v+(t-2t) Exponential tails due to series losses Components due to reflection Γ T Equalizer Span t/t Mistermination & Loss in the delay lines Tap responses have components outside equalizer span ISI" within the equalizer! Degrades performance

39 Problems with Transversal Filters Normalized Filter Output time (ps) Eye diagram at the first tap output

40 Traveling Wave Amplifier (TWA) FIR Filter G R T Z o, T/2 Z o, T/2 R T v i v 1 v 2 v 3 w 1 w 2 w 3 Z o, T/2 Z o, T/2 v g i v out R T R T i = gv

41 Traveling Wave Amplifier (TWA) FIR Filter v i G R T Z o, T/2 Z o, T/2 R T v 1 v 2 v 3 h v1 (t) k 1 Γ T k=gz o (1+Γ Τ )/ t/t v out w 1 w 2 w 3 Z o, T/2 Z o, T/2 h w1 (t) 1 k1 k1=k 2 /G 2Γ T t/t R T R T

42 TWA FIR Filters : Comments Improvement over a transversal filter Robust with mistermination and series loss Used in several commerical equalizer ICs Two doubly terminated lines - Tap weights need to be larger by a factor of 2

43 Traveling Wave versus Transversal Equalizers NRZ response (V) 0.3 Tap 1 (a) Tap t / T b NRZ response (V) Tap 1 Tap 10 (b) t / T b

44 Traveling Wave versus Transversal Equalizers Equalizer Output Receiver Input e Receiver Input time (ps) MSE = time (ps) 10 Tap Transversal Equalizer Equalizer Input Equalizer Output Equalizer Input time (ps) MSE = time (ps) 10 Tap TW Equalizer

45 Summary-1 TWA FIR Filters represent the state-of-the-art in high speed equalization Signal attenuation due to double termination Need for an anti-alias" filter Delay cells are large and occupy space Example : A fully differential 10 tap TWA equalizer has 36 inductors! (each being about 300µm on a side Capacitive loading of lines reduces cut-off frequency of the delay lines TWA filters are not amenable to LMS adaptation

46 Summary-2 DFE used alongwith an FFE in tough channels - e.g. multimode channels. Timing recovery is an important issue. In simple channels, common to use an upfront timing recovery module that works with the receiver input. In more complicated channels, the FFE output can be used to derive the timing error. Joint timing recovery/equalization without a training sequence is a challenge.

47 Conclusions High speed equalization at multi-ghz datarates involves signal processing, circuit design and electromagnetics. The challenge is to implement well known signal processing techniques at such high data rates. Many problems to be solved - e.g. efficient LMS implementation at several GHz speeds. Lots of work to do!

48 Selected References Wu et. al, Integrated transversal equalizers in high-speed fiber-optic systems, IEEE JSSC, December Sewter et. al, A 3-tap FIR filter with cascaded distributed tap amplifiers for equalization up to 40 Gb/s, IEEE JSSC, August Pavan et. al, Nonidealities in Traveling Wave and Transversal FIR Filters Operating at Microwave Frequencies, IEEE TCAS-1, January 2006.