2/3/4/5-Phase PWM Controller for High-Density Power Supply. Features. VTT/EN VR_Ready FBRTN FB COMP SS QRSEL VR_FAN VR_HOT TSEN

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1 2/3/4/5Phase PWM Controller for HighDensity Power Supply General Description The RT8802A is a 2/3/4/5phase synchronous buck controller specifically designed to power Intel / AMD next generation microprocessors. It implements an internal 8bit DAC that is identified by VID code of microprocessor directly. RT8802A generates VID table that conform to Intel VRD10.x and VRD11 core power with 6.25mV increments and 0.5% accuracy. RT8802A adopts innovative timesharing DCR current sensing technique to sense phase currents for phase current balance, load line setting and over current protection. Using a common GM to sense all phase currents eliminates offset and linearity variation between GMs in conventional current sensing methods. As submilliohmgrade inductors are widely used in modern motherboards, slight offset and linearity mismatch will cause considerable current shift between phases. This technique ensures good current balance in mass production. Other features include over current protection, programmable soft start, over voltage protection, and output offset setting. RT8802A comes to a small footprint package with VQFN40L 6x6. Ordering Information RT8802A Note : Richtek products are : Package Type QV : VQFN40L 6x6 (VType) Lead Plating System P : Pb Free Z : ECO (Ecological Element with Halogen Free and Pb free) RoHS compliant and compatible with the current requirements of IPC/JEDEC JSTD020. Suitable for use in SnPb or Pbfree soldering processes. Features 5V Power Supply 2/3/4/5Phase Power Conversion with Automatic Phase Selection 8bit VID Interface, Supporting Intel VRD11/VRD10.x and AMD K8, K8_M2 CPUs VR_HOT and VR_FAN Indication Precision Core Voltage Regulation Power Stage Thermal Balance by DCR Current Sensing Adjustable Softstart Over Voltage Protection Adjustable Frequency and Typical at 300kHz per Phase Power Good Indication 40Lead VQFN Package RoHS Compliant and 100% Lead (Pb)Free Applications Intel /AMD New generation microprocessor for Desktop PC and Motherboard Low Output Voltage, High power density DC/DC Converters Voltage Regulator Modules Pin Configurations VTT/EN VR_Ready FBRTN FB COMP SS QRSEL VR_FAN VR_HOT TSEN (TOP VIEW) PWM5 PWM4 PWM3 PWM2 PWM1 ISP1 ISP2 ISP3 ISP4 ISP5 IOUT DVD RT OFS ADJ TCOC IMA ISN1 ISN24 ISN35 VID_SEL VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VDD GND VQFN40L 6x6 1

2 Marking Information RT8802APQV RT8802A PQV YMDNN RT8802APQV : Product Number YMDNN : Date Code RT8802AZQV RT8802A ZQV YMDNN RT8802AZQV : Product Number YMDNN : Date Code 2

3 Typical Application Circuit R15 12k C7 C9 5.6pF 470pF C5 56nF R16 R17 0 CPU_VCC BT_5V R VCORE35 VCORE24 VCORE1 R29 R28 NC NC C10 C11 C12 C13 1µF 1µF 1µF 1µF R30 R31 R32 R BT_12V R34 10 C14 0.1µF BT_12V R36 10 C21 0.1µF BT_12V R38 10 C27 0.1µF BT_12V R40 10 C34 0.1µF VIN BT_12V C15 C16 C17 C µF 4.7µF 4.7µF 4.7µF 1N4148 NC VCC PWM BOOT UGATE PHASE RT9619 LGATE PGND C19 1µ F IPD09N03LA IPS06N03LA Q1 Q2 Q3 Q4 VIN C22 C23 C24 C µF 4.7µF 4.7µF 4.7µF 1N4148 NC VCC VIN BOOT UGATE PHASE RT9619 LGATE PGND C26 1µ F IPD09N03LA IPS06N03LA Q5 Q6 Q7 Q8 VIN C28 C29 C30 C µF 4.7µF 4.7µF 4.7µF 1N4148 NC VCC VIN 1 BOOT UGATE PHASE RT9619 LGATE PGND C32 1µF IPD09N03LA IPS06N03LA Q9 Q10 Q11 Q12 VIN C35 C36 C37 C µF 4.7µF 4.7µF 4.7µF 1N4148 NC VCC VIN 1 BOOT UGATE PHASE RT9619 LGATE PGND C39 1µF IPD09N03LA IPS06N03LA Q13 Q14 Q15 Q16 R C20 3.3nF R C27 3.3nF R C33 3.3nF R C40 3.3nF R43 NTC L1 VCORE1 VCC VSS VCORE24 R20 L2 R18 C8 R19 C41 to C50 560µF x 10 C6 C4 C51 to C68 10µF x 18 15k 2.2nF 1.5k R14 VCORE35 L3 VCORE24 For AMD L4 BT_5V RT k NTC 15 RT2 4.3k FB 100k PWM3 PWM4 PWM2 PWM1 COMP SS TCOC IMA RT ADJ For Intel VID_SEL k PWM5 470 ISN35 ISN24 RT8802A 100k 470 R21 R22 R23 R24 R25 R26 GND VID0 VID1 VID2 VID3 VID4 VID5 VID6 ISN1 ISP1 ISP2 ISP3 ISP4 ISP5 VID_SEL VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 For K8 VDDIO For K8_M GND VID7 VDD DVD 10 TSEN IOUT QRSEL OFS FBRTN VR_Ready VR_FAN VR_HOT VTT/EN R1 BT_5V BT_5V R42 C1 0.1uF k R2 BT_12V C3 R7 R8 9.52k 0.1µF C69 NC R3 1.1k Enable R13 NC R4 R5 R6 BT_5V 10k 10k 10k R9 For Intel VTT PGOOD R10 NC BT_5V R11 NC 0 For AMD VDDIO R12 CPU_VSS 3

4 Functional Pin Description VTT/EN (Pin 1) The pin is defined as the chip enable, and the VTT is applied for internal VID pull high power and power sequence monitoring. VR_Ready (Pin 2) Power good opendrain output. FBRTN (Pin 3) Feedback return pin. VID DAC and error amplifier reference for remote sensing of the output voltage. FB (Pin 4) Inverting input pin of the internal error amplifier. COMP (Pin 5) Output pin of the error amplifier and input pin of the PWM comparator. SS (Pin 6) Connect this SS pin to GND with a capacitor to set the softstart time interval. QRSEL (Pin 7) Quick response mode select pin. When QRSEL = GND and quick response is triggered during heavy load to light load transient, 2 channels will turn on simultaneously to prevent V OUT undershoot. When QRSEL = NC and quick response is triggered, all channels will turn on simultaneously to prevent V OUT undershoot. VR_FAN (Pin 8) The pin is defined to signal VR thermal information for external VR thermal dissipation scheme triggering. VR_HOT (Pin 9) The pin is defined to signal VR thermal information for external VR thermal dissipation scheme triggering. TSEN (Pin 10) Temperature detect pin for VR_HOT and VR_FAN. IOUT (Pin 11) Output current indication pin. The current through IOUT pin is proportional to the total output current. DVD (Pin 12) Programmable power UVLO detection input. Trip threshold is 1V at V DVD rising. RT (Pin 13) The pin is defined to set internal switching operation frequency. Connect this pin to GND with a resistor R RT to set the frequency F SW. F e SW = RRT OFS (Pin 14) The pin is defined for load line offset setting. ADJ (Pin 15) Current sense output for active droop adjusting. Connect a resistor from this pin to GND to set the load droop. TCOC (Pin 16) Input pin for setting thermally compensated over current trigger point. Voltage on the pin is compared with V ADJ. If V ADJ > V TCOC then OCP is triggered. IMA (Pin 17) The pin is defined to set threshold of over current. ISN1 (Pin 18) Current sense negative input pin for channel 1 current sensing. ISN24 (Pin 19) Current sense negative input pins for channel 2 and channel 4 current sensing. ISN35 (Pin 20) Current sense negative input pins for channel 3 and channel 5 current sensing. 4

5 ISP1 (Pin 25), ISP2 (Pin 24), ISP3 (Pin 23), ISP4 (Pin 22), ISP5 (Pin 21) Current sense positive input pins for individual converter channel current sensing. PWM1 (Pin 26), PWM2 (Pin 27), PWM3 (Pin 28), PWM4 (Pin 29), PWM5 (Pin 30) PWM outputs for each driven channel. Connect these pins to the PWM input of the MOSFET driver. For systems which using 2/3/4 channels, pull PWM 3/4/5 pins up to high. VDD (Pin 31) IC power supply. Connect this pin to a 5V supply. Function Block Diagram VID7 (Pin 32), VID6 (Pin 33), VID5 (Pin 34), VID4 (Pin 35), VID3 (Pin 36), VID2 (Pin 37), VID1 (Pin 38), VID0 (Pin 39), VID_SEL (40) DAC voltage identification inputs for VRD10.x / VRD11 / K8 / K8_M2. These pins are internally pulled up to VTT. VIDSEL VID [7] Table VTT VR11 GND VR10.x VDD NC K8 VDD GND K8_M2 GND [Exposed pad (41)] The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. VDD VTT/EN DVD SS VR_Ready COMP Soft Start & PGOOD Power On Reset Oscillator & Ramp Generator RT FB OFS VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID_SEL FBRTN TSEN VR_FAN VR_HOT DAC Temperature Processing Clamp EA Droop Tune & HiI Detection Current Processing SUM/N & OCP Detection Sample & Hold Mux Pulse Width Modulator & Output Buffer CSA Mux Mux PWM1 PWM2 PWM3 PWM4 PWM5 IMA ISN1 ISN24 ISN35 ISP1 ISP2 ISP3 ISP4 ISP5 TCOC ADJ IOUT GND 5

6 Table 1. Output Voltage Program (VRD10.x VID6) Pin Name Nominal Output Voltage DACOUT VID4 VID3 VID2 VID1 VID0 VID5 VID V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V To be continued 6

7 Table 1. Output Voltage Program (VRD10.x VID6) Pin Name Nominal Output Voltage DACOUT VID4 VID3 VID2 VID1 VID0 VID5 VID V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V ,15625V V V V V V V To be continued 7

8 Table 1. Output Voltage Program (VRD10.x VID6) Pin Name Nominal Output Voltage DACOUT VID4 VID3 VID2 VID1 VID0 VID5 VID V V V V OFF OFF OFF OFF V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V To be continued 8

9 Table 1. Output Voltage Program (VRD10.x VID6) Pin Name Nominal Output Voltage DACOUT VID4 VID3 VID2 VID1 VID0 VID5 VID V V V V V V V V V V V 9

10 Table 2. Output Voltage Program (VRD11) Pin Name HE Nominal Output Voltage DACOUT 00 OFF 01 OFF V V V V V V V V 0A V 0B V 0C V 0D V 0E V 0F V V V V V V V V V V V 1A V 1B V 1C V 1D V 1E V 1F V V V V V V V V Pin Name HE Nominal Output Voltage DACOUT V V V 2A V 2B V 2C V 2D V 2E V 2F V V V V V V V V V V V 3A V 3B V 3C V 3D V 3E V 3F V V V V V V V V V V V 4A V 4B V 4C V 4D V 10 To be continued

11 Table 2. Output Voltage Program (VRD11) Pin Name HE Nominal Output Voltage DACOUT 4E V 4F V V V V V V V V V V V 5A V 5B V 5C V 5D V 5E V 5F V V V V V V V V V V V 6A V 6B V 6C V 6D V 6E V 6F V V V V V V Pin Name HE Nominal Output Voltage DACOUT V V V V V 7A V 7B V 7C V 7D V 7E V 7F V V V V V V V V V V V 8A V 8B V 8C V 8D V 8E V 8F V V V V V V V V V V V 9A V 9B V To be continued 11

12 Table 2. Output Voltage Program (VRD11) Pin Name HE Nominal Output Voltage DACOUT 9C V 9D V 9E V 9F V A V A V A V A V A V A V A V A V A V A V AA V AB V AC V AD V AE V AF V B V B V B V B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 Pin Name HE C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 Nominal Output Voltage DACOUT 12 To be continued

13 Table 2. Output Voltage Program (VRD11) Pin Name HE EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Nominal Output Voltage DACOUT OFF OFF Note: (1) 0 : Connected to GND (2) 1 : Open (3) : Don't Care 13

14 Table 3. Output Voltage Program (K8) VID4 VID3 VID2 VID1 VID0 Nominal Output Voltage DACOUT Shutdown Note: (1) 0 : Connected to GND (2) 1 : Open 14

15 Table 4. Output Voltage Program (K8_M2) Pin Name VID5 VID4 VID3 VID2 VID1 VID0 Nominal Output Voltage DACOUT To be continued 15

16 Table 4. Output Voltage Program (K8_M2) Pin Name VID5 VID4 VID3 VID2 VID1 VID0 Nominal Output Voltage DACOUT Note: (1) 0 : Connected to GND (2) 1 : Open (3) The voltage above are load independent for desktop and server platforms. For mobile platforms the voltage above correspond to zero load current. 16

17 Absolute Maximum Ratings (Note 1) RT8802A Supply Voltage, V DD 7V Input, Output or I/O Voltage (GND 0.3V) to (V DD 0.3V) Power Dissipation, P T A = 25 C VQFN 40L 6x W Package Thermal Resistance (Note 2) VQFN40L 6x6, θ JA 35 C/W Junction Temperature 150 C Lead Temperature (Soldering, 10 sec.) 260 C Storage Temperature Range 65 C to 150 C ESD Susceptibility (Note 3) HBM (Human Body Mode) 2kV MM (Machine Mode) 200V Recommended Operating Conditions (Note 4) Supply Voltage, V DD 5V ± 10% Junction Temperature Range 40 C to 125 C Ambient Temperature Range 40 C to 85 C Electrical Characteristics (VDD = 5V, TA = 25 C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Supply Current V DD Nominal Supply Current I DD PWM 1, 2, 3, 4, 5 Open ma VID Change Current I SS VR_RDY = High ma Power On Reset POR Threshold V DDRTH V DD Rising V Hysteresis V DDHYS V V DVD Threshold Trip (Low to High) V DVDTH Enable V Hysteresis V DVDHYS 60 mv V TT Threshold Trip (Low to High) V TTTH Enable Hysteresis V TTHYS 0.1 V Oscillator Free Running Frequency f OSC R RT = 20kΩ khz Frequency Adjustable Range f OSC_ADJ khz Ramp Amplitude ΔV OSC R RT = 20kΩ 1.9 V Ramp Valley V RV V To be continued 17

18 Parameter Symbol Test Conditions Min Typ Max Unit Maximum OnTime of Each Four Phase % Channel Operation RT Pin Voltage V RT R RT = 20kΩ V Maximum OnTime 1 3 μs Reference and DAC DACOUT Voltage Accuracy ΔV DAC V DAC 1V % 1V V DAC 0.8V 5 5 mv V DAC < 0.8V 8 8 mv DAC (VID0VID125) Input Low V ILDAC 1/2V TT 0.2 V DAC (VID0VID125) Input High V IHDAC 1/2V TT 0.2 V V ID Pullup Resistance kω OFS Pin Voltage V OFS R OFS = 100kΩ V Error Amplifier DC Gain 65 db GainBandwidth Product GBW 10 MHz Slew Rate SR COMP = 10pF 8 V/μs Maximum Current I EA_SLEW 50 μa Current Sense GM Amplifier CSN Full Scale Source Current I ISPFSS 100 μa CSN Current for OCP 150 μa Input Offset Voltage V OSCS mv Protection Over Voltage Trip (FBDACOUT) ΔOVT mv Over Voltage Delay Time 20 μs IMA Voltage V IMA R IMA = 20kΩ V Power Good Output Low Voltage V PGOODL I PGOOD = 4mA 0.2 V Thermal Management VR_HOT Threshold Level %VCC5 VR_HOT Hysteresis 5 %VCC5 Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θja is measured in the natural convection at TA = 25 C on the four layers high effective thermal conductivity test board of JEDEC 517 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution recommended. Note 4. The device is not guaranteed to function outside its operating conditions. 18

19 Typical Operating Characteristics 700 Frequency vs. R RT 450 GM Frequency (khz) Positive Duty (ns) PHASE 3 PHASE 1 PHASE 2 PHASE 4 PHASE R RT (k (kω)) ISN (μa) Output Voltage vs. Temperature 322 Frequency vs. Temperature Output Voltage (V) Frequency (khz) Temperature ( C) Temperature ( C) Power On from DVD Power Off from DVD DVD DVD SS VOUT PHASE 3 (10V/Div) SS V OUT PHASE 3 (10V/Div) Time (1ms/Div) Time (1μs/Div) 19

20 Power On from VCC12 Power Off from VCC12 VCC12 (10V/Div) SS VOUT PHASE 3 (10V/Div) VCC12 (10V/Div) SS VOUT PHASE 3 (10V/Div) Time (1ms/Div) Time (1ms/Div) Power On from VCC5 Power Off from VCC5 VCC5 (5V/Div) SS V OUT PHASE 3 (10V/Div) VCC5 (5V/Div) SS V OUT PHASE 3 (10V/Div) Time (1ms/Div) Time (25ms/Div) VR_Ready SS (2V/Div) VOUT 1V/Div) PWM (5V/Div) Power On with OCP VR_Ready SS (2V/Div) V OUT PWM (5V/Div) Output Short Circuit Time (500μs/Div) Time (1ms/Div) 20

21 V OUT Droop V OUT Overshoot V OUT (20mV/Div) V OUT (20mV/Div) I OUT (40A/Div) I OUT (40A/Div) Time (2μs/Div) Time (2μs/Div) Dynamic VID Dynamic VID V OUT (200mV/Div) VOUT (200mV/Div) VID0 (500mV/Div) VID0 (500mV/Div) Time (50μs/Div) Time (50μs/Div) OVP VR_Ready SS (2V/Div) FB PWM (5V/Div) Time (10μs/Div) 21

22 Applications Information RT8802A is a multiphase DC/DC controller specifically designed to deliver high quality power for next generation CPU. RT8802A controls a special power on sequence & monitors the thermal condition of VR module to meet the VRD11 requirement. Phase currents are sensed by innovative timesharing DCR current sensing technique for channel current balance, droop tuning, and over current protection. Using one common GM amplifier for current sensing eliminates offset errors and linearity variation between GMs. As submilliohmgrade inductors are widely used in modern mother boards, slight mismatch of GM amplifiers offset and linearity results in considerable current shift between phases. The timesharing DCR current sensing technique is extremely important to guarantee phase current balance in mass production. Converter Initialization, Phase Selection, and Power Good Function The RT8802A initiates only after 3 pins are ready: VDD pin power on reset (POR), VTT/EN pin enabled, and DVD pin is higher than 1V. VDD POR is to make sure RT8802A is powered by a voltage for normal work. The rising threshold voltage of VDD POR is 4.2V typically. At VDD POR, RT8802A checks PWM3, PWM4 and PWM5 status to determine phase number of operation. Pull high PWM3 for twophase operation; pull high PWM4 for three phase operation; pull high PWM5 for fourphase operation. The unused current sense pins should be connected to GND or left floating. VTT/EN acts as a chip enable pin and receives signal from FSB or other power management IC. DVD is to make sure that AT12V is ready for drivers to work normally. Connect a voltage divider from AT12V to DVD pin as shown in the Typical Application Circuit. Make sure that DVD pin voltage is below its threshold voltage before drivers are ready and above its threshold voltage for minimum AT12V during normal operation. with Intel VRD11 specification as shown in Figure 1. A time variant internal current source charges the capacitor connected to SS pin. SS voltage ramps up piecewise linearly and locks VID_DAC output with a specified voltage drop. Consequently, V CORE is built up according to VID_DAC output and meet Intel VRD11 requirement. VR_READY output is pulled high by external resistor when V CORE reaches VID_DAC output with 1~2ms delay. An SS capacitor about 47nF is recommend for VRD11 compliance. VDD POR, DVD, and VTT/EN ready SS V CORE 1.1V VR_Ready VID on the fly 1~2ms 1~2ms 1~2ms 1~2ms 1~2ms Figure 1. Timing Diagram During Soft Start Interval Voltage Control CPU V CORE voltage is Kelvin sensed by FB and FBRTN pins and precisely regulated to VID_DAC output by internal high gain Error Amplifier (EA). The sensed signal is also used for power good and over voltage function. The typical OVP trip point is 170mV above VID_DAC output. RT8802A pulls PWM outputs low and latches up upon OVP trip to prevent damaging the CPU. It can only restart by resetting one of VDD, DVD, or VTT/EN pin. RT8802A supports Intel VRD10.x, VRD11, AMD K8 and AMD K8_M2 VID specification. The change of VID_DAC output at VID on the fly is also smoothed by capacitor connected to SS pin. Consequently, Vcore shifts to its new position smoothly as shown in Figure 2. If any one of VDD, VTT/EN, and DVD is not ready, RT8802A keeps its PWM outputs high impedance and the companion drivers turn off both upper and lower MOSFETs. After VDD, VTT/EN, and DVD are ready, RT8802A initiates its soft start cycle that is compliant 22

23 PWM4 V CORE VID7 Figure 2. Vcore Response at VID on the Fly DCR Current Sensing RT8802A adopts an innovative timesharing DCR current sensing technique to sense the phase currents for phase current balance (phase thermal balance) and load line regulation as shown in Figure 3. Current sensing amplifier GM samples and holds voltages VCx across the current sensing capacitor Cx by turns in a switching cycle. According to the Basic Circuit Theory, if Lx DCRx = Rx Cx then VCx = I L DCRx Consequently, the sensing current I is proportional to inductor current I L and is expressed as : IL DCRx I = RCSN The sensed current I is used for current balance and droop tuning as described as followed. Since all phases share one common GM, GM offset and linearity variation effect is eliminated in practical applications. As submilliohmgrade inductors are widely used in modern mother boards, slight mismatch of GM amplifiers offset and linearity results in considerable current shift between phases. The time sharing DCR current sensing technical is extremely important to guarantee phase current balance in mass production. Phase Current Balance The sampled and held phase current I are summed and averaged to get the averaged current I. Each phase current I then is compared with the averaged current. The difference between I and I is injected to corresponding PWM comparator. If phase current I is smaller than the averaged current, RT8802A increases the duty cycle of corresponding phase to increase the phase current accordingly and vice versa. T1 T2 L1 DCR1 T3 T4 I = I L x DCR /R CSN I S/H CKT CSA CSA: Current Sense Amplifier T1 T3 T1 T3 ISP1 ISN1 ISP3 ISN35 R1 R CSN1 C1 VC1 R CSN3 L3 R3 DCR3 C3 VC3 L2 DCR2 T2 T4 T2 or T4 ISP2 ISN24 ISP4 R2 R CSN24 C2 VC2 L4 R4 DCR4 C4 VC4 Figure 3 23

24 Output Voltage Offset Function To meet Intel requirement of initial offset of load line, RT8802A provides programmable initial offset function. External resistor R OFS and voltage source at OFS pin VOFS generate offset current I OFS = ROFS, where V OFS is 1V typical. One quarter of I OFS flows through R FB1 as shown in Figure 4. Error amplifier would hold the inverting pin equal to V DAC V ADJ. Thus output voltage is subtracted from V DAC V ADJ for a constant offset voltage. RFB1 VCORE = VDAC VADJ 4 ROFS A positive output voltage offset is possible by connecting R OFS to VDD instead of to GND. Please note that when R OFS is connected to VDD, V OFS is V DD 2V typically and half of I OFS flows through R FB1. V CORE is rewritten as : Current Ratio Setting Current ratio adjustment is possible as described below. It is important for achieving thermal balance in practical application where thermal conditions between phases are not identical. Figure 5 shows the application circuit of GM for current ratio requirement. According to Basic Circuit Theory Figure 4. Load Line and Offset Function R V FB1 CORE = VDAC VADJ ROFS VCx = V CORE DAC R FB1 RP Rx RP I SRx RP Cx 1 Rx R P I OFS 4 EA V ADJ L R ADJ DCRx COMP 4I If L = (R//RP ) Cx then DCRx RP VCx = IL DCRx Rx RP With other phase kept unchanged, this phase would share (R P Rx) / R P times current than other phases. Figure 6 and 7 show different current ratio setting for the power stage when Phase 4 is programmed 2 times current than other phases. Figure 8 and 9 compare the above current ratio setting results. T Rx L DCRx I L VCx Cx R P I L4 Figure 5 1.5uH 3k Figure 6. GM4 Setting for current ratio function I L1~3 1.5uH 1.5k 1mΩ 1µF V OUT Figure 7. GM1~3 Setting for current ratio function 3k 1mΩ 1µF 24

25 35 Current Ratio Function 1.31 Load Line without dead zone at light loads IL w/o Dead Zone Compensation RCSN open IL (A) IL3 IL2 IL1 VCORE (V) RCSN2 = 82k w/i Dead Zone Compensation I OUT (A) Figure I OUT (A) Figure Current Balance Function I L Lx DCRx Rx Cx VCx V OUT IL (A) IL3 IL2 GMx R CSN 10 IL1 5 IL I OUT (A) Figure 9 Dead Zone Elimination RT8802A samples and holds inductor current at 50% period by timesharing sourcing a current I to R CSN. At light load condition when inductor current is not balance, voltage VCx across the sensing capacitor would be negative. It needs a negative I to sense the voltage. However, RT8802A CANNOT provide a negative I and consequently cannot sense negative inductor current. This results in dead zone of load line performance as shown in Figure 10. Therefore a technique as shown in Figure 11 is required to eliminate the dead zone of load line at light load condition. Ix R CSN2 Figure 11. Application circuit of GM Referring to Figure 11, I is expressed as : VOUT IL_50% DCRx IL_50% DCRx I = RCSN2 RCSN2 RCSN where I L_50% is the of inductor current at 50% period. To make sure RT8802A could sense the inductor current, right hand side of Equation (1) should always be positive: VOUT IL_50% DCRx IL_50% DCRx 0 (2) RCSN2 RCSN2 RCSN Since R CSN >> DCRx in practical application, Equation (2) could be simplified as : V OUT IL_50% DCRx RCSN2 RCSN (1) 25

26 For example, assuming the negative inductor current is I L_50% = 5A at no load, then for R CSN 330Ω, R ADJ = 160Ω, V OUT = 1.300V 1.3V RCSN2 R CSN2 85.8kΩ 5A 1mΩ 330Ω If R ADJ is connected as in Figure 14, R ADJ = R1 (R2// R NTC ), which is a negative temperature correlated resistance. By properly selecting R1 and R2, the positive temperature coefficient of DCR can be canceled by the negative temperature coefficient of R ADJ. Thus the load line will be thermally compensated. ADJ Choose R CSN2 = 82kΩ Figure 10 shows that dead zone of load line at light load is eliminated by applying this technique. R1 R ADJ VR_HOT & VR_FAN Setting R NTC R2 V CC 5V Figure 14. R ADJ Connection for Thermal Compensation V TSEN R1 R NTC TSEN 0.39 x V CC 0.33 x V CC 0.28 x V CC CMP CMP CMP Q1 Q2 Q3 Over Current Protection Thermally compensated total current OCP V TCOC is compared with V ADJ. If V ADJ > V TCOC then OCP is triggered. ADJ Figure 12 IMA(1V) V TSEN 0.39 x V CC 0.33 x V CC 0.28 x V CC V TSEN is inversely proportional to Temperature. R1 R2 TCOC CMP Figure 15 OC VR_FAN VR_HOT Temperature Figure 13. VR_HOT and VR_FAN Signal vs TSEN Voltage Load Line Setting and Thermal Compensation V ADJ = Sum(I ) x R ADJ = (DCR x R ADJ / R CSN ) x I OUT = LL x I OUT V OUT = V DAC V ADJ = V DAC LL x I OUT LL = DCR(PTC) x R ADJ (NTC) / R CSN DCR is the inductor DCR which is a PTC resistance. Phase Current OCP RT8802A uses an external resistor R IMA connected to IMA pin to generate a reference current I IMA for over current protection : V I IMA IMA = RIMA where V IMA is typical 1.0V. OCP comparator compares each sensed phase current I with this reference current as shown in Figure 16. Equivalently, the maximum phase current I L(MA) is calculated as below : (MA) (MA) L(MA) = 1 I 2 V = 3 I = R R 3 V = I = DCR 2 R 26 1 I 3 I I IMA IMA CSN IMA IMA IMA IMA R R CSN L

27 OCP Comparator 1/3 I 1/2 I IMA Figure 16. Over Current Comparator VFB EA Rising Slew Rate Phase current OCP and total current OCP with thermal compensation I 1 I OC, Phase I 2 I OC, Phase I 3 I OC, Phase I 4 I OC, Phase Vcomparator Vcomparator Vcomparator Vcomparator Thermal compensated OCP Reset while VID changing I (n) I L(n) H Pulse width detector H Last 20us? Y = 1, N = 0 H Pulse width detector H Last 20us? Y = 1, N = 0 Short circuit protection Over current protection OCP V COMP Time (250ns/Div) Figure 19. EA Falling Transient with 10pF Loading ; Slew Rate = 8V/μs 4.7k CH1:(500mV/Div) CH2:(2V/Div) Figure 17 Error Amplifier Characteristic For fast response of converter to meet stringent output current transient response, RT8802A provides large slew rate capability and high gainbandwidth performance. EA Falling Slew Rate VFB B 4.7k EA V REF Figure 20. GainBandwidth Measurement by signal A divided by signal B Design Procedure Suggestion a. Output filter pole and zero (Inductor, output capacitor value & ESR). b. Error amplifier compensation & sawtooth wave amplitude (compensation network). A c. Kelvin sense for V CORE. V COMP CH1:(500mV/Div) CH2:(2V/Div) Time (250ns/Div) Current Loop Setting a. GM amplifier S/H current (current sense component DCR, ISP and ISN pin external resistor value). b. Over current protection trip point (R IMA resistor). Figure 18. EA Rising Transient with 10pF Loading ; Slew Rate = 10V/μs VRM Load Line Setting a. Droop amplitude (ADJ pin resistor). b. No load offset (R CSN ) c. DAC offset voltage setting (OFS pin & compensation network resistor). 27

28 d. Temperature coefficient compensation(tsen external resister & thermistor, resistor between ADJ and GND.) Power Sequence & SS DVD pin external resistor and SS pin capacitor. PCB Layout a. Kelvin sense for current sense GM amplifier input. b. Refer to layout guide for other items. 28

29 Outline Dimension D D2 SEE DETAIL A 1 L E E2 e b A A1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A A A b D D E E e L VType 40L QFN 6x6 Package Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863) Fax: (8863) Richtek Technology Corporation Taipei Office (Marketing) 5F, No. 95, Minchiuan Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862) Fax: (8862) marketing@richtek.com Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. 29