Programming with SIMD Instructions
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1 Programming with SIMD Instructions Debrup Chakraborty Computer Science Department, Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional México D.F., México. debrup@cs.cinvestav.mx November 13, 2014
2 Flynn s Taxonomy A classification of computer architectures by Michael J. Flynn, Single Instruction Multiple Instruction Single Data SISD MISD Multiple Data SIMD MIMD Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del Instituto Politécnico November 13, Nacional 2014 México 2 / 26 D.F.,
3 SISD Single Instruction Multiple Instruction Single Data SISD MISD Multiple Data SIMD MIMD One instruction operating on one data in the same time (traditional sequential processing). Flynn includes pipelined architectures also in this category. Intel processors < 1996 and AMD < 1998 Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del Instituto Politécnico November 13, Nacional 2014 México 3 / 26 D.F.,
4 MISD Single Instruction Multiple Instruction Single Data SISD MISD Multiple Data SIMD MIMD Executes different instructions on the same data at the same time. This is not common. Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del Instituto Politécnico November 13, Nacional 2014 México 4 / 26 D.F.,
5 SIMD Single Instruction Multiple Instruction Single Data SISD MISD Multiple Data SIMD MIMD Execute the same instruction on multiple data at the same time. First Intel processor: Intel Pentium MMX (1996), MMX instructions First AMD processor : AMD K6-2 (1998), 3DNow! instructions Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del Instituto Politécnico November 13, Nacional 2014 México 5 / 26 D.F.,
6 MIMD Single Instruction Multiple Instruction Single Data SISD MISD Multiple Data SIMD MIMD Executes asynchronously distinct instructions on distinct data. Multiprocessor architectures, clusters etc. Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del Instituto Politécnico November 13, Nacional 2014 México 6 / 26 D.F.,
7 A Brief History of Intel Processors Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del Instituto Politécnico November 13, Nacional 2014 México 7 / 26 D.F.,
8 A Brief History of Intel Processors Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del Instituto Politécnico November 13, Nacional 2014 México 8 / 26 D.F.,
9 A Brief History of Intel Processors Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del Instituto Politécnico November 13, Nacional 2014 México 9 / 26 D.F.,
10 Time line for SIMD Instruction sets Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del InstitutoNovember Politécnico13, Nacional 2014 México 10 / 26 D.F.,
11 Intel SIMD Instruction Sets MMX instructions: Multimedia extentions. 8 registers of 64 bits. SSE instructions: Streaming SIMD Extensions. Includes 128 bit registers, and a variety of instructions for bit manipulations, arithmetic etc. Recently includes dedicated instructions for cryptography. AVX instructions: Advanced Vectorial Extension, includes 256 bit registers. More extensions on the way. Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del InstitutoNovember Politécnico13, Nacional 2014 México 11 / 26 D.F.,
12 History of SSE Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del InstitutoNovember Politécnico13, Nacional 2014 México 12 / 26 D.F.,
13 How SSE instructions work? Utilize dedicated registers. Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del InstitutoNovember Politécnico13, Nacional 2014 México 13 / 26 D.F.,
14 How SSE instructions work? Multiple data can be packed in a single register Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del InstitutoNovember Politécnico13, Nacional 2014 México 14 / 26 D.F.,
15 How SSE instructions work? Task: For each f in array compute f = sqrt(f ). SISD: for each f in array { load f to the floating point register calculate the square root write the result from the register to memory } Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del InstitutoNovember Politécnico13, Nacional 2014 México 15 / 26 D.F.,
16 How SSE instructions work? SIMD: for each 4 members in array { load 4 members to the SSE register calculate 4 square roots in one operation write the result from the register to memory } Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del InstitutoNovember Politécnico13, Nacional 2014 México 16 / 26 D.F.,
17 Summary of SSE registers Number of registers Size MMX 8 64-bits SSE bits SSE bits AVX bits Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del InstitutoNovember Politécnico13, Nacional 2014 México 17 / 26 D.F.,
18 Sample SSE Instructions movss xmm, m32 Load a single-precision (32-bit) floating-point element from memory into the lower of xmm, and zero the upper 3 elements. memory address does not need to be aligned on any particular boundary. movaps xmm, m128 Load 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from memory into destination. Memory address must be aligned on a 16-byte boundary. movdqa xmm1, m128, Load 128-bits of integer data from memory into destination. Memory address must be aligned on a 16-byte boundary. (Other usages possible) Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del InstitutoNovember Politécnico13, Nacional 2014 México 18 / 26 D.F.,
19 Sample SSE Instructions Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del InstitutoNovember Politécnico13, Nacional 2014 México 19 / 26 D.F.,
20 Sample SSE Instructions Scalar operations (ss Single scalar) Packed (ps Parallel scalar) Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del InstitutoNovember Politécnico13, Nacional 2014 México 20 / 26 D.F.,
![Initially it was done by "Inline Assembly": asm { MOV EAX Op_A MOV EBX, Op_B MOVUPS XMM0, [EAX] MOVUPS XMM1, [EBX] ADDPS XMM0, XMM1 MOVUPS [Op_C], XMM0 } Complicated, not very readable, programmer](/docs-images/81/83707534/images/21-0.jpg "needs to take care of low level details like register allocation etc.")
21 Initially it was done by "Inline Assembly": asm { MOV EAX Op_A MOV EBX, Op_B MOVUPS XMM0, [EAX] MOVUPS XMM1, [EBX] ADDPS XMM0, XMM1 MOVUPS [Op_C], XMM0 } Complicated, not very readable, programmer needs to take care of low level details like register allocation etc. Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del InstitutoNovember Politécnico13, Nacional 2014 México 21 / 26 D.F.,
22 How to use these instructions in my C code? A better alternative is to use Intel intrinsics... m128 _mm_add_ps( m128 a, m128 b ); They are functions coded in assembly in appropriate header files. The syntax is much intuitive, and the programmer need not take care of low level details. Most compilers (say GCC, ICC) has a good understanding of the intrinsics and can generate optimized codes with them. Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del InstitutoNovember Politécnico13, Nacional 2014 México 22 / 26 D.F.,
23 What do we need? A processor which supports the instructions that we want to use. An appropriate copiler, which understand intrinsics(gcc or ICC, in general) The headers (.h) which corresponds to the instructions. Compile with appropriate flags to enable the instruction sets. Know the syntax of the instructions. Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del InstitutoNovember Politécnico13, Nacional 2014 México 23 / 26 D.F.,
24 Intrinsics Instructions Headers Flags -MMX mmintrin.h -mmmx -SSE xmmintrin.h -msse -SSE2 emmintrin.h -msse2 -SSE3 pmmintrin.h -msse3 -SSSE3 tmmintrin.h -mssse3 -SSE4.1 et SSE4.2 smmintrin.h -msse4.1 -msse4.2 -AES et PCLMUL wmmintrin.h -maes -mpclmul Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del InstitutoNovember Politécnico13, Nacional 2014 México 24 / 26 D.F.,
25 Intrinsics In intrinsics we can use some nonstandard data types : m128d, m128i General syntax for function names: _mm_<name>_<type> The prefix _mm_ is always present The second part is <name>, generally it is same as the assembly mnemonic, but not always. The final part <type> indicates the packing information. Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del InstitutoNovember Politécnico13, Nacional 2014 México 25 / 26 D.F.,
26 Intrinsics Examples : m128i _mm_add_epi8( m128i a, m128i b) m128i _mm_add_epi32( m128i a, m128i b) m128i _mm_add_epi64( m128i a, m128i b) m128i _mm_and_si128( m128i a, m128i b) m128i _mm_xor_si128( m128i a, m128i b) m128i _mm_or_si128( m128i a, m128i b) _pix : vector MM (64-bits) packed with X-bit words _epix : vector XMM (128-bits) packed with X-bit words _si64 : vector MM (64-bits) of a single 64-bit word _si128 : vector XMM (128-bits) of a single 128-bit word see instruction list at: https: //software.intel.com/sites/landingpage/intrinsicsguide/ Debrup (Computer Science Department, Centro deprogramming Investigaciónwith y desimd Estudios Instructions Avanzados del InstitutoNovember Politécnico13, Nacional 2014 México 26 / 26 D.F.,
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