Physics of Semiconductors (8)

Transcription

1 Physics of Semicoductors (8) Shigo Katsumoto et. Physics ad Ist. for Solid State Physics, Uiversity of Tokyo Jue 15, juctio trasistors From left, Joh Bardee, William Shockley, Walter Brattai. At AT&T Bell Laboratories, i Today, we see two kids of semicoductor devices iveted by a geius amed William Shockley. The style of research ad develomet which he bega, as well as his devices, has bee chagig the huma life. The above exressio is ot exaggeratio, I believe. I have read a short commetary, which tells the researchers i Bell Labs. were doig basic research o the surface states of Ge with uttig tis o the surfaces ad accidetally foud the trasistor actio. But this is far from real situatio. Walter Brattai ad Joh Bardee, who were the direct fiders, were doig research aimig at costructio of solid state amlifier uder the team leader Shockley. They did ot exect such a easy fidig robably but they realized the amlificatio certaily because they were doig such objective research. The exerimet was doe a little before the hristmas of 1947 (said to be 12/16. The alicatio for atet was 12/23) Shockley was out of the labs for a jourey. He was thus ot so glad hearig the success. Also the trasistor (the term is a combiatio of trasfer ad resistor) which Brattai ad Bardee accidetally foud was called oit cotact tye, ustable, had low reroducibility. It should have serious obstacles for commercial viability. Their fidig might have stimulated Shockley s fight as a ivetor, he was absorbed i thought as a theorist aimig at realizatio of reroducible device for amlificatio ad fially got the brilliat isiratio of juctio trasistor, o the ew year s eve allegedly. The theory for the juctio trasistor established 1/23 i the ext year. The exerimetal realizatio was a year later. The evet was the glorious daw of the semicoductor hysics, i which artificial structures i solids utilize the structural sesitivity of semicoductors ad create ew fuctios, ew stages of hysics[2] Juctio trasistor: structure Figure 2.4 shows basic structure of juctio trasistor (Biolar Juctio Trasistor, BJT, at times just biolar trasistor ), i which two -juctios are laced close to each other. ad are ossible tyes of juctios. A ohmic cotact to the cetral layer is required for the device to have three termials. The termials at the two eds are called ollector (), Emitter (E) resectively ad the cetral oe is called Base (B). I the very begiig, the structure was fabricated with alloyig metals which work as doats to both sides of the base material. The amig Base came from the fact though lithograhy ad thermal diffusio, io imlatatio ad eitaxy soo became the domiat methods. As we will see for the trasistor actio, the base should be very thi. Thier tha the miority carrier diffusio legth. 8-1

2 ollector () J Base (B) B B B E J B J E E (a) Emitter (E) (b) E Figure 2.4: (a) Schematic structure of trasistor. ircuit symbol ad the ames of termials. (b) Schematic structure of trasistor ad the circuit symbol. ircuit symbols of trasistors are show i Fig.2.4, which rereset coectios of two electrodes to the base grahically. ircles are ofte omitted. ad are distiguished with the directio of arrow, which idicates directio of electric curret whe miority carriers are ijected ito the base electrode. Below we cosider -tye ad defie the directios of the curret as i the figure urret-amlificatio of juctio trasistors I the first exerimet a costat voltage source is coected to B- ad collector curret J is measured. Iside the structure B- is othig but a diode ad the result is a well kow rectificatio characteristics (J E =i Fig.2.5(a)). Now we coect a costat curret source betwee E ad B, ad aly fiite currets through E. Because B-E is also a juctio, the forward bias is ositive for B. As show i Fig.2.5(a) V B J curve shifts arallely to egative. The amout of shift is almost J E. It should be oted that the characteristics is close to that of a solar cell show i Fig.2.3(b). The similarity is ot a coicidece, rather, the hysical situatio is almost the same. While I a solar cell, the miority carriers are directly created by hoto irradiatio, i a trasistor, the miority carriers are ijected through the juctio betwee E ad B to the other juctio betwee B ad. The heomeo occurrig i the juctios are summarised as follows. Here we oly describe the heomeo i coductio bad while that i valece bad ca be discussed i arallel. I a juctio, a reverse bias voltage to B()-() suresses the diffusio curret from the -layer to the -layer. The (reverse) diffusio of electros from the -layer to the -layer is ot ehaced by the reverse bias because all the electros reach from the -layer to the juctio are swug to the -layer ad it is already saturated at zero-bias. Uder the reverse (or zero) bias coditio of V B, let the other -juctio (E-B) be uder a forward bias coditio. This is ossible because a Ohmic cotact is attached to the base electrode, hece V EB ad V B ca be cotrolled ideedetly. The forward bias lowers the barrier by the built-i otetial i E-B juctio ad the electros (majority i the -layer) diffuse ito the base layer ad the miority carrier cocetratio icreases i B. This is the heomeo called miority carrier ijectio, which decays over the miority carrier diffusio legth through the recombiatio with majority carriers (holes). Note that the cotiuity i curret is hold. The flow by ijected electros is ot drive by the electric field but by the desity gradiet. So the flux is eredicular to the juctio lae almost igorig the base Ohmic electrode (the recombiatio curret goes to the electrode). Whe the B-layer is much thier tha the miority carrier diffusio legth, most of the ijected carriers reach the other juctio ehacig the reverse curret. I Fig.2.6(a), this aears as the ehacemet of the reverse curret, the amout of which is determied that of ijected miority carriers. Hece the curret does ot deed o V B as log as there is o forward curret. Now a amlificatio circuit ca be comosed as follows. Let the electrodes -E be voltage biased as i Fig.2.6(c). The amout of miority carrier ijectio ito B-layer is determied by V BE. Hece i this circuit 8-2

3 J (ma) (a) 2N222a J E = 1mA 2mA 3mA 4mA 5mA V B (V) V B B J J E electro E J (ma) (b) 4 2N222A J B = 2A 3 A A 2 A 1 A.5 1 V E (V) B J B J E electro E J V E Figure 2.5: (a) J (uside dow for coveiece) as a fuctio of V B with J E as a arameter i the circuit show i the lower ael. With icreasig J E i.e., ijectig electros from E to B, the characteristics resembles to that of a illumiated solar cell. (b) Alicatio of collector-emitter voltage V E with floatig B, almost o curret flows due to the reverse bias i -B. The biasig B with some currets J aears accordig to J B showig saturatio for V E. J strogly deeds o V BE as show i Fig.2.6(a). However, the relatio is too o-liear for the use of the device i a voltage-iut circuit. Some of the ijected miority carriers recombie with majority carriers ad some ortio flows out to B-electrode. The base curret J B deeds o V BE i the same fuctioal form oly but the coefficiet as J because the -juctio is the same. J is thus roortioal J B,thatis, J = h FE J B. (2.16) The good liearity is cofirmed i the measuremet as show i Fig.2.6(b). h FE is called curret amlificatio factor. Ad it is ofte said that a biolar trasistor works as a curret amlificatio device from this face. This is i ractice, true as log as we use it as a black box device i electric circuits. However i hysical mechaism, as discussed above, there is o such causality that a small curret drives a larger curret. The followig exressio may be closer to reality: a small curret here is just a moitor for voltage to cotrol a large curret. I the usage of a BJT i a circuit, care should be take that (because it is a curret amlificatio device ) the iut voltage bias should be set to a low differetial resistace regio. Particularly i high frequecy circuits, the imedace matchig should be take to the characteristic imedace of the trasmissio lie. Oe simle rule for trasistor circuits is that whe a trasistor is workig as a amlifier, the base-emitter bias voltage should be aroud the quasi-threshold voltage (though as we saw there is o threshold voltage i -juctios, i ordiary circuit scale, the I-V curve seems as if it has). 8-3

4 N222A V E =6V J (A) N222A V E =6V J (ma) V BE (V) (a) V BE B electro J B E (c) J 6V 1 J (A) J B (A) J B ( A) (b) Figure 2.6: haracteristics of a trasistor measured i a exerimetal circuits show i (c). (a) -E is biased with 6 V ad the voltage betwee B-E (V BE ) is varied. J strogly deeds o V BE.(b)J is re-lotted as a fuctio of J B ad (because oututs of the same diode is observed) very good liearity is obtaied. The iset shows a log-log lot with a broke lie idicatig sloe Field effect trasistors I Field Effect Trasistors (FETs) are ow used much more widely i circuits tha BJTs. Ad the idea of FET was bor eve log before that of BJT 1, but for the realizatio of FET requires techologies eve higher tha those for BJT ad the realizatio was later tha that for BJT. I these 2 years, Metal-Oxide-Semicoductor (MOS) tye FETs are maily used but the first FET was realized for Juctio FET (JFET), which utilize juctios juctio ad deletio layer For uderstadig the device actio of JFET, the relatio betwee the reverse bias voltage ad the deletio layer is imortat. We cosider a -juctio show i Fig.2.7, with x-deedet otetial φ(x). The Poisso equatio is give as d 2 φ dx 2 = aq(x) (a (ɛɛ ) 1 ). (2.17) I the sace-charge regio (deletio layer) we assume abrut cocetratio distributio of doats ad shar cuttig of the ed of deletio layer. The { q = en A ( w x ), (2.18) q = en ( x w ). 1 Shockley wrote a atet o FET before BJT though may similar ideas had existed before that. We caot say the atet is as uique as that of BJT. 8-4

5 e( V V) bi w w Figure 2.7: Simle model of a juctio Let s take the asymtotic coditio as φ( ) =. Whe there is exteral reverse bias voltage V,the boudary coditio at the edges of deletio layer is dφ φ( w )=, dx =, w (2.19) dφ φ(w )=V V bi, dx =. w Itegratio of the above gives φ(x) = { (aen A /2)(x w ) 2 ( w x ), V V bi (aen /2)(x w ) 2 ( x w ). (2.2) From the coditio for the coectio at x = lim φ = lim φ, x x the widths of deletio layer w, w are give as follows. lim (dφ/dx) = lim (dφ/dx), (2.21) x x [ ] 2ɛ ɛ(v V bi ) N 1/2 [ ] 2ɛ ɛ(v V bi ) N 1/2 A w =, w = (2.22) en A N N A en N N A [ ] 2ɛ ɛ(v V bi ) w d = w w = NA N 1/2. (2.23) e N A N 1/ 2 The charge accumulated i the deletio layer o -side is Q = en w d er uit area givig the effective caacitace (differetial caacitace) as dq dv = en 2ɛɛ 1 en 2 ɛɛ en = (V V bi ) 1/2. (2.24) V V bi 2 I a -structure, that is, N A N, V [ ] 2ɛɛ (V V bi ) 1/2 w d w. (2.25) en V bi This meas the deletio layer exads i roortioal to the square root of the reverse bias voltage lus the built-i otetial. This relatioshi is frequetly used for characterizatio of juctios. For examle, differetial caacitace (V ) ca be measured with alyig high frequecy voltage 8-5

6 source with a small amlitude ad through the hase shift. We lot the data as show i the left figure (for the coveiece, the horizotal axis is take to V ), 1/ 2 versus V.IfN is satially uiform, the data oits should be aliged o a lie. (2.24) is valid oly for V > ad caot be realized. But with extraolatio from V > the oit 1/ 2 =ca be secified ad we obtai V bi from this. Whe N is ot uiform satially or some dee level tras exist, we obtai iformatio of the satial distributio from differetiatig the lot. Alicatio of ulses i V ad aalysis of trasiet resose uder light illumiatio or related techiques ca brig much of the iformatio iside the semicoductor[4] Juctio Field Effect Trasistors Figure 2.8 shows a schematic drawig of the JFET structure i a cross sectioal view. It is for a -chael, which has two electrodes o the both edges. They are called Source (S) ad rai () resectively. The chael is sadwiched by layers called Gates (G). The ricile of device actio is very simle as ca be see i Fig.2.8. Alyig reverse bias to the gates causes exasio of white-colored deletio layer accordig to eq.(2.23). This makes the coductio chael arrower ad ehaces the chael resistace u to ifiity for ich-off. Thus the curret through the device is cotrolled by the gate voltage. This is aaretly a voltage-cotrolled device ad the iut imedace is tyically resistace of -juctio i reverse bias coditio. So it is classified ito high iut imedace device. A characteristic feature here is that a large source-drai curret causes a sigificat voltage dro across the device, resultig i gradiet of effective reverse bias voltage for the chael-cotrollig deletio layer. Let us see a simle model. As before i the model for -juctios, we assume the boudaries betwee deletio layers ad coductio chael are abrut. Let the gate legth L, the thickess of JFET 2w t. We take the chael directio alog y-axis. The deletio layer with w d is 2ɛɛ V (y) w d (y) =, (2.26) en where V (y) is local voltage at ositio y betwee the chael ad the gate. V (y) ca be obtaied by subtractig voltage alog the chael V ch due to the source-drai curret from the sum of the built-i otetial V bi ad the reverse bias gate voltage V g. V (y) =V g V bi V ch (y). S (source) L G (gate) w d ( y) G (gate) y (drai) 2w t 3V 3V G G S S -chael -chael Figure 2.8: Schematic structure of JFET (-chael) (uer left ael). A cross-sectioal view. The easiest way to form the -layer is alloyig the metal, which ca work as accetor iside the semicoductor. The icture i the ceter shows the way the deletio layer exad (white regio) with alicatio of reverse bias to the gates. The uer left shows circuit symbols. The (lower) left shows the dimesios of the model adoted i the text. 8-6

7 We have o ijectio of miority carrier ad oly cosider the drift curret of majority carriers. The electric field alog y-directio is dv/dy. Let the chael deth W ad the drift curret through the chael is J ch = en μ dv dy 2(w t w d )W. (2.27) I steady state there is o chargig u ad J ch is uiform through the chael thus itegratio over the chael should be J ch L. J ch L = L J ch dy =2eN μ W L (w t w d ) dv dy dy =2w ten μ W VL V ( 1 w ) d dv. (2.28) w t Let the critical voltage V c at which the chael is iched (w d = w t )adj ch =the V c = en w 2 t /2ɛɛ. Hece from w d /w t = V/V c, J ch i this model is obtaied as J ch = 2N eμ Ww t L [ V L V 2 ] 3 (V (V ) 3/2 V (V L ) 3/2 ). (2.29) V c I eq.(2.29), at small voltages, the first liear term i V L is domiat ad J ch icreases liearly. With icreasig the voltage, the last V 3/2 L term grows ad at last the curret begis decreasig, which meas egative differetial resistace. I actual device, this does ot occur ad J ch simly saturates with icreasig V.The model cotais various shortages, e.g., the equiotetial lies are straight ad alog x-axis. Imroved models ca reroduce the saturatio but they are ievitably comlicated. There are also emirical aalytical formulas well fit to the exerimets but they have o hysical reasoig. 2.6 Field Effect Trasistors II Next we see FETs without -juctio. For trasistor actio, they utilize heomea o the surfaces or iterfaces. I homo-tye -juctios the uiformity of sace is broke by imurity doig. They do ot use iterfaces or surfaces. This was imortat for Shockley ad co-workers to realize stable ad reroducible devices because for the semicoductor techologies i those days cotrol of surfaces or iterfaces was too difficult for commercial roductio. Eve the high quality crystallie growth ad the accurate doig techique, which are idisesable for the realizatio of -juctios, were surrisigly high techique. However the great strides i semicoductor techologies caught the cotrol techiques of surfaces ad iterfaces i icredibly short time. Naturally there were movemet to utilize them for device actios ad they overwhelmed bulk shortly. We have a look for these reresetative moder devices here. But the limit of miiaturizatio ievitably requires three dimesioality owadays ad we do ot kow what haes ext Schottky barrier (juctio) Here we cosider juctios betwee semicoductors ad metals. Simle guidig riciles are 1. Rigid bad aroximatio, 2. Recovery of bulk states away from the juctio, 3. I equilibrium E F (μ) is costat over the sace. O semicoductor surfaces, there usually are surface states with high desity of states. Metal-semicoductor juctios are strogly affected by those states. Here, however, we first look what Aderso s rule tells about the iterface[5]. The baselie of rigid bads ca be take to a edge of bad, i which electros ca freely travel betwee the metal ad the semicoductor. It is usually imossible to fid such a eergy bad iside isulators ad semicoductors, which have very differet eergy bads. The such a bad ca be foud as 8-7

8 e S E c E c E c e M e( M S ) E E F E F E F E F e surf E E v w d (a) (b) (c) E Figure 2.9: (a) Virtual bad aligmet, i which a metal ad a semicoductor are coected as the vacuum levels for them agree. (b) Bad bedig effect to make E F costat throughout the juctio is suerosed to the aligmet i (a). The situatio corresods to a ideal iterface without surface states at the semicoductor side. (c) Illustratio of Fermi level iig by surface states. The surface otetial φ surf is determied by the ositio of the domiat surface states from the bad edge E c. This usually has othig to do with the differece betwee the work fuctio. the vacuum levels. The the excitatio eergy required is so called work fuctio. Let the work fuctios i the semicoductor ad the metal eφ S ad eφ M resectively. Geerally eφ M eφ S. O the other had, from the guidig ricile 2., the bulk E F s i the metal ad i the semicoductor away from the juctio should be the same. Ad E F should be costat throughout the system. The followig rocedure, of course, is ot real hysical rocess but just a virtual rocess iside huma brai, for costructio of cosistet bad aligmet. The fial result, however, may be realized i the model of juctios though there still remai may idealizatios ad reality should be much more comlex. We assume eφ M is larger tha eφ S, the semicoductor is doed to -tye ad the door cocetratio is N. We make the vacuum levels i the both sides fit to each other ad extraolate the bulk bad structures to the iterface to obtai the bad aligmet show i Fig.2.9(a). Here the Fermi level i the semicoductor laces higher tha that i the metal causig flow of carriers from the semicoductor to the metal. The carrier flow geerates charge accumulatio at the iterface creatig a electric field eredicular to the juctio lae. The metallic side is also charged u but it has much higher charge cocetratio, which screes the electric field withi the screeig legth less tha a lattice costat makig the bad bedig egligible i this side. Let the accumulated charge i the metal side er uit area Q, i the semicoductor side (x >, iterface at x =), the electric field at x is (en x Q)/ɛɛ ad the otetial differece betwee ad x d is φ(x d )= xd (en x Q)/ɛɛ dx = 1 ɛɛ ( en 2 x2 d Qx d ). (2.3) Let the sace charge (deletio) layer width be w d. The coditio that electric field outside the deletio layer should be zero, gives w d = Q/eN. O the other had, the coditio eφ(w d )=φ M φ S also gives Q as Q = 2ɛɛ (φ M φ S ) 2ɛɛ V s 2ɛɛ N e(φ M φ S ), w d =. (2.31) en en Here we write ev s φ M φ S. Now we ca illustrate the bad structure for electros (holes for -tye) aroud the metal-semicoductor iterface as i Fig.2.9(b), showig a otetial barrier, which is called Schottky barrier. A exteral voltage V is mostly bared i the semicoductor side, ad the height of the barrier chages to e(v s V ) while the height from the metal side remais as ev s. To be more accurate, we eed to cosider the kietic eergy distributio i the semicoductor ad cout the umber of electros which go over the barrier. But here for simlicity we assume the kietic eergy of electros i the semicoductor is a costat. The the 8-8

9 equatio for thermal electro emissio from metallic surface ca be alied to obtai ( ) ( )] ( )[ e(v J = AT [ex 2 Vs ) evs ex = eat 2 evs ex ex k B T k B T k B T ( ev k B T ) ] 1. (2.32) Here A is the Richardso coefficiet. The first term is curret from the semicoductor side, the secod is that from the metal side. The curret-voltage characteristics is similar to that of a -juctio with the Schttkey barrier height corresodig to the built-i otetial. I the above the surface of semicoductor is too much idealized for it to have o surface states. However i real metal-semicoductor juctios, curret-voltage characteristics are similar to eq.(2.32). Oe big differece is i eq.(2.32), the barrier height should chage with chagig the metal secies but i reality, the barrier height is almost costat for semicoductor secies ad ideedet of metals. This is due to the surface states o the semicoductors. The surface states have arrow eergy widths, very high desity of states iig the Fermi level to the ceter of them. Hece the bad bedig exists eve before the coectio to metals ad the aligmet is accomlished betwee the metal E F ad the surface states. This is called iig of Fermi level by the surface states. Oce the Fermi level is ied by the surface states, the bad bedig is determied by semicoductor secies. Hece whe -tye Schottky barrier ca be formed for a semicoductor for examle, -tye is ot available for the same semicoductor. The other way aroud. Actually, for GaAs, -tye Schottky barrier is ot available while for IP, -tye Schottky barrier is difficult. This makes it difficult to obtai comlemetary devices which utilize Schottky barriers. I the case of metal-oxide-semicoductor (MOS) devices, a iversio layer formed by e.g., ushig dow a bad of a -tye semicoductor ad turig it to a -tye chael, ca be used for comlemetary device. This is, however, imossible for Schottky devices MES-FET Amog III-V semicoductors, GaAs is frequetly used for electric devices as well as for otical devices. But it is difficult to form good quality oxide layers o the surfaces, hece o MOS tye device for GaAs is available. Istead, MEtal-Semicoductor FET (MES-FET) structure has bee frequetly adoted. GaAs has light electro mass, high mobilities. Ad the effective caacitace of Schottky diode ca be small. Hece GaAs MESFETs are ofte used for high-frequecy alicatio. As show i the left figure, the structure of MES-FET is simle. The coductio chael thickess is cotrolled source coductio chael gate drai deletio layer with the reverse bias voltage (gate voltage) through that of deletio layer. The device actio, characteristics are similar to those for JFET. Schottky juctios have larger leak curret i gate characteristics, oly sigle carrier tye is available ad comlemetary circuits caot be comosed with them. These roerties are great obstacles for large scale itegratio. MES-FETsarestill widely used as high frequecy devices for e.g., microwave MOS structure As amed, a thi oxide film for isulatio is iserted betwee a metal ad a semicoductor i a Metal-Oxide- Semicoductor (MOS) structure. Needless to say, most frequetly used Si has SiO 2 as the oxide layer, which is very stable ad has good isulatio characteristics. A SiO 2 film ca be easily formed with thermal oxidatio oto a Si. Both -tye ad -tye chaels ca be cotrolled ad omlemetary MOS (MOS) circuits are easily realized. Also with low gate leakage curret, high o-coductace, off-resistace, the ower cosumtio i logic circuits jumed dow with the MOS circuits hece icreased degree of itegratio. Now MOS is doubtlessly the kig of semicoductor circuits. A few decades ago high seed logic circuits were 8-9

10 metal electrode oxide film V G metal electrode oxide film V -Si source coductio chael gate drai oxide film Figure 2.1: Schematic view of a MOSFET device. I fabricatio holes are oeed o thermally oxidized films with lithograhy. The doats are diffused through the holes. The structure like this ofte aears due to the rocess. maily comosed with Emitter oulled Logic (EL) of BJT but the requiremet of large scale itegratio ad the icrease of cut-off frequecy i MOS circuit have made drastic chage ad ow, eve so called suercomuters are usig MOS circuit i PU. MOSFET structure also resembles to JFET ad the essetial differece to MESFET is the existece of thi oxide layer betwee the semicoductor ad the gate metal. I a deletio tye device, the coductio chael is iched by deletio layer while i a ehacemet tye device, the bad is ushed dow with gate electric field to form coductio chael. A oxide layer bears much higher voltage tha a Schottky barrier, hece with a strog bedig, e.g., formatio of a -tye two-dimesioal coductio chael below a -tye semicoductor surface (iversio layer). Refereces [1] S. M. Sze, K. K. Ng, Physics of semicoductor devices, (Wiley-Blackwell, 27). [2] Jo Gerter, The Idea Factory: Bell Labs ad the Great Age of America Iovatio, (Pegui Press, 212). [3] Lectures o exerimetal hysics Basic measuremet techiques (Maruze, 1999) h.2 (i Jaaese) [4] A. Pataè ad N. Balka eds. Semicoductor Research: Exerimetal Techiques (Sriger Series i Materials Sciece, 212). [5] R. L. Aderso, IBM J. Res. ev. 4, 283 (196). Aedix ee level trasiet sectroscoy (LTS) Here I would like to give qualitative exlaatio o the basic riciles of ee Level Trasiet Sectroscoy (LTS). For details, see e.g. ref. [4]. We cosider modificatio to effective caacitace (2.24), which deeds o the reverse bias voltage V.LetN be the shallow door cocetratio, N P the oe for a dee door. I the regio where this dee door resods to chage i the bias voltage, the voltage-differetial caacitace is exressed as a fuctio of reverse voltage V as [ ] 2ɛɛ (V V bi ) 1/2 w d (V ) w, (.1) e(n N P ) ɛɛ e(n N P ) (V )= (V V bi ) 1/2. (.2) 2 For simlicity, we cosider the situatio that the reverse bias V is alied ad ket for sufficietly log time for electros to escae from the deletio layer icludig the dee levels 2. Now V is abrutly lowered to 2 At low temeratures the cature/emissio rates of dee levels become very small ad it is ot rare that we eed days for the emissio. So this coditio is, i geeral, hard to be fulfilled. But the cosideratio of this does ot give sigificat chage ad thus we adot the assumtio. 8-1

11 w( V) w( V) ( T) T ( V) ee level 1 ee level 2 ( V) t 1 t 2 t T (a) (b) Figure 2.11: (a) Uer ael: Illustratio that the chage i the reverse bias V V makesshallowlevelsad a art of dee levels ready for catchig carriers. Lower ael: With rogress i cature of carriers, differetial caacitace (V ) shows trasiet resose. (b) Uer ael: two dee levels exist ad assumed temerature deedeces of the cature cross sectio σ are illustrated. Lower ael: shows how the LTS sigal aears from the temerature deedece σ(t ). V <V ad the carriers are catured by the door levels withi w(v ) <x w(v ). Shallow doors have high cature rate ad ca resod withi ms without delay, dee levels, o the other had, the cature rate strogly deeds o temerature ad with decreasig temerature, the average time for cature ofte elogates from ms to s, mi, hour ad sometimes day. The if we oe u a fixed time widow ad observe the time evolutio of, the time deedece is observed i the time widow at some temerature rage ad i low or high temerature regios the effect of dee levels does ot observed. Such a rocess is illustrated i Fig.2.11(a). We take t =at the time the reverse bias is chaged:v V ad measure the differece i the differetial caacitaces at t 1 ad t 2 : Δ = (t 1 ) (t 2 ) as a fuctio of temerature T. We ow assume existece of two secies of dee doors, which have temerature deedet cature cross sectios show i the uer ael of Fig.2.11(b). Δ should show two eaks i the temerature deedece. Aalysis of the data gives the cocetratio ad cature cross sectio of each dee level, ad combiatio with hoto-resose, i some cases idetificatio of dee levels or at least eergy ositios ca be measured[4]. With variatio of V ad V, deth rofile of dee levels ca be obtaied also. 8-11