DEI1058 Six Channel Discrete-to-Digital Interface Sensing 28 Volt/Ground

Transcription

1 Device Engineering Incrprated 385 East Alam Drive handler, AZ Phne: (480) Fax: (480) DEI1058 Six hannel DiscretetDigital Interface Sensing 28 lt/grund Features: Senses six 28 / Grund inputs Small ftprint (16L SOI NB) Inputs are lightning prtected per DO160D Level 3 TTL/MOSmpatible Tristate utputs Lw st 55º t 85º perating temperature range. 100% Final testing Functinal Descriptin: The DEI1058 is a six channel discretetdigital interface BiMOS device. It senses six 28/Grund discrete signals f the type cmmnly fund in avinic systems. The inverted utputs are TTL/ MOS cmpatible and are en abled by the OE and E pins. The inputs f this small 16 lead narrw bdy SOI device are lightning prtected t meet the requirements f DO160D wave frms 3, 4, and 5 Level 3. See figures 57. OE E DD IN 1 OUT 1 IN 2 OUT 2 IN GND IN 3 IN 4 IN 5 IN 6 OUT 3 OUT 4 OUT 5 OUT 6 IN 2 IN 3 IN 4 IN 5 IN OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 DD OE 7 10 OUT Reference GND E 8 9 DD Figure 1: ncept Drawing Figure 2: Pinut Diagram 2007 Device Engineering 1 f 5

2 Table 1: Abslute Maximum Ratings PARAMETER MIN MAX UNITS Supply ltage DD Discrete Input ltage (Pins 16) 5 35 * Digital Input ltage (E and OE) SS 0.3 DD 0.3 Lightning Prtectin (Pins 16) DO160D, Wavefrm 3; Level 3 DO160D, Wavefrms 4, and 5; Level Strage Temperature Operating Free Air Temperature Lead Sldering Temperature (10 Secnds Max) 280 Bdy Sldering Temperature (10 Secnds Max) 210 The DEI1058 cntains circuitry t prtect inputs frm damage due t electrstatic discharge. It has been characterized per JEDE A114A Human Bdy Mdel t lass 1. Observe precautins fr handling and string Electrstatic Sensitive Devices. * The DEI1058 will withstand the transient surge D vltage step functin lci limits fr categry B equipment per MIL STD704A. Table 2: DEI1058 Device Operating haracteristics PARAMETER SYMBOL ONDITIONS MIN TYP MAX UNITS Supply ltage DD Free Air Operating Temp. T A DD = Lgic Output Sink urrent I OL DD = ma Lgic Output Surce urrent I OH DD = ma Table 3: DEI1058 Lgic Truth Table E (hip Enable) OE (Output Enable) Discrete Input Output Grund 1 1 X X High Z X 1 X High Z 2007 Device Engineering 2 f 5

3 Table 4: DEI1058 Electrical haracteristics (T A = 55º TO 85º, DD = 4.5 TO 5.5, Unless therwise nted) PARAMETER SYMBOL ONDITIONS MIN TYP MAX UNITS Pwer Supply and Thermal Data Supply urrent I IN = DD (all inputs) DD DD = ma Thermal Resistance θ JA θ J Junctin t Ambient Junctin t ase Max. Junctin Temperature Τ Jmax Max. Junctin Temperature 125 Discrete Input haracteristics 28 lt input vltage High Output SG terminal t grund fr Lgic ltage surce frm input High Output. 28 lt input vltage Lw Output SO terminal t grund fr Lgic ltage surce frm input Lw Output /W Grund State Input Resistr R IG Grund t guarantee Lgic 100 Ω Resistr frm input t High Output. urrent surced int 100 Input surce current I IO Ohm resistr t grund µa Reverse Leakage urrent I IR IN = 35, DD = µa Lgic Input haracteristics E, OE input lgic 1 level IH 2.0 E, OE input lgic 0 level IL 0.8 D Output haracteristics Output lgic 1 level (TTL) OH I OH = 5 ma. 2.4 Output lgic 0 level (TTL) OL I OL = 5 ma. 0.4 Output lgic 1 level (MOS) OH I OH = 100 µa DD 50m Output lgic 0 level (MOS) OL I OL = 100 µa SS 50m /10 µa Offstate Output urrent I OZ DD = 5.5 OE = DD OUT = 0 r DD Switching haracteristics I/O prpagatin delay t HL, t LH Refer t Figure ns Delay frm E r OE input (with utput lw) t utput HIZ t LZ Refer t Figure ns Delay frm E r OE input (with utput HIZ) t utput lw t ZL Refer t Figure ns Delay frm E r OE input (with utput high) t utput HI Z t HZ Refer t Figure ns Delay frm E r OE input (with utput HIZ) t utput high t ZH Refer t Figure ns 2007 Device Engineering 3 f 5

4 OE r E t ZL t LZ t ZH t HZ HI 0.3 OUTPUT LO 0.3 IN = DD = 1K Ω t DD L IN = SS = 1K Ω t SS L Figure 3: Enable t Output Prpagatin Delay INPUT 16 t HL t LH 2.4 OUTPUT 0.4 LO = 1K Ω L t DD Figure 4: Input t Output Prpagatin Delay 2007 Device Engineering 4 f 5

5 /I Largest 25% t 75% f Largest T1 = 6.4 micrsecnds ±20% T2 = 70 micrsecnds ±20% 0 t Figure 5: DO160D ltage Wavefrm #3 O = 600, I S = 24A, Frequency = 1.0MHZ ±20% 0 T1 T2 Figure 6: DO160D ltage Wavefrm #4 O = 300, I S = 60A t /I 5A: 5B: T1 = 40 micrsecnds ±20% T2 = 120 micrsecnds ±20% T1 = 50 micrsecnds ±20% T2 = 500 micrsecnds ±20% Ntes: 1. O = Open ircuit ltage available at the calibratin pint. 2. IS = Shrt ircuit urrent available at the calibratin pint. 3. Amplitude tlerances: 10%, 0% 4. The rati f O t IS is the generatr surce impedance t be used fr generatr calibratin purpses. 0 T1 Figure 7: DO160D ltage Wavefrm #5 O = 300, I S = 300A T2 t Pin 1 Dimensins are in IN (MM) ( ) ( ) ( ) ( ) ( ) ( ) (0.381) ( ) (1.270) BS ( ) ( ) Figure 8: DEI1058 Mechanical Outline JEDE MS Device Engineering 5 f 5