Dynamic Voltage and Frequency Scaling Under a Precise Energy Model Considering Variable and Fixed Components of the System Power Dissipation

Transcription

1 Dynamic Voltage and Frequency Scaling Under a Precise Energy Model Csidering Variable and Fixed Compents of the System Power Dissipati Kihwan Choi W-bok Lee Ramakrishna Soma Massoud Pedram University of Southern California Outline! Background! Workload decompositi " Executi time model " System energy model! Fine-grained DVFS policy! Experimental results! Cclusi 1

2 Background DVFS! DVFS is a method through which different amount of energy is allocated to perform a task! Power csumpti of a digital CMOS circuit is: P = α C V 2 f eff α : switching factor C eff : effective capacitance V : operating voltage f : operating frequency! Energy required to run a task during T is: E = P T V 2 (assuming f V, T f 1 )! Lowering V (while simultaneously and proportiately cutting f) causes a quadratic reducti in E! The target CPU frequency is calculated as follows: " Given a task with workload, W, and latency cstraint, D " f target is hence calculated as W/D (Note that T task = D) Overview of prior DVFS works! Most DVFS methods are ccerned about CPU energy reducti ly " More precisely, dynamic porti of the CPU energy! Most computing systems, however, comprise of many subsystems such as memory and peripheral devices! Lowering CPU frequency can cause shorter battery lifetime due to increased energy csumpti in the subsystems Power f = 1 f cpu =.5 P cpu = 1 P cpu =.125 =.9 =.9 P mod E sys = 1.9 P mod E sys = 2.5 P cpu P mod Time ~8% more energy csumpti 2

3 DVFS for the minimal system energy! Two requirements " Satisfy timing cstraint " Minimize the system energy! Timing cstraint " Different applicatis exhibit disparate executi time variati as a functi of the CPU frequency change " Accurate modeling of the task executi time as the CPU frequency is varied! Minimal system energy " Power csumpti of each system compent should be known " Info. about each compent state, i.e., active or idle is required! These two requirements can be satisfied by using the workload decompositi approach Workload decompositi! CPU-bound vs. memory-bound applicatis show different executi time variati according to the CPU frequency! Workload of a program csists of -chip (W ) and chip (W ) workloads " W : work performed inside the CPU, e.g., ALU operati " W : work performed outside the CPU, e.g., -chip memory access after cache miss! Program executi time T W W T = T + T = + cpu ext f f! Given a task with workload, W and W, and latency cstraint, D W ftarget = W D ext f 3

4 System power breakdown! Power csumpti profile fluctuates greatly due to alternate executi of W and W " W (W ) requires the CPU (sub-module) power! System power csumpti can be broken into the following compents: remains unchanged DC-DC cverter, PLL, leakage, PCI bridges idle + fixed fixed variable idle standing active when each compent is not used CPU idle, memory is not accessed when each compent is used for some task CPU active, memory is accessed obtained by simple measurements or using values in the spec Performance mitoring unit (PMU)! W is modeled as: N W = CPI = N CPI i avg i = 1 N CPI : number of chip instructis : CPU clocks per instructi! PMU the PXA255 processor chip can report up to 15 different dynamic events during executi of a program " Cache hit/miss counts, TLB hit/miss counts, No. of stall cycles, Total no. of instructis being executed, Branch mispredicti counts! For DVFS, we use the PMU to generate statistics for " Total no. of instructis being executed (INSTR) " No. of stall cycles due to /-chip data dependencies (STALL) " No. of Data Cache misses (DMISS)! We also record the no. of clock cycles from the beginning of the program executi (CCNT) 4

5 Frequency settings in BitsyX! PXA255 can operate from 1MHz to 4MHz, with a core supply voltage of.85v to 1.3V! Internal bus cnects the core and other functial blocks inside the CPU! External bus is cnected to SDRAM (64MB)! Nine frequency combinatis (f cpu, f int, f ext ) Freq. Set f cpu [MHz] V cpu [V] f int [MHz] f ext [MHz] F 1.85 F F F F F F F F Executi time and frequency settings! Executi time variati over different frequency combinatis math, crc, djpeg, qsort, and gzip " math is CPU-bound ( strgly dependent f cpu ) " gzip is memory-bound (f int & f ext dependent ) Executi time (norm.) math gzip Frequency combinati Freq. Set F 1 F F F F F F F F 8 f cpu (MHz) f int (MHz) f ext (MHz) 1 5

6 Calculating T (I)! T W avg is calculated as: T =, W = N CPI cpu f! We define SPI as ratio of the number of stall cycles to the total instructi count " SPI avg = STALL / INSTR, during a time quantum avg avg avg SPI = SPI + SPI CPI = CPI + SPI avg min avg Onchip CPI value without any stall cycles CPI avg gzip SPI avg Calculating T (II)! Based the following observati: " The more D-cache miss events, the higher probability of -chip accesses! We define DPI as ratio of the number of D-cache miss events to the total instructi count " DPI avg = DMISS / INSTR, during a time quantum CPI min CPI avg min CPI = CPI + dpi2 spi( DPI) avg CPI min SPI DF = avg CPI min ( CPI CPI ) n avg SPI Dpi2spi(DPI) CPI -CPI min DF*(n-1) DF*2 DF*1 DPI DPI K 1 K 1 < DPI K 2 K n-2 < DPI K n-1 K n-1 < DPI K n DPI > K n K n is cstant: K 1 <K 2 < < K n 6

7 Calculating T! T is dependent the f ext as well as f int! Example: when a D-cache miss occurs, two operatis are performed: " Data fetch from the external memory (f ext ) " Data transfer to the CPU core where the cache-line and destinati register are updated (f int )! Due to lack of exact timing informati, we have opted to model T as: α α = + = + (1 ) W W T Tint Text int ext f f! An α value of ~.35 was obtained for tested applicatis " The average error in predicting the executi time was less than 2% for all nine frequency settings System energy modeling BitsyX! Hard to get system energy without workload decompositi! Using workload decompositi Power P, ( t) sys F n power T t 1 t 1 +T time std P sys, Fn P F n T F n P int,f n T int,f n P ext, Fn T ext, Fn t 1 t 2 t 4 t 3 active power standing power Time E = P T + P T + P T + P T std sys, F sys, F F F int, F int, F ext, F ext, F n n n n n n n n 7

8 Accuracy of the system energy model! The estimated energy csumpti for djpeg " The average error rate is less than 4% measured parameters Freq. set F F *1.33 F F F *1.33 F F F 8 F 9 std P sys, F n ( mw ) ( m W ) P F n 675 P int,f n ( mw ) 1733 P ext, F n ( m W ) Energy csumpti [J] measured estimated Frequency combinati P ~ k V f + k f 2 cpu int int,f n 1 Fn n 2 n k 1 =.73 [nf], k 2 = 6.2 [V 2 nf] Determining the optimal frequency setting! Csider timing cstraint followed by system energy minimizati " For a timing cstraint, we used performance loss (PF loss ) which is defined as: ( TF T ) n F PFloss = TF! Pseudo code for optimal frequency selecti Timing cstraint Energy minimizati 1. Ψ = { F min,, F }, Γ = {φ }, and E min = 2. for every frequency setting F n in Ψ 3. i+1 i if ( T (1 + PFloss ) T F F n ) 4. Γ = Γ F n ; 5. for every frequency setting F n in Γ 6. calculate system energy using proposed model 7. if ( E sys E min ), Fn 8. E min = E sys,fn ; F opt i+1 = F n ; 8

9 The software architecture! The software architecture comprises of a proc interface module and a policy setting module tightly linked with the Linux scheduler, the PMU, and the freq. and voltage ctrol circuitry the BitsyX board External PF loss input parameter Kernel Space proc Interface Module Linux Scheduler Policy Setting Module PMU Access Module DVFS Module PXA255 Processor Actual performance [%] Experimental results (I)! Compared two DVFS techniques: " SE-DVFS : proposed DVFS (saving the system energy) " CE-DVFS : cvential DVFS (saving the CPU energy)! Resulting performance loss factors: Target PF loss CE-DVFS 1% 2% 3% 4% 5% Actual performance [%] SE-DVFS Target PF loss 1% 2% 3% 4% 5% 9

10 Experimental results (II)! System energy csumpti of the two DVFS approaches compared to the case without any DVFS " CE-DVFS : always more energy csumed " SE-DVFS : system energy saving for some applicatis CE-DVFS SE-DVFS 1 1 System energy saving [%] Target PF loss 1% 2% 3% 4% 5% System energy saving [%] Target PF loss 1% 2% 3% 4% 5% Experimental results (III)! Actual power csumpti of the two DVFS methods! For gzip with 3% target PF loss, SE-DVFS results in 11.4% lower total system energy than CE-DVFS Power csumpti [mw] 5 gzip, with 3% Target PF loss CE-DVFS avg. power : 2619mW, 6.531sec Energy : 17.15J Time [sec] Power csumpti [mw] 5 gzip, with 3% Target PF loss SE-DVFS avg. power : 272.3mW, 5.568sec Energy : J Time [sec] 1

11 Experimental results (IV)! CE-DVFS vs. SE-DVFS " SE-DVFS results in 2% ~ 18% higher system energy savings compared to CE-DVFS System energy difference [%] Target PF loss 1% 2% 3% 4% 5% Cclusis! A DVFS policy for the actual system energy reducti was proposed and implemented, which uses line decompositi of the applicati workload into -chip and -chip compents! Based actual current measurements in the BitsyX platform, up to 18% more system energy saving was achieved with the proposed DVFS compared with the results in the previous DVFS techniques! For both CPU and memory-bound programs, given timing cstraints were also satisfied 11