Leveraging Task-Parallelism in Energy-Efficient ILU Preconditioners
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1 Leveraging Task-Parallelism in Energy-Efficient ILU Preconditioners José I. Aliaga
2 Leveraging task-parallelism in energy-efficient ILU preconditioners Universidad Jaime I (Castellón, Spain) José I. Aliaga Manuel F. Dolz Rafael Mayo Enrique S. Quintana-Ortí CIMNE (Barcelona, Spain) Alberto F. Martín
3 Concurrency and energy efficiency 2010 PFLOPS (10 15 flops/sec.) 10 9 core level 2010 JUGENE (PowerPC 450, 850MHz 3.4 GFLOPS) 10 1 node level 10 5 cluster level (Quad-Core) ( nodes)
4 Concurrency and energy efficiency 2010 PFLOPS (10 15 flops/sec.) 2020 EFLOPS (10 18 flops/sec.) 10 9 core level 2010 JUGENE (PowerPC 450, 850MHz 3.4 GFLOPS) 10 1 node level 10 5 cluster level (Quad-Core) ( nodes) core level 10 3 node level! cluster level
5 Concurrency and energy efficiency Green500 (November 2011*) Rank Green/Top Site, Computer #Cores MFLOPS/W LINPACK (TFLOPS) 1/29 IBM Rochester BlueGene/Q, Power BQC 16C 1.60 GHz MW to EXAFLOPS? ,83 493,47 32/1 RIKEN AICS K Computer Sparc64 VIIIfx (8-core) , , ,60 Most powerful reactor under construction in France Flamanville (EDF, 2017 for US $9 billion): 1,630 MWe *Green500 June 2012 to be released today
6 Concurrency and energy efficiency Green500/Top500 (June 2012) Rank Green/Top Site, Computer #Cores MFLOPS/W LINPACK (TFLOPS) 1/252 DOE/NNSA/LLNL BlueGene/Q, Power BQC 16C 1.6GHz MW to EXAFLOPS? 8,192 2, ,35 475,99 20/1 DOE/NNSA/LLNL BlueGene/Q, Power BQC 16C 1.6GHz 1,572,864 2, ,324,75 483,31 Most powerful reactor under construction in France Flamanville (EDF, 2017 for US $9 billion): 1,630 MWe
7 Concurrency and energy efficiency Reduce energy consumption! Costs over lifetime of an HPC facility often exceed acquisition costs Carbon dioxide is a hazard for health and environment Heat reduces hw reliability Personal view Hardware features energy saving mechanism Scientific apps are in general energy oblivious
8 Outline Introduction ILUPACK Experimental setup Power model Leveraging P-states Leveraging C-states Conclusions
9 ILUPACK Incomplete LU Package ( Numerical solution of large sparse linear systems (Ax=b) Iterative Krylov subspace methods (CG, GMRES) Multilevel ILU preconditioners for general/symmetric/hermitian positive definite systems Incorporate the inverse-based approach to the factorization, to control the growth of inverse triangular factors Specially competitive for linear systems from 3D PDEs
10 ILUPACK Factorization of a five-point matrix arising from Laplace PDE discretization.
11 ILUPACK Multi-threaded version (task parallelism) Real s.p.d. systems Construction of preconditioner and PCG solver Algebraic parallelization based on a task tree Leverage task parallelism of the tree Dynamic scheduling via runtime (OpenMP) Exploiting thread-level parallelism in the iterative solution of sparse linear systems. J. I. Aliaga, M. Bollhöfer, A. F. Martín, E. S. Quintana- Ortí. Parallel Computing, 2011
12 ILUPACK Multi-threaded version (task parallelism) P T AP G A Task Tree
13 ILUPACK Multi-threaded version (task parallelism) Run-time in charge of scheduling by demand
14 Experimental setup 2 AMD Opteron 6128 processors (16 cores) 48 GB of RAM DVFS enabled per core (P-states) C-states: C0: normal operation mode C1, C1E: disable core components (L1/L2 caches), clock signal, mem. controller, increases energy savings at the expense of recovery time
15 Experimental setup Sparse linear system benchmark Laplacian PDE equation Δu = f in a 3D unit cube Ω= [0,1] 3 with Dirichlet boundary conditions = on Ω. For the discretization, o o Ω replaced by NxNxN uniform grid approximated by centered finite differences Linear system Au = b with A n x n, o o N = 252, n = million unknowns 111 millions of nonzero entries
16 Cost of energy Setup DC powermeter with sampling freq. = 25 Hz LEM HXS 20-NP transductors with PIC microcontroller RS232 serial port Only 12 V lines
17 Power model!"# = $ %& '(# ) *+,# = % ) $! -.# ) /01!(-.# * is the power dissipated by CPU (socket): $ ) / $ is the static power / is dynamic power % is the power of remaining components (e.g., RAM) Considerations: / changes with the number of active cores % and $ are constants (though $ grows with temperature) Hot system
18 Power model System power: = % ) $ ) / Estimated as idle power Due to off-chip components: e.g., RAM (only mainboard) % 2 = W
19 Power model CPU power: = % ) $ ) / Busy-wait loops For each P-state and c Linear regression = 6 ) 7 9 where 6 = % ) $ 7 9 = /
20 Power model Static power: = % ) $ ) / 0 9 = 6 0 ) = ) 9.12 c W $ = % = = W
21 Power model Dynamic power: = % ) $ ) / 0 9 = 6 0 ) = ) 9.12 c W Busy-wait: / = 9.12 c W 0
22 Power model To analyze the goodness of the α and β values we made an additional analysis. The static and dynamic power satisfied that A 9 We have defined the variation operator as B - = B - = B C /B C
23 Power model Remember, % 2 is constant Thus, e.g., moving all cores from C to E 1 16 = % ) $ # )/ 016# # = W These values agree within 2.5% with the linear regression models
24 Power model Leveraging P-states DVFS = P-states (see ACPI standard) Moving to a more power-friendly state results in power power = energy? For a compute-bounded operation, A - is linear to performance and time -1 In principle, for a memory-bounded operation (ILUPACK), decreasing A - should not affect time!
25 Power model Leveraging P-states 1st attempt: Dynamic Static voltage-frequency scaling Why?
26 Power model Leveraging P-states 1st attempt: Dynamic Static voltage-frequency scaling Combined effect of linear decrease of CPU performance and memory bandwidth!
27 Power model Leveraging P-states 2nd attempt: DVFS during idle periods
28 Power model Leveraging P-states 2nd attempt: DVFS during idle periods Why?
29 Power model Levaraging P-states 2nd attempt DVFS during idle periods by demand
30 Power model Leveraging P-states Active polling for work
31 Power model Leveraging P- and C-states 3rd attempt: DVFS and idle-wait
32 Power model Leveraging P- and C-states 3rd attempt: DVFS and idle-wait: Savings of 6.92% of total energy Negligible impact on execution time but take into account that Idle time: 23.70% Dynamic power: 39.32% Upper bound of savings: = 9.32%
33 Performance and energy consumption Summary A battle to be won in the core arena More concurrency Heterogeneous designs A related battle to be won in the power arena Do nothing, efficiently (V. Pallipadi, A. Belay) or Doing nothing well (D. E. Culler) Don t forget the cost of system+static power
34 More information Energy-aware dense and sparse linear algebra, P. Alonso, M.F. Dolz, R. Mayo, E.S. Quintana. PMAA London (UK) Modeling power and energy of the task-parallel Cholesky factorization on multicore processors, P. Alonso, M. F. Dolz, R. Mayo, E. S. Quintana-Ortí. EnaHPC Hamburg (Germany) Energy-efficient execution of dense linear algebra algorithms on multicore processors. P. Alonso, M. F. Dolz, R. Mayo, E. S. Quintana-Ortí. Cluster Computing, 2012
35 Leveraging Task-Parallelism in Energy-Efficient ILU Preconditioners Thanks for your attention! Any question?
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